DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 06/18/2024 and 05/12/2025 were filed before the first action on the merits. The submissions are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 9-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lilak et al. (2020/0411433). Re claim 1, Lilak teaches a method (Figs. 2-11) comprising: forming a complementary Field-Effect Transistor (CFET) (201) comprising: forming a first FinFET (206) comprising: forming at least one semiconductor fin (110A) having a first total count (“3”, Fig. 2/11); and forming a first gate stack (150) on the at least one semiconductor fin (110); and forming a second FinFET (205) vertically aligned to the first FinFET (Fig. 2/11), the forming the second FinFET (205) comprising: forming a plurality of semiconductor fins (210A-C), wherein the plurality of semiconductor fins (210A-C) have a second total count (“4 fins”) greater than the first total count (“3 fins”); and forming a second gate stack (273) on the plurality of semiconductor fins (210A-C).
Re claim 9, Lilak teaches the method of claim 1, wherein a first one of the first FinFET and the second FinFET are formed in a first wafer (Figs. 4-11), and the method further comprises: bonding a second wafer to the first wafer, wherein the second wafer comprises a semiconductor layer ([64], Fig. 8); and forming a second one of the first FinFET and the second FinFET based on the semiconductor layer ([64], Fig. 8).
Re claim 10, Lilak teaches the method of claim 1, wherein a first gate electrode in the first gate stack is electrically connected to a second gate electrode in the second gate stack ([51-53], Figs. 2, 11).
Re claim 11, Lilak teaches the method of claim 10, wherein the first gate electrode and the second gate electrode are formed as portions of a continuous homogeneous conductive region [45-46].
Re claim 12, Lilak teaches the method of claim 11, wherein the first FinFET is separated from the second FinFET by a dielectric layer (191), and the method further comprises: forming a gate via (177) in the dielectric layer (191), wherein the second gate electrode is connected to the first gate electrode (Figs. 2, 11) through the gate via (177).
Claim(s) 13 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lilak et al. (2020/0411433).
Re claim 13, Lilak teaches a structure (Fig. 2) comprising: a first FinFET (206) comprising: at least one semiconductor fin (110); and a first gate stack (150) on the at least one semiconductor fin (110); and a second FinFET (205) vertically aligned to the first FinFET (206), the second FinFET (205) comprising: a plurality of semiconductor fins (210), wherein the plurality of semiconductor fins (210) have a second total count (“4 fins”) greater than the first total count (“3 fins”); and a second gate stack (273) on the plurality of semiconductor fins (210).
Claim(s) 18 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lilak et al. (2020/0411433).
Re claim 18, Lilak teaches a structure (Fig. 2) comprising: a lower FinFET (205) comprising: at least one semiconductor fin (210A); a dielectric fin (280); a first gate dielectric (211) on the at least one semiconductor fin (210A); and a first gate electrode (273) on the first gate dielectric (211), wherein the first gate electrode (273) comprises portions on opposite sides of the at least one semiconductor fin (210A) and the dielectric fin (280); and an upper FinFET (206) comprising: a plurality of semiconductor fins (110A-C) overlapping the at least one semiconductor fin (210A); an additional semiconductor fin (110B) overlapping the dielectric fin (280); a second gate dielectric on the plurality of semiconductor fins [41-43]; and a second gate electrode (150) on the second gate dielectric [41-43], wherein the second gate electrode (150) comprises portions on opposite sides of the plurality of semiconductor fins and the additional semiconductor fin (Fig. 2).
Allowable Subject Matter
Claims 2-8, 14-17 and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Re claim 2, Lilak teaches the method of claim 1, yet remains explicitly silent to wherein the second FinFET overlaps the first FinFET, and wherein the forming the at least one semiconductor fin comprises performing a bottom fin-cut process to remove a fin in the at least one semiconductor fin.
Claims 3-6 are objected to for at least depending from objected claim 2.
Re claim 7, Lilak teaches the method of claim 1, yet remains explicitly silent to wherein the first FinFET overlaps the second FinFET, and wherein the forming the at least one semiconductor fin comprises a top fin-cut process. Claim 8 is objected to for at least depending from objected claim 7.
Re claim 14, Lilak teaches the structure of claim 13, yet remains explicitly silent to wherein the second FinFET overlaps the first FinFET, and wherein the first FinFET comprises a dielectric fin overlapped by a semiconductor fin in the plurality of semiconductor fins.
Claims 15-17 are objected to for at least depending from objected claim 14. Re claim 19, Lilak teaches the structure of claim 18, yet remains explicitly silent to wherein in a cross-sectional view of the structure, the second gate dielectric comprises a plurality of discrete portions, each encircling one of the plurality of semiconductor fins, and the first gate dielectric is free from portions contacting the dielectric fin. Re claim 20, Lilak teaches the structure of claim 18, yet remains explicitly silent to wherein the dielectric fin has a same width as one of the at least one semiconductor fin.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM S BOWEN whose telephone number is (571)272-3984. The examiner can normally be reached M-F 9-5.
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/ADAM S BOWEN/Examiner, Art Unit 2897