Prosecution Insights
Last updated: July 17, 2026
Application No. 18/302,987

SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME

Final Rejection §102
Filed
Apr 19, 2023
Examiner
KIM, JAY C
Art Unit
2815
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
2 (Final)
49%
Grant Probability
Moderate
3-4
OA Rounds
3m
Est. Remaining
71%
With Interview

Examiner Intelligence

Grants 49% of resolved cases
49%
Career Allowance Rate
421 granted / 861 resolved
-19.1% vs TC avg
Strong +22% interview lift
Without
With
+21.7%
Interview Lift
resolved cases with interview
Typical timeline
3y 6m
Avg Prosecution
42 currently pending
Career history
921
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
64.7%
+24.7% vs TC avg
§102
8.7%
-31.3% vs TC avg
§112
25.2%
-14.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 861 resolved cases

Office Action

§102
DETAILED ACTION This Office Action is in response to Amendment filed March 3, 2026. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 21 and 23 are rejected under 35 U.S.C. 102(a)(1) or (a)(2) as being anticipated by Su et al. (US 9,735,131) Regarding claims 21 and 23, Su et al. disclose aa method for forming a semiconductor device (Fig. 11A), comprising: forming a first device layer (24; dielectric layer) (col. 2, line 43) on a first substrate (20; carrier) (col. 2, line 32), see Fig. 1, because (a) Applicant does not specifically claim what the “device layer” refers to, and what the “device” is, and (b) therefore, the term “first device layer” can be interpreted to be a layer that is either a part of an unspecified device or an entirety of an unspecified device, in which case, the dielectric layer 24 disclosed by Su et al. can be referred to as the first device layer since it is a part of a device; forming a dielectric structure (48; encapsulating material) (col. 4, line 28) over the first device layer, see Fig. 4, wherein the first device layer is disposed between the first substrate and the dielectric structure; forming a second device layer (structure including Redistribution Lines (RDLs) 52 in Fig. 5) (col. 4, line 48), because (a) Applicant does not specifically claim what the “device layer” refers to, and what the “device” is, and (b) therefore, the term “second device layer” can be interpreted to be a layer that is either a part of an unspecified device or an entirety of an unspecified device, in which case, the structure including the Redistribution Lines (RDLs) 52 in Fig. 5 disclosed by Su et al. can be referred to as the second device layer since it is a part of a device, over the dielectric structure (48), see Fig. 5, wherein the first device layer (24) and the second device layer are disposed on opposite sides of the dielectric structure; providing a first interconnect structure (through-vias 56 inside encapsulating material 66 in Fig. 7, or composite structure including through-vias 56 in Fig. 8) (col. 5, line 34) over the first device layer, see Fig. 8; removing the first substrate (20) to expose the first device layer (24), see Fig. 9; and providing a second interconnect structure (interconnect structure above 24 in Fig. 11A) over the first device layer, see Fig. 11A; wherein a first side of the first interconnect structure (top side of through-vias 56 inside encapsulating material 66 or composite structure including through-vias 56 in Fig. 11A) faces a second side of the first device layer (bottom side of 24 in Fig. 11A) and a second side of the second device layer (bottom side of structure including Redistribution Lines (RDLs) 52 in Fig. 11A), and a first side of the second interconnect structure (bottom side of interconnect structure above 24 in Fig. 11A) faces a first side of the first device layer (top side of 24 in Fig. 11A) and a first side of the second device layer (top side of structure including Redistribution Lines (RDLs) 52 in Fig. 11A) (claim 21), further comprising providing a substrate (structure including dielectric layers 68 in Fig. 11A) in contact with a second side of the first interconnect structure (bottom side of through-vias 56 inside encapsulating material 66 in Fig. 11A, or composite structure including through-vias 56 in Fig. 11A), because (a) Applicants do not specifically claim what “a substrate” refers to, and (b) Merriam-Webster dictionary defines “substrate” as “an underlying support” (claim 23). Allowable Subject Matter Claims 1-4, 6-12 and 26-29 are allowed, because (a) Lee does not disclose that “the vias are electrically connected to both the first interconnect structure and the second interconnect structure” recited on the last two lines of claim 1, and (b) Lee or Su et al. do not disclose the step of “forming a via … partially extending into the first interconnect structure” recited on lines 8-9 of claim 10. Claims 22, 24 and 30 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Response to Arguments Applicant’s arguments with respect to claim 21 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Applicant's amendment necessitated the new ground of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY C KIM whose telephone number is (571) 270-1620. The examiner can normally be reached 8:00 AM - 6:00 PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at (571) 270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JAY C KIM/Primary Examiner, Art Unit 2815 /J. K./Primary Examiner, Art Unit 2815 July 1, 2026
Read full office action

Prosecution Timeline

Apr 19, 2023
Application Filed
Dec 04, 2025
Non-Final Rejection mailed — §102
Mar 03, 2026
Response Filed
Jul 07, 2026
Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12685044
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, METHOD OF PROCESSING SUBSTRATE, SUBSTRATE PROCESSING APPARATUS, AND RECORDING MEDIUM
4y 10m to grant Granted Jul 14, 2026
Patent 12672528
METHOD OF FABRICATING SEMICONDUCTOR DEVICE
4y 3m to grant Granted Jun 30, 2026
Patent 12666611
METHOD FOR MANUFACTURING HIGH-DENSITY THREE-DIMENSIONAL PROGRAMMABLE MEMORY
3y 10m to grant Granted Jun 23, 2026
Patent 12648405
METHOD OF MANUFACTURING SEMICONDUCTOR SUBSTRATE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
2y 12m to grant Granted Jun 02, 2026
Patent 12615923
ORGANIC LIGHT-EMITTING DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME
5y 3m to grant Granted Apr 28, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
49%
Grant Probability
71%
With Interview (+21.7%)
3y 6m (~3m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 861 resolved cases by this examiner. Grant probability derived from career allowance rate.

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