DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I (claims 1-14 and 21-26) in the reply filed on 01/12/0226 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 6, 21, 22, and 23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Qi (Qi et al., “Ferroelectricity of as-deposited HZO fabricated by plasma-enhanced atomic layer deposition at 300C by inserting TiO2 interlayers, “Appl. Phys. Lett. 118, 032906 (2021)).
Regarding claim 1, Qi discloses a method, comprising: forming a first electrode layer (Fig.1, “TiN”) over a substrate (“Si”); forming an interfacial layer (TiO2) on the first electrode layer (TiN), wherein the interfacial layer is formed such that the interfacial layer has a centrosymmetric crystal structure (TiO2); forming a ferroelectric layer (HZO) on the interfacial layer (TO2); and forming a second electrode layer (TiN) over the ferroelectric layer (HZO).
Regarding claim 2, Qi discloses wherein forming the ferroelectric layer comprises: forming the ferroelectric layer such that the ferroelectric layer (HZO) has a non- centrosymmetric crystal structure (Fig.3; page 118, column 1, paragraph 1).
Regarding claim 3, Qi discloses wherein the centrosymmetric crystal structure promotes formation of an orthorhombic phase in the ferroelectric layer (Fig.3; page 118, column 1, paragraph 1).
Regarding claim 4, Qi discloses wherein forming the interfacial layer comprises: forming the interfacial layer such that a grain size of the interfacial layer promotes formation of an orthorhombic phase in the ferroelectric layer (page 118, column 2, paragraph 1).
Regarding claim 6, Qi discloses wherein forming the interfacial layer comprises: forming the interfacial layer to a thickness that is included in a range of approximately 0.5 nanometers to approximately 3 nanometers (page 118, column 1, paragraph 3).
Regarding claim 21, Qi discloses a method of forming a ferroelectric tunnel junction (FTJ) structure, the method comprising: forming a bottom electrode (Fig.1, “TiN”); forming a top electrode (Fig.1, “TiN”) above the bottom electrode; forming an interfacial layer (Fig.1, “TiO2”) between the bottom electrode and the top electrode, wherein the interfacial layer has a centrosymmetric crystal structure (page 11, column 2, paragraph 1); and forming a ferroelectric layer (Fig.1, “HZO”) between the bottom electrode and the top electrode, and vertically adjacent with the interfacial layer, wherein the ferroelectric layer has a non-centrosymmetric crystal structure (Fig.3; page 118, column 1, paragraph 1).
Regarding claim 22, Qi discloses wherein the interfacial layer is below the ferroelectric layer (Fig.1).
Regarding claim 23, Qi discloses wherein the interfacial layer is above the ferroelectric layer (Fig.1).
Claim 8 is rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Lu (US 2021/0005734).
Regarding claim 8, Lu discloses a method, comprising: forming a seed layer (Fig.3E, numeral 20) over a substrate (10); forming a first plurality of layers (25) of an interfacial layer on the seed layer (20) ([0056]; note: ALD deposition), wherein the seed layer promotes forming the interfacial layer to a grain size in a particular grain size range ([0056]); and forming a second plurality of layers (30A), (30B) of a ferroelectric layer on the interfacial layer ([0060]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim5 is rejected under 35 U.S.C. 103 as being unpatentable over Qi.
Regarding claim 5, Qi does not disclose wherein forming the interfacial layer comprises: forming the interfacial layer such that a grain size of the interfacial layer is included in a range of approximately 2 nanometers to approximately 10 nanometers.
Qi however discloses that grain structure of an interfacial layer affects the orthorhombic phase in a ferroelectric layer (page 118, column 2, paragraph 1).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was field to adjust the grain size in the interfacial layer to be in the claimed range for the purpose of optimization ferroelectric properties in the ferroelectric layer (Qi, page 118, column 2, paragraph 1, paragraph 3).
Claim(s) 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Lu as applied to claim 8 above, and further in view of Lee (US 2021/0335799).
Regarding claim 12, Lu does not disclose wherein forming the first plurality of layers of the interfacial layer comprises: forming the first plurality of layers of the interfacial layer such that the interfacial layer has a centrosymmetric crystal structure, wherein the centrosymmetric crystal structure promotes formation of a non-centrosymmetric crystal structure in the ferroelectric layer.
Lee however discloses wherein forming the first plurality of layers of the interfacial layer comprises: forming the first plurality of layers of the interfacial layer (Fig.2A, numeral 110) such that the interfacial layer has a centrosymmetric crystal structure, wherein the centrosymmetric crystal structure promotes formation of a non-centrosymmetric crystal structure in the ferroelectric layer ([0031]; [0034]; [0035]).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Lu with Lee to form wherein forming the first plurality of layers of the interfacial layer comprises: forming the first plurality of layers of the interfacial layer such that the interfacial layer has a centrosymmetric crystal structure, wherein the centrosymmetric crystal structure promotes formation of a non-centrosymmetric crystal structure in the ferroelectric layer for the purpose improving ferroelectric properties of the ferroelectric layer (Lee, [0035]).
Regarding claim 13, Lu does not disclose wherein forming the interfacial layer to the grain size in the particular grain size range promotes formation of the ferroelectric layer such that the ferroelectric layer has a grain size that is included in a range of approximately 2 nanometers to approximately 15 nanometers.
Lee discloses forming the interfacial layer to the grain size in the particular grain size range promotes formation of the ferroelectric layer such that the ferroelectric layer has a grain size that is included in a range of approximately 2 nanometers to approximately 15 nanometers ([0034]).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Lu with Lee to form the interfacial layer to the grain size in the particular grain size range promotes formation of the ferroelectric layer such that the ferroelectric layer has a grain size that is included in a range of approximately 2 nanometers to approximately 15 nanometers for the purpose of improving ferroelectric properties of the ferroelectric layer (Lee, [0035]).
Regarding claim 14, Lu does not disclose wherein forming the interfacial layer to the grain size in the particular grain size range promotes formation of the ferroelectric layer such that the ferroelectric layer has a grain size that promotes formation of an orthorhombic phase in the ferroelectric layer.
Lee however discloses wherein forming the interfacial layer to the grain size in the particular grain size range promotes formation of the ferroelectric layer such that the ferroelectric layer has a grain size that promotes formation of an orthorhombic phase in the ferroelectric layer ([0034]).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Lu with Lee to form the interfacial layer to the grain size in the particular grain size range promotes formation of the ferroelectric layer such that the ferroelectric layer has a grain size that promotes formation of an orthorhombic phase in the ferroelectric layer for the purpose of improving device performance (Lee, [0034]).
Claim(s) 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Qi as applied to claim 21 above, and further in view of Boeske (US 2009/0057737).
Regarding claim 24, Qi does not disclose wherein the bottom electrode, the top electrode, the interfacial layer, and the ferroelectric layer are arranged in a deep trench configuration that extends below a top surface of a substrate.
Heo however discloses wherein the bottom electrode, the top electrode, the interfacial layer, and the ferroelectric layer are arranged in a deep trench configuration that extends below a top surface of a substrate (Fig.2C).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Qi with Boeske to have the bottom electrode, the top electrode, the interfacial layer, and the ferroelectric layer are arranged in a deep trench configuration that extends below a top surface of a substrate for the purpose of fabrication a trench capacitor structure (Boeske, [0030]).
Claim(s) 7 and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Qi as applied to claims 1 and 21 above, and further in view of Jeon (US 2021/0202508).
Regarding claim 7, Qi does not disclose forming the interfacial layer such that the interfacial layer includes a material that has a dielectric constant that is included in a range of approximately 5 to approximately 50.
Jeon however discloses forming the interfacial layer such that the interfacial layer includes a material that has a dielectric constant that is included in a range of approximately 5 to approximately 50 ([0076]; note: hafnium oxide).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was field to modify Qi with Jeon to have the interfacial layer such that the interfacial layer includes a material that has a dielectric constant that is included in a range of approximately 5 to approximately 50 because this material is an alternative material for increasing remnant polarization in a ferroelectric layer (Jeon, [0077]).
Regarding claim 25, Qi does not disclose wherein the FTJ structure is included in a memory cell structure; and wherein the FTJ structure is electrically connected with a source/drain region of a transistor of the memory cell structure.
Jeon however discloses the FTJ structure is included in a memory cell structure; and wherein the FTJ structure is electrically connected with a source/drain region of a transistor of the memory cell structure (Fig. 4).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Qi with Jeon to include the FTJ structure in a memory cell structure; and wherein the FTJ structure is electrically connected with a source/drain region of a transistor of the memory cell structure for the purpose of fabrication a ferroelectric memory device (Jeon, [0091]).
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Qi as applied to claim 21 above, and further in view of Ando (US 9, 793, 397).
Regarding claim 26, Qi does not disclose wherein the FTJ structure is included in a ferroelectric field effect transistor (FeFET) structure of a memory cell structure; wherein the bottom electrode corresponds to a channel layer of the FeFET structure; wherein the top electrode corresponds to a gate electrode of the FeFET structure; wherein the interfacial layer corresponds to a gate dielectric layer of the FeFET structure; and wherein the ferroelectric layer corresponds to a ferroelectric switching layer of the FeFET structure.
Ando discloses wherein the FTJ structure is included in a ferroelectric field effect transistor (FeFET) structure of a memory cell structure; wherein the bottom electrode corresponds to a channel layer (Fig. 2, numeral 210) of the FeFET structure; wherein the top electrode corresponds to a gate electrode (280’) of the FeFET structure; wherein the interfacial layer corresponds to a gate dielectric layer (220) of the FeFET structure; and wherein the ferroelectric layer (250) corresponds to a ferroelectric switching layer of the FeFET structure.
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Qi with Ando to have the FTJ structure included in a ferroelectric field effect transistor (FeFET) structure of a memory cell structure; wherein the bottom electrode corresponds to a channel layer of the FeFET structure; wherein the top electrode corresponds to a gate electrode of the FeFET structure; wherein the interfacial layer corresponds to a gate dielectric layer of the FeFET structure; and wherein the ferroelectric layer corresponds to a ferroelectric switching layer of the FeFET structure for the purpose a semiconductor device with improved performance (column 1, lines 12-20).
Allowable Subject Matter
Claims 9-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the search of the prior art does not disclose or reasonably suggest wherein forming the first plurality of layers of the interfacial layer comprises: forming a first layer, of the first plurality of layers, on the seed layer; annealing the first layer after forming the first layer; forming a second layer, of the first plurality of layers, on the first layer; and annealing the second layer after forming the second layer as required by claim 9.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JULIA SLUTSKER whose telephone number is (571)270-3849. The examiner can normally be reached Monday-Friday, 9 am-6 pm.
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/JULIA SLUTSKER/Primary Examiner, Art Unit 2891