DETAILED ACTION
This office action is in response to the amendments filed on November 10, 2025. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgement
The present office action is made with all the suggested amendments being fully considered. Accordingly, claims 1-20 are currently pending in this application.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on April 19, 2023 is being considered by the examiner.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2, 4, 10-12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites the limitation "the electrode" in the 2nd line of the claim. There is insufficient antecedent basis for this limitation in the claim. For consistency in the claim, the examiner suggests the applicant to use “the conductive electrode.”
Claim 4 recites the limitation "the electrode" in the 2nd line of the claim. There is insufficient antecedent basis for this limitation in the claim. For consistency in the claim, the examiner suggests the applicant to use “the conductive electrode.”
Claim 10 recites the limitation "the electrode" in the 2nd line of the claim. There is insufficient antecedent basis for this limitation in the claim. For consistency in the claim, the examiner suggests the applicant to use “the conductive electrode.”
Claims 11-12, depend from Claim 10, thus inherit the deficiencies identified supra. Appropriate correction is required.
Claim 12 recites the limitation "the electrode" in the 2nd line of the claim. There is insufficient antecedent basis for this limitation in the claim. For consistency in the claim, the examiner suggests the applicant to use “the conductive electrode.”
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 8-9, 13-20 are rejected under 35 U.S.C. 103 as being unpatentable over Koyanagi (US 2009/0149023) in view of Kwon (US 8,399,987).
With respect to Claim 1, Koyanagi shows (Fig. 1-5) most aspects of the current invention including a method, comprising
providing a semiconductor substrate (11) having a front surface coated with an interconnect structure (30), a rear surface opposite to the front surface, and a first via (13) extending into the substrate along a first direction that is transverse to the front surface, the first via comprising a silicon conductive core (15) and a silicon oxide insulating sheath (14) covering the core and electrically insulating the core from the substrate
etching the substrate from the rear surface selectively over the insulating sheath to expose a portion of the first via from the rear surface of the substrate, the portion having a first height along the first direction; (Fig 2-3)
depositing a silicon oxide insulating layer (41) on the rear surface, the insulating layer surmounting the exposed portion of the first via, (Fig 3)
polishing the insulating layer and a portion of the insulating sheath developing along a second direction parallel to the first direction to expose the conductive core of the first via, the polishing leaving a second thickness of the insulating layer on the rear surface; (Fig 4)
forming a conductive electrode (42) on the rear surface and in contact with the core of the first via
Additionally, although Koyanagi depicts the silicon oxide insulating layer on the rear surface, and the insulating layer higher than the first height of the exposed portion of the first via, Koyanagi fails to explicitly disclose the insulating layer having a first thickness along the first direction greater than the first height of the exposed portion of the first via.
On the other hand, and in the same field of endeavor, Kwon teaches (Fig 15A-15E) a method, comprising forming a semiconductor substrate (10) comprising a front surface (11) and a rear surface (12) opposite to the front surface, a first via (16) extending into the substrate along a first direction that is transverse to the front surface, etching the substrate from the rear surface to expose a portion of the first via from the rear surface of the substrate, depositing a silicon oxide insulating layer (30) on the rear surface, the insulating layer surmounting the exposed portion of the first via, the insulating layer having a first thickness along the first direction greater than the first height of the exposed portion of the first via. Kwon teaches the silicon oxide insulating layer serves to reduce or prevent the second side of the substrate/die from being contaminated with a conductive material during an exposure process.
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have the insulating layer having a first thickness along the first direction greater than the first height of the exposed portion of the first via, in the device of Koyanagi, as taught by Kwon because the silicon oxide insulating layer serves to reduce or prevent the second side of the substrate/die from being contaminated with a conductive material during an exposure process.
With respect to Claim 2, Koyanagi shows (Fig. 1-5) wherein the forming of the conductive electrode includes depositing a conductive layer on the insulating layer and in contact with the core of the first via, and removing/etching a portion of the conductive layer.
With respect to Claim 3, Koyanagi shows (Fig. 1-5) wherein the insulating layer (41) is deposited on the rear surface of the substrate and the protruding portion of the first via.
With respect to Claim 4, Kwon teaches (Fig 15A-15E) the method further comprising between the polishing and the forming of the conductive electrode (60; see Fig 15E), an etching of a portion of the core of the first via, the etching being implemented on the side of the rear surface and being selective over the sheath and over the insulating layer. Additionally, Kwon teaches an embodiment (see Fig 21A-21B) wherein the method further comprising between the polishing and the forming of the conductive electrode (66; see Fig 21B), an etching of a portion of the core of the first via, the etching being implemented on the side of the rear surface and being selective over the sheath and over the insulating layer.
With respect to Claim 8 Koyanagi shows (Fig. 1-5) wherein the insulating sheath of the first via is in contact with the core of the first via.
With respect to Claim 9, Koyanagi shows (Fig. 1-5) most aspects of the current invention including a device, comprising
a semiconductor substrate (11) having a front surface and a rear surface opposite to the front surface,
an interconnect structure (30) coating the front surface
an insulating layer (41) on a first portion of the rear surface
a first via (13) comprising a conductive core (15) covered with an insulating sheath (14), the first via extending into the substrate along a first direction that is transverse to the front surface, the insulating sheath of the first via extending along a sidewall of the first via through the insulating layer and being coplanar with a first surface of the insulating layer opposite to a second surface of the insulating layer,
Additionally, although Koyanagi shows a conductive electrode (42) disposed on the rear surface of the substrate and in contact with the conductive core of the first via, Koyanagi fails to show the conductive core partially extending along a sidewall of the insulating sheath to form a cavity in the first via, and the conductive electrode partially housed in the cavity of the first via.
On the other hand, and in the same field of endeavor, Kwon teaches (Fig 21A-21B) a device, comprising a semiconductor substrate (10) comprising a front surface (11) and a rear surface (12) opposite to the front surface, an insulating layer (30) on a first portion of the rear surface, a first via (16) comprising a conductive core (20) covered with an insulating sheath (22) extending into the substrate along a first direction that is transverse to the front surface, the conductive core partially extending along a sidewall of the insulating sheath to form a cavity (space of the via hole after sacrificial layer 39 is removed) in the first via, a conductive electrode (66) partially housed in the cavity of the first via, the conductive electrode in contact with the conductive core of the first via. Kwon teaches the conductive electrode is used to fill the cavity of the first via and make a stronger direct connection to the conductive core of the first via.
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have the conductive core partially extending along a sidewall of the insulating sheath to form a cavity in the first via, and the conductive electrode partially housed in the cavity of the first via, in the device of Koyanagi, as taught by Kwon because the conductive electrode is used to fill the cavity of the first via and make a stronger direct connection to the conductive core of the first via.
With respect to Claim 13, Koyanagi shows (Fig. 1-5) wherein the insulating sheath of the first via is in contact with the conductive core of the first via.
With respect to Claim 14, Koyanagi shows (Fig. 1-5) wherein the insulating layer includes silicon oxide or silicon nitride.
With respect to Claim 15, Koyanagi shows (Fig. 1-5) wherein the insulating sheath includes silicon oxide or silicon nitride.
With respect to Claim 16, Koyanagi shows (Fig. 1-5) most aspects of the current invention including a device, comprising:
a semiconductor substrate (11) including a front surface and a rear surface opposite to the front surface, the substrate having a first thickness
an interconnect structure (30) on the front surface
an insulating layer (41) having a first surface on the rear surface and a second surface opposite the first surface
a first via (13) extending from the front surface to the second surface of the insulating layer along a first direction, the first direction being transverse to the front surface, the first via including:
a conductive core (15) comprising a first sidewall that is transverse to the front surface and a first surface coplanar with the front surface,
an insulating sheath (14) covering the first sidewall and extending along the first direction from the front surface to the second surface of the insulating layer, the insulating sheath being coplanar with the second surface of the insulating layer
Additionally, although Koyanagi shows a conductive electrode (42) disposed on the rear surface of the substrate and in contact with the conductive core of the first via, Koyanagi fails to show the conductive core having a first length along the first direction that is smaller than the first thickness to form a cavity in the first via at the rear surface of the semiconductor substrate, the conductive electrode partially housed in the cavity of the first via at the rear surface of the semiconductor substrate, the conductive electrode being in contact with the conductive core of the first via.
On the other hand, and in the same field of endeavor, Kwon teaches (Fig 21A-21B) a device, comprising a semiconductor substrate (10) comprising a front surface (11) and a rear surface (12) opposite to the front surface, an insulating layer (30) on a first portion of the rear surface, a first via (16) comprising a conductive core (20) covered with an insulating sheath (22) extending into the substrate along a first direction that is transverse to the front surface, the conductive core having a first length along the first direction that is smaller than the first thickness to form a cavity (space of the via hole after sacrificial layer 39 is removed) in the first via at the rear surface of the semiconductor substrate, a conductive electrode (66) partially housed in the cavity of the first via at the rear surface of the semiconductor substrate, the conductive electrode being in contact with the conductive core of the first via. Kwon teaches the conductive electrode is used to fill the cavity of the first via and make a stronger direct connection to the conductive core of the first via.
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have the conductive core having a first length along the first direction that is smaller than the first thickness to form a cavity in the first via at the rear surface of the semiconductor substrate, the conductive electrode partially housed in the cavity of the first via at the rear surface of the semiconductor substrate, the conductive electrode being in contact with the conductive core of the first via, in the device of Koyanagi, as taught by Kwon because the conductive electrode is used to fill the cavity of the first via and make a stronger direct connection to the conductive core of the first via.
With respect to Claim 17, Kwon teaches (see Fig 15C-15E) an embodiment encompassing a device comprising a conductive electrode (60) partially housed in the cavity of the first via (16) at the rear surface of the semiconductor substrate, the conductive electrode being in contact with the conductive core (20) of the first via, wherein the conductive electrode includes a first portion in contact with the conductive core, and a second portion that is in contact with the insulating layer.
Furthermore, although Kwon teaches the first portion having a first sidewall that is offset with the first sidewall of the conductive core, it is noted that the specification fails to provide teachings about the criticality of the first portion having a first sidewall that is coplanar with the first sidewall of the conductive core.
Therefore, absent any criticality, this limitation is only considered to be an obvious modification of the conductive electrode disclosed by Kwon as the courts have held that a change in shape or configuration, without any criticality, is within the level of skill in the art, as the particular conductive electrode arrangement claimed by applicant is nothing more than one of numerous conductive electrode arrangements that a person having ordinary skill in the art will find obvious to provide using routine experimentation based on its suitability for the intended use of the invention. See In re Daily, 149 USPQ 47 (CCPA 1976).
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to modify the conductive electrode as claimed in the structure of Koyanagi, as suggested by Kwon because the conductive electrode is used to fill the cavity of the first via and make a stronger direct connection to the conductive core of the first via.
With respect to Claim 18, Kwon teaches (see Fig 15C-15E) wherein the conductive core has a first width along a second direction transverse to the first direction and the second portion of the conductive electrode has a second width along the second direction that is greater than the first width.
With respect to Claim 19, Koyanagi shows (Fig. 1-5) wherein the interconnect structure includes a plurality of conductive layers and a plurality of insulating layers.
With respect to Claim 20, Koyanagi shows (Fig. 1-5) wherein the interconnect structure includes a plurality of antireflection layers
Claims 5-7, 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over Koyanagi in view of Kwon and in further view of Agranov (US 2020/0412980).
With respect to Claim 5, Koyanagi in view of Kwon show most aspects of the current invention. However, the combination of references fail to show after the forming of the conductive electrode, a forming of a quantum film on the insulating layer and the conductive electrode.
On the other hand, and in the same field of endeavor, Agranov teaches (Fig 1-3B) a method, comprising a silicon substrate (304) having a front surface and a rear surface opposite to the front surface, a conductive electrode (316) on the rear surface and in contact with a core of a first via (par 78; circuitry formed in substrate to provide control and signal processing for the quantum film; see Fig 7A-7B) and after the forming of the conductive electrode, a forming of a quantum film (302) on the conductive electrode. Agranov teaches advantages of using the quantum film include high absorption of electromagnetic radiation in the target spectral range, high quantum efficiency (QE) in the target spectral range, high uniformity and low crosstalk between pixels, low dark current, flexibility in spectral response tuning, a low operating voltage, and compatibility with complimentary metal-oxide semiconductor (CMOS) imaging processes (par 80).
Accordingly, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have after the forming of the conductive electrode, a forming of a quantum film on the insulating layer and the conductive electrode, in the structure of Koyanagi and Kwon, as suggested by Agranov because advantages of using the quantum film include high absorption of electromagnetic radiation in the target spectral range, high quantum efficiency (QE) in the target spectral range, high uniformity and low crosstalk between pixels, low dark current, flexibility in spectral response tuning, a low operating voltage, and compatibility with complimentary metal-oxide semiconductor (CMOS) imaging processes.
With respect to Claim 6, Koyanagi shows (Fig. 1-5) further comprising forming an additional silicon substrate (2) having a front surface coated with an additional interconnect structure and a rear surface opposite to the front surface of the additional substrate, the rear surface intended to receive light; and forming the interconnect structure on the additional interconnect structure.
With respect to Claim 7, Agranov teaches (Fig 1-3B) wherein the quantum film converts infrared light into electron-hole pairs and the electrode comprises a material transparent to infrared light (par 59 and 71).
With respect to Claim 10, Koyanagi in view of Kwon show most aspects of the current invention. However, the combination of references fail to show a quantum film on the insulating layer and the conductive electrode.
On the other hand, and in the same field of endeavor, Agranov teaches (Fig 1-3B) a device, comprising a silicon substrate (304) having a front surface and a rear surface opposite to the front surface, a conductive electrode (316) on the rear surface and in contact with a core of a first via (par 78; circuitry formed in substrate to provide control and signal processing for the quantum film; see Fig 7A-7B) and a quantum film (302) on the conductive electrode. Agranov teaches advantages of using the quantum film include high absorption of electromagnetic radiation in the target spectral range, high quantum efficiency (QE) in the target spectral range, high uniformity and low crosstalk between pixels, low dark current, flexibility in spectral response tuning, a low operating voltage, and compatibility with complimentary metal-oxide semiconductor (CMOS) imaging processes (par 80).
Accordingly, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have a quantum film on the insulating layer and the conductive electrode, in the structure of Koyanagi and Kwon, as suggested by Agranov because advantages of using the quantum film include high absorption of electromagnetic radiation in the target spectral range, high quantum efficiency (QE) in the target spectral range, high uniformity and low crosstalk between pixels, low dark current, flexibility in spectral response tuning, a low operating voltage, and compatibility with complimentary metal-oxide semiconductor (CMOS) imaging processes.
With respect to Claim 11, Koyanagi shows (Fig. 1-5) further comprising forming an additional silicon substrate (2) having a front surface coated with an additional interconnect structure and a rear surface opposite to the front surface of the additional substrate, the rear surface intended to receive light; and forming the interconnect structure on the additional interconnect structure.
With respect to Claim 12, Agranov teaches (Fig 1-3B) wherein the quantum film converts infrared light into electron-hole pairs and the conductive electrode includes a material transparent to infrared light (par 59 and 71).
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/Q.A.B/ Examiner, Art Unit 2814
/WAEL M FAHMY/ Supervisory Patent Examiner, Art Unit 2814