Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 6-16, 18, and 21-22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chang et al (US 20210384203).
Chang et al teaches
[claim 1] A semiconductor device, comprising: a first transistor, comprising: a first electrical conductor having a first width and extending along a first direction (figures 3 and 4A, paragraphs 0040 and 0044, where element 420A is the first conductor over the first transistor region which extends along the X-direction, which is a first direction);
a first additional electrical conductor having a second width and extending along the first direction, wherein the second width is greater than the first width (figures 3 and 4A, paragraphs 0040 and 0044, where element 391A in the region over element 251 [top of figure 4A] is the first additional electrical conductor having a second width along the X-direction [first direction] where the width in the x-direction of 392B is greater than the width in the x-direction of element 420A);
a first active region extending along a second direction perpendicular to the first direction, wherein the first active region overlaps the first electrical conductor and the first additional electrical conductor from a top view perspective (figures 3, 4A and 4B, paragraphs 0040 and 0044, where element 251 is the first active region which extends in the z-direction [into the page on figures 3 and 4A] which is perpendicular to the first direction [z-direction is perpendicular to x-direction], where the first active region overlaps the first electrical conductor and first additional electrical conductor [element 420A and 391A respectively]);
a second transistor, comprising: a second electrical conductor having the first width and extending along the first direction (figures 3 and 4A, paragraphs 0040 and 0044, where element 420B is the second conductor over the second transistor region which extends along the X-direction, which is a first direction);
a second additional electrical conductor having the second width and extending along the first direction (figures 3 and 4A, 0040 and 0044, where element 392B in the region over element 252 [second from the top of figure 4A] is the second additional electrical conductor having a second width along the X-direction [first direction] where the width in the x-direction of 392B is greater than the width in the x-direction of element 420B);
a second active region extending along the second direction, wherein the second active region overlaps the second electrical conductor and the second additional electrical conductor from the top view perspective (figures 3, 4A and 4B, paragraphs 0040 and 0044, where element 252 is the second active region which extends in the z-direction [into the page on figures 3 and 4A] which is perpendicular to the first direction [z-direction is perpendicular to x-direction], where the second active region overlaps the second electrical conductor and second additional electrical conductor [element 420B and 392B respectively]);),
and the first transistor and the second transistor are disposed at different elevation levels (figure 4A, paragraphs 0040 and 0044, where the first transistor [top of element 4A in the y-direction] is at a different elevation than the second transistor [second to top of figure 4A] where elevation is defined as the y-direction).
[claim 2] The semiconductor device of Claim 1, wherein the first transistor comprises a PMOS transistor, and the second transistor comprises a NMOS transistor (paragraph 0057, where transistors relating to element 251 and 252 [respectively] can be PMOS and NMOS transistors [respectively] as the structure of the memory cells can be set up such that any of the transistors could be NMOS or PMOS).
[claim 3] The semiconductor device of Claim 1, wherein the first electrical conductor and the second electrical conductor are electrically connected to a first voltage or a second voltage (figure 4A, paragraph 0044, where elements 420A and 420B [first and second electrical conductor] are connected to first or second voltage),
the first additional electrical conductor is electrically connected to one of the first voltage and the second voltage, and the second additional electrical conductor is electrically connected to another one of the first voltage and the second voltage (figure 4A, paragraph 0040, where elements 391A and 392B [first and second additional electrical conductor] are connected to a first or second voltage).
[claim 4] The semiconductor device of Claim 3, wherein the first additional electrical conductor is electrically connected to the second voltage, and the second additional electrical conductor is electrically connected to the first voltage (figure 4A, paragraph 0040, where element 391A [first additional electrical conductor] is connected to a second voltage, and element 392B [second additional electrical conductor] is connected to a first voltage).
[claim 6] The semiconductor device of Claim 1, wherein a first projection of the first additional electrical conductor on a plane defined by the first direction and the second direction is separated from a second projection of the second additional electrical conductor on the plane (figure 4A, paragraph 0040, where the plane defined by a first and second direction is the X-Z plane [z-direction is in and out of the page], where element 391A [first additional electrical conductor] in the X-Z plane is separated from element 392B [second additional electrical conductor] in the X-Z plane).
[claim 7] The semiconductor device of Claim 1, further comprising: a plurality of first gates extending along the first direction and overlapping the first active region from the top view perspective (figure 4A, paragraphs 0037-0038, where elements 220A and 240A comprises the plurality of first gates extending along a first direction [X-direction] and overlapping the first active region [element 251] from a top view perspective [perspective of figure 4A]);
and a plurality of second gates extending along the first direction and overlapping the second active region from the top view perspective (figure 4A, paragraphs 0037-0038, where elements 220B and 240B comprises the plurality of first gates extending along a first direction [X-direction] and overlapping the second active region [element 252] from a top view perspective [perspective of figure 4A]);
[claim 8] The semiconductor device of Claim 7, wherein any two adjacent ones of the first gates are spaced apart by a first distance, any two adjacent ones of the second gates are spaced apart by the first distance, and the second width is substantially identical to the first distance (figure 4A, paragraphs 0040 and 0044, where the distance between element 220A and 240A [first plurality of gate electrodes] is the same distance between elements 240B and 220B [second plurality of gates], and said distance is the first distance. The first distance is substantially equal to the second width, defined as the width of element 391A and 392B in the X-direction [as seen visually in figure 4A]).
[claim 9] The semiconductor device of Claim 8, wherein the second width is in a range of 0.5 times the first distance to 1.5 times the first distance (figure 4A, paragraphs 0040 and 0044, where the second width [width of elements 391A and 392B] is between 0.5 and 1.5 the first distance [distance between element 240A and 220A], as seen visually they are roughly the same distance).
[claim 10] A semiconductor device, comprising: a first electrical conductor having a first width and extending along a first direction (figure 4A, paragraphs 0040 and 0044, where element 420A is the first electrical conductor having a first width [defined in the X-direction] and extends in the first direction [Y-direction]);
a plurality of first gates extending along the first direction, wherein any two adjacent ones of the first gates are spaced apart by a first distance (figure 4A, paragraphs 0040 and 0044, where elements 220A and 240A are the first gates both extending in the first direction [Y-direction], whereas the two gates are separated by a first distance in the second direction);
a first additional electrical conductor having a second width and extending along the first direction, wherein the first additional electrical conductor overlaps the first electrical conductor or one of the first gates from a top view perspective (figure 4A, paragraph 0040 and 0044, where element 391A is the first additional electrical conductor having a second width [defined in the X-direction] and extends in a first direction [it has an element that extends in the Y-direction], and it overlaps both the first electrical conductor [420A] and one of the plurality of first gates [220A, 240A]);
and a first active region extending along a second direction perpendicular to the first direction, wherein the first active region overlaps the first electrical conductor from the top view perspective the first gates and the first additional electrical conductor (figure 4A and 4B, paragraph 0028, where element 251 is the first active region extending in a second direction [defined as the Z-direction as seen in figure 4B] and is perpendicular to the first direction [Y-direction], which overlaps the first electrical conductor in a top view perspective [as seen in figure 4A, element 420A overlaps 391A]),
wherein the second width is greater than the first width (figure 4A, paragraphs 0040 and 0044, where the width of element 391A [second width] is greater than the width element 420A [first width]).
[claim 11] The semiconductor device of Claim 10, wherein the second width is different from the first distance (figure 4A, paragraph 0040 and 0044, where the second width [width of element 391A] is different than the first distance between elements 220A and 240A [first distance] – that is they are almost the same but not exactly the same).
[claim 12] The semiconductor device of Claim 10, wherein the second width is in a range of 0.5 times the first distance to 1.5 times the first distance (figure 4A, paragraph 0040 and 0044, where the second width [width of element 391A] is almost equal to first distance between elements 220A and 240A [first distance] – thus being in a range of 0.5 to 1.5 multiplier).
[claim 13] The semiconductor device of Claim 10, further comprising: a second electrical conductor having a first width and extending along the first direction (figure 4A, paragraphs 0040 and 0044, where element 420B is the second electrical conductor having a first width [defined in the X-direction] and extends in the first direction [Y-direction]);
a plurality of second gates extending along the first direction, wherein any two adjacent ones of the second gates are spaced apart by the first distance (figure 4A, paragraphs 0040 and 0044, where elements 220B and 240B are the second gates both extending in the first direction [Y-direction], whereas the two gates are separated by the first distance in the second direction);
a second additional electrical conductor having the second width and extending along the first direction, wherein the first additional electrical conductor overlaps the second electrical conductor or one of the second gates from the top view perspective (figure 4A, paragraph 0040 and 0044, where element 392B is the second additional electrical conductor having the second width [defined in the X-direction] and extends in a first direction [it has an element that extends in the Y-direction], and it overlaps both the second electrical conductor [420B] and one of the plurality of first gates [220B, 240B]);
and a second active region extending along the second direction, wherein the third active region overlaps the second electrical conductor, the second gates and the second additional electrical conductor from the top view perspective (figure 4A and 4B, paragraph 0028, where element 252 is the second active region extending in a second direction [defined as the Z-direction as seen in figure 4B] and is perpendicular to the first direction [Y-direction], which overlaps the second electrical conductor in a top view perspective [as seen in figure 4A, element 420B overlaps 392B]),
wherein the second width is greater than the first width, and the second width is substantially identical to the first distance (figure 4A, paragraphs 0040 and 0044, where the width of element 392B [second width] is greater than the width element 420B [first width], and the second width is essentially identical to the first distance [distance between 220B and 240B]).
[claim 14] The semiconductor device of Claim 13, further comprising: a first transistor, comprising the first electrical conductor, the first gates, the first additional electrical conductor and the first active region (figure 4A, paragraphs 0038, 0040, 0044, where the first transistor comprises the first electrical conductor [420A], the first gates [220A, 240A], the first additional electrical conductor [391A] and the first active region [251]),
and a second transistor, comprising the second electrical conductor, the second gates, the second additional electrical conductor and the second active region (figure 4A, paragraphs 0038, 0040, 0044, where the second transistor comprises the second electrical conductor [420B], the second gates [220B, 240B], the second additional electrical conductor [392B] and the second active region [252]),
wherein a conductive type of the first transistor is different from that of the second transistor (paragraph 0057, where transistors relating to element 251 and 252 [respectively] can be PMOS and NMOS transistors [respectively] as the structure of the memory cells can be set up such that any of the transistors could be NMOS or PMOS).
[claim 15] The semiconductor device of Claim 14, wherein the first transistor is formed above the second transistor along a third direction perpendicular to the first direction and the second direction (figure 4A, paragraph 0038, where the X-direction is the third direction, and if the device of figure 4A is rotated 90 degress clockwise, the first transistor [220A, 240A, 420A, 391A, 251] is located above the second transistor [220B, 240B, 420B, 392B, 252]).
[claim 16] The semiconductor device of Claim 13, wherein the first additional electrical conductor and the second additional electrical conductor are electrically connected to different voltages (figure 4A, paragraph 0040, where elements 391A [first additional electrical conductor] and element 392B [second additional electrical conductor] are connected to different voltages [connected to different gate lines for different transistors for different function]).
[claim 18] The semiconductor device of Claim 13, wherein a first projection of the first additional electrical conductor on a plane defined by the first direction and the second direction is spaced apart from a second projection of the second additional electrical conductor on the plane (figure 4A, paragraph 0038, where the first direction and second direction comprise the Y-Z plane, and elements 391A and 392B are separated from each other in the Y-Z plane).
[claim 21] A semiconductor device, comprising: a first electrical conductor having a first width and extending along a first direction (figure 4A, paragraph 0040, where element 420A is the first electrical conductor with a first width [in the x-direction] extending in the first direction [y-direction]);
a first active region extending along a second direction perpendicular to the first direction, wherein the first active region overlaps the first electrical conductor from a top view perspective (figures 4A and 4B, paragraph 0040 and 0044, where element 251 is the first active region extending along a second direction [z-direction] which is perpendicular to the y-direction, and the first electrical conductor [420A] overlaps the first active region [251] from a top down perspective [view of figure 4A]);
a plurality of first gates extending along the first direction and overlapping the first active region from the top view perspective (figure 4A, paragraph 0038, where elements 220A and 240A is the plurality of first gates extending in the first direction [y-direction] and overlaps the first active region [element 251] from a top down perspective [as seen in figure 4A]);
a second electrical conductor having the first width and extending along the first direction (figure 4A, paragraph 0040, where element 420B is the second electrical conductor having a first width [in the x-direction] and extending along a first direction [y-direction]);
a second active region extending along the second direction, wherein the second active region overlaps the second electrical conductor from the top view perspective (figures 4A and 4B, paragraph 0040 and 0044, where element 252 is the second active region along a second direction [z-direction] and overlaps the second electrical conductor [element 420B] in a top down perspective [as seen in figure 4A]);
and a plurality of second gates extending along the first direction and overlapping the second active region from the top view perspective (figure 4A, paragraph 0040 and 0044, where the plurality of second gates are elements 240B and 220B extending along a first direction [y-direction] and overlaps a second active region [element 252] from a top down perspective [as seen in figure 4A]).
[claim 22] The semiconductor device of Claim 21, wherein any two adjacent ones of the first gates are spaced apart by a first distance, any two adjacent ones of the second gates are spaced apart by the first distance (figure 4A, paragraph 0040 and 0044, where elements 220A and 240A comprises the plurality of first gates with a first distance between the two gate lines, and the second gates which are elements 240B and 220B which are separated by the first distance).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al (US 20210384203).
Change et al teaches all of the limitations of the parent claims, claims 1 and 13, but does not specifically disclose
[claim 5] The semiconductor device of Claim 1, wherein a first projection of the first additional electrical conductor on a plane defined by the first direction and the second direction overlaps a second projection of the second additional electrical conductor on the plane.
[claim 17] The semiconductor device of Claim 13, wherein a first projection of the first additional electrical conductor on a plane defined by the first direction and the second direction overlaps a second projection of the second additional electrical conductor on the plane.
However, according to MPEP 2144.04 VI. REVERSAL, DUPLICATION, OR REARRANGEMENT OF PARTS
C. Rearrangement of Parts
In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950) (Claims to a hydraulic power press which read on the prior art except with regard to the position of the starting switch were held unpatentable because shifting the position of the starting switch would not have modified the operation of the device.); In re Kuhle, 526 F.2d 553, 188 USPQ 7 (CCPA 1975) (the particular placement of a contact in a conductivity measuring device was held to be an obvious matter of design choice).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Chang et al to re-arrange the first and second additional electrical contacts to overlap each-other in the plane between the first and second directions to maximize spatial density of the device, and moving said parts does not change the function of the device but rather simply re-arranges one portion to be closer together such that there is an overlap.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Buckley et al (US 20230282710), Shimizu et al (US 20230104041), Lai et al (US 20230067311), Chen et al (US 20220278092), Chang et al (US 20210202505), Chang et al (US 20210173995), Chang et al (US 20200058634), and Kim et al (US 20190148547).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDREW ZABEL whose telephone number is (703)756-4788. The examiner can normally be reached M-F 9-5PM ET.
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/ANDREW JOHN ZABEL/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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