4Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
Claim(s) 24-28 and 37 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Link (US Patent No. 11824013).
Regarding claim 24, Link teaches A method of fabricating a substrate for a semiconductor package, comprising: bonding a first sheet, a second sheet, and a third sheet to form a stack, wherein the third sheet is located between the first sheet and the second sheet in the stack, the first sheet comprises a first coefficient of thermal expansion (CTE), the second sheet comprises a second CTE, and the third sheet comprises a third CTE, the first CTE is lower than the second CTE and the third CTE is between the first CTE and the second CTE (Fig. 2, Col. 2, lines 39-43, Col. 5, lines 62-64, and Col. 9, lines 54-59 point to a substrate 12 (package substrate) comprising a first buildup material 26 (first sheet) with a CTE of about 3 ppm/° C, a second buildup material 46 (second sheet) with a CTE of about 20 ppm/° C, and a core 18 (third sheet) with a coefficient of thermal expansion of about 3.2 ppm/° C, which make up a laminated, multi-layer structure.); forming openings through the first sheet, the second sheet and the third sheet (Fig. 2 points to vias 24, through-core vias 34, and vias 44.); depositing a conductive material within the openings through the first sheet, the second sheet and the third sheet to provide conductive vias extending through the stack (Id. points to conductive materials 22 and 42, which are electrically connected by the through-core vias 34.); forming a first redistribution layer comprising first conductive interconnect structures within a first insulating material over a first side of the stack; and forming a second redistribution layer comprising second conductive features within a second insulating material over a second side of the stack, wherein the conductive vias extending through the stack electrically connect the first conductive interconnect structures of the first redistribution layer with the second conductive interconnect structures of the second redistribution layer (Id. points to the solder masks 32 (first redistribution layer; second redistribution layer).).
Regarding claim 25, Link teaches wherein the first sheet, the second sheet and the third sheet are bonded using an adhesive (Col. 6, lines 37-40 point to embodiments where each of the first and second buildup materials 26 (first sheet) and 46 (second sheet) can be a buildup film suitable for flexible circuits, such as an epoxy, polyimide, polyester, or other polymer or combination of polymers (adhesive).).
Regarding claim 26, Link teaches wherein the first sheet comprises a first laminate reinforced resin sheet, the second sheet comprises a second laminate reinforced resin sheet and the third sheet comprises a third laminate reinforced resin sheet, and the adhesive comprises a partially-cured epoxy resin located between the first laminate reinforced resin sheet and the third laminate reinforced resin sheet (Fig. 2 and Col. 5, lines 62-64 point to a substrate 12 (package substrate) comprising a core 18 (hybrid substrate core), a first buildup material 26 (first portion; first laminate reinforced resin sheet), and a second buildup material 46 (second portion; second laminate reinforced resin sheet) which make up a laminated, multi-layer structure.), and a between the second laminate reinforced resin sheet and the third laminate reinforced resin sheet (Col. 6, lines 37-40 point to embodiments where each of the first and second buildup materials 26 (first sheet) and 46 (second sheet) can be a buildup film suitable for flexible circuits, such as an epoxy, polyimide, polyester, or other polymer or combination of polymers (adhesive).).
Regarding claim 27, Link teaches wherein bonding the first laminate reinforced resin sheet, the second laminate reinforced resin sheet, and the third laminate reinforced resin sheet comprises performing a press lamination process and a final cure (Col. 10, lines 42-46 point to laminating the core, conductive material, and buildup materials to define a multi-layer substrate, which may include subjecting the layered structure to heat and pressure to fuse together the materials.).
Regarding claim 28, Link teaches wherein a first layer of copper foil is provided over the first side of the stack and a second layer of copper foil is provided over the second side of the stack prior to performing the press lamination process to provide a first metal laminate layer over the first side of the stack and a second metal laminate layer over the second side of the stack (Fig. 6 and Col. 10, lines 36-41 point to a method of formation 300 comprising a process 335 where a final or outermost layer of conductive material (e.g., copper foil) is applied on the buildup materials (first side of the stack; second side of the stack), which is performed prior to the lamination process of 340.)., the method further comprising: patterning the first metal laminate layer to form a first plurality of metal traces over the first side of the stack prior to forming the first redistribution layer; and patterning the second metal laminate layer to form a second plurality of metal traces over the second side of the stack prior to forming the second redistribution layer (Id. points to the process 335 optionally including patterning and etching the outermost layer of conductive material (first metal laminate layer; second metal laminate layer) to define contact pads, conductive traces, and other features.).
Regarding claim 31, Link teaches wherein a Young's modulus of the first sheet is greater than a Young's modulus of the second sheet (Col. 9, lines 10-13 and lines 19-21 point to the first buildup material 26 (first portion) having a Young’s modulus E′ (at 25° C.) of at least 10 GPa, including at least 12 GPa, at least 15 GPa, and at least 20 GPa, and the second buildup material 46 (second portion) having a Young’s modulus E′ (at 25° C.) of no greater than 10 GPa.).
Regarding claim 37, Link teaches wherein forming the first redistribution layer comprises forming an array of first bonding pads having a pattern that corresponds to a pattern of bonding pads located on a surface of a package structure comprising at least one semiconductor die (Fig. 2 points to a first level interconnect 20 (first bonding pads) which is used to mount semiconductor chips 60 to the substrate 12.); and forming the second redistribution layer comprises forming an array of second bonding pads having a pattern that corresponds to a pattern of bonding pads located on a surface of a printed circuit board (PCB) (Id. points to a second level interconnect 40 (second bonding pads) which is used to mount the substrate 12 to a PCB 11.).
Claim Rejections - 35 USC § 103
Claim(s) 29-30 are rejected under 35 U.S.C. 103 as being unpatentable over Link (US Patent No. 11824013).
Regarding claim 29, Link teaches wherein the openings through the first sheet, the second sheet and the third sheet are formed after the first sheet, the second sheet, and the third sheet are bonded to form the stack (Fig. 2 points to vias 24, through-core vias 34, and vias 44, which are found in the first buildup material 26 (first sheet), the core 18 (third sheet), and the second buildup material 46 (second sheet), respectively. It is considered obvious that one of ordinary skill in the art would first create the bonded stack prior to forming the openings in order to first line up each of the sheets and/or establish a stable structure before removing any of the sheet material(s).).
Regarding claim 30, Link teaches wherein the openings through the first sheet, the second sheet and the third sheet are formed prior to bonding the first sheet, the second sheet and the third sheet to form the stack (Fig. 2 points to vias 24, through-core vias 34, and vias 44, which are found in the first buildup material 26 (first sheet), the core 18 (third sheet), and the second buildup material 46 (second sheet), respectively. It is considered obvious that one of ordinary skill in the art would first form openings in each of the sheets prior to creating the bonded stack in order to form modular components that could be further modified or completely replaced prior to the bonding process.).
Response to Arguments
Applicant’s arguments, see Remarks, filed 11/26/2025, with respect to claim(s) 17-23 and 32-36 have been considered but are moot because the Applicant has chosen to elect claims 24-31 (along with newly added claim 37) without traverse.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Patrick L Cullen whose telephone number is (703)756-1221. The examiner can normally be reached Monday - Friday, 8:30AM - 5PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at (571)270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PATRICK CULLEN/ Assistant Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899