DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I (original claims 1-9) and Species 1 (Fig. 10) in the reply filed on 8.25.2025 is acknowledged.
Non-elected claims 10-20 of Inventions II and III have been cancelled and applicant adds claims 21-31; applicant states that claims 1-9 and 21-31 are elected.
Newly submitted claims 21-26 are directed to an invention that is independent or distinct from the elected invention of original claims 1-9 for the following reasons:
Original claims 1-9 and new claims 21-26 are directed to related processes. The related inventions are distinct if: (1) the inventions as claimed are either not capable of use together or can have a materially different design, mode of operation, function, or effect; (2) the inventions do not overlap in scope, i.e., are mutually exclusive; and (3) the inventions as claimed are not obvious variants. See MPEP § 806.05(j). In the instant case, the inventions as claimed can have a materially different design, mode of operation, function, or effect since original claims 1-9 require removal of a selected gate which is not required in new claims 21-26; in addition, new claims 21-26 require spacer formation which is not required in original claims 1-9. Recall that MPEP 806.05 states “Related inventions in the same statutory class are considered mutually exclusive, or not overlapping in scope, if a first invention would not infringe a second invention, and the second invention would not infringe the first invention” and in this case original claims 1-9 do not infringe on new claims 21-26 and vice versa. Furthermore, the inventions as claimed do not encompass overlapping subject matter and there is nothing of record to show them to be obvious variants.
Furthermore, restriction for examination purposes as indicated is proper because all the inventions listed in this action are independent or distinct for the reasons given above and there would be a serious search and/or examination burden if restriction were not required because one or more of the following reasons apply:
the inventions have acquired a separate status in the art in view of their different classification;
the inventions have acquired a separate status in the art due to their recognized divergent subject matter;
the inventions require a different field of search (e.g., searching different classes/subclasses or electronic resources, or employing different search strategies or search queries); and/or
the prior art applicable to one invention would not likely be applicable to another invention and/or the inventions are likely to raise different non-prior art issues under 35 U.S.C. 101 and/or 35 U.S.C. 112, first paragraph.
Since applicant has received an action on the merits for the originally presented invention or has elected an invention that is independent or distinct from the newly added invention, this (original claims 1-9) invention has been constructively elected by original presentation for prosecution on the merits. Accordingly, claims 21-26 are withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03.
To preserve a right to petition, the reply to this action must distinctly and specifically point out supposed errors in the restriction requirement. Otherwise, the election shall be treated as a final election without traverse. Traversal must be timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are subsequently added, applicant must indicate which of the subsequently added claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
Finally, to summarize, claims 1-9 and 27-31 are elected as drawn to Invention I (original claims 1-9) and Species 1 (Fig. 10) and claims 21-26 are withdrawn as drawn to an invention independent or distinct from the elected invention.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the elements listed below must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Elements not shown:
Claim 2: a bottom nanosheet (561) having a top surface at a first height (not shown) over the semiconductor material; and the isolation layer (300) has a top surface (301) at a second height (H1) over the semiconductor material; the first height (not shown) is greater than the second height (H1). There is no first height disclosed with regards to 561.
Claim 5: wherein the isolation layer (300) comprises a plurality of sublayers.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 2 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 2, “a bottom nanosheet having a top surface at a first height over the semiconductor material; and the isolation layer has a top surface at a second height over the semiconductor material; the first height is greater than the second height” is indefinite because the claim is inconsistent with the specification which is the basis for indefiniteness per MPEP 2173.03.
There is no first height disclosed with regards to 561 (“a bottom nanosheet”) and as such: a bottom nanosheet (561) having a top surface at a first height (not shown/disclosed) over the semiconductor material; and the isolation layer (300) has a top surface (301) at a second height (H1) over the semiconductor material; the first height (not shown/disclosed) is greater than the second height (H1) is indefinite because it conflicts with the specification per MPEP 2173.03.
For purposes of examination “bottom nanosheet” will be treated as presented or as “top nanosheet”.
Examiner Note
Claims below may be rejected multiple times over different prior art to show unpatentability of the claims in view of their breadth based on different interpretations of the claimed subject matter.
Claim Rejections - 35 USC § 102 and 35 USC § 103
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4 and 7-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tseng et al. (US 20170154823 A1).
Regarding claim 1, Tseng discloses a method comprising:
forming an isolation layer (30, “STI 30”) over a semiconductor material (12, Fig. 6);
forming source/drain regions (54, “source/drain region 54”) over (indirectly) the isolation layer (Fig. 7);
removing a selected gate structure (48, “gate structures 46, 48”), wherein removing the selected gate structure forms a trench (via removal of 44/50 which are replaced with 66/68/70/72) in the semiconductor material (Figs. 8-9); and
forming an isolation structure (68, “high-k dielectric layer 68”) in (partially) the trench (Figs. 8-9).
Regarding claim 4, Tseng discloses the method of claim 1, wherein the isolation layer (30, “STI 30”) comprises silicon oxide ([0011] – SiO2), silicon nitride, or a combination thereof.
Regarding claim 7, Tseng discloses the method of claim 1, wherein the isolation layer (30, “STI 30”, ([0011] – SiO2), has a band gap of at least 4eV (SiO2 has a higher band gap than 4eV; see, for example, https://www.iue.tuwien.ac.at/phd/hollauer/node11.html).
Regarding claim 8, Tseng discloses the method of claim 1, wherein the isolation layer (30, “STI 30”, ([0011] – SiO2) has a dielectric constant of less than 7.5 (SiO2 has a dielectric constant of less than 7.5; see, e.g., https://www.iue.tuwien.ac.at/phd/hollauer/node11.html).
Claim 5-6 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Tseng et al. (US 20170154823 A1).
Regarding claim 5, Tseng fails to disclose the method of claim 1, wherein the isolation layer (30) comprises a plurality of sublayers.
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to ensure that STI 30 comprises a plurality of sublayers as claimed in the method of Tseng so as to increase the likelihood of properly filling the STI region and improve electrical isolation between devices and/or because it has been held that duplicating parts of an invention involves only routine skill in the art as is prima facie obvious. See MPEP 2144.04 VI.
Regarding claim 6, Tseng fails to disclose the method of claim 1, wherein the isolation layer (30) has a vertical thickness of less than 6 nanometers (nm).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to ensure that STI 30 comprises a vertical thickness as claimed in the method of Tseng so as to ensure that STI 30 is recessed below a fin structure as disclosed by Tseng ([0015]) while still allowing for electrical isolation between devices.
Regarding claim 9, Tseng fails to disclose the method of claim 1, wherein the isolation structure (68) is laterally distanced from a nearest adjacent gate structure (62) by a distance of from 22 to 34 nanometers (nm).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to arrive at a value within the claimed range in the method of Tseng so as to achieve
electrical isolation between devices while allowing for high density integration of said devices.
Claims 1-2, 4 and 7-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (US 20210126113 A1).
Regarding claim 1, Ling discloses a method comprising:
forming an isolation layer (501, “spacers 501 are transformed into a dielectric material”) over a semiconductor material (201, Fig. 5C);
forming source/drain regions (503, “source/drain regions 503”) over the isolation layer (501, Fig. 5C);
removing a selected gate structure (middle gate 107/801 of Figs. 10A and 11A), wherein removing the selected gate structure forms a trench (1003) in the semiconductor material (201, Fig. 12A); and
forming an isolation structure (111, “CPODE structure 111 may be formed by depositing a dielectric material”) in the trench (Fig. 13A).
Regarding claim 2, Ling discloses the method of claim 1, wherein:
after removing the selected gate structure (Fig. 12A), a non-selected gate structure (next to 1003) remains over the semiconductor material (Figs. 12A and 13A);
the non-selected gate structure comprises a stack of vertically spaced-apart nanosheets (701, Fig. 7A) including a bottom (middle one of Fig. 7A shown in Fig. 7C as the top one) nanosheet having a top surface at a first height (H1) over the semiconductor material (201);
the isolation layer (501) has a top surface at a second height (H2) over the semiconductor material; and
the first height (H1) is greater than the second height (H2).
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Regarding claim 4, Ling discloses the method of claim 1, wherein the isolation layer (501) comprises silicon oxide, silicon nitride, or a combination thereof ([0060]).
Regarding claim 7, Ling discloses the method of claim 1, wherein the isolation layer (501) has a band gap of at least 4eV ([0060] discloses SiN which applicant discloses at [0049] as “a band gap of about 5 eV.”).
Regarding claim 8, Ling discloses the method of claim 1, wherein the isolation layer has a dielectric constant of less than 7.5 ([0060] discloses silicon oxynitride (SiON) which has a dielectric constant as “SiOxNy films can exhibit dielectric constants up to around 5.0” per https://www.mks.com/n/dielectric-thin-films. Other materials of [0060] also meet the claim).
Claims 3, 5-6, 9 and 27-31 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 20210126113 A1).
Regarding claim 3, Ling discloses a method of claim 1, wherein:
after removing the selected gate structure, a non-selected gate structure (107+) remains over the semiconductor material (201, Fig. 13A);
the non-selected gate structure comprises a stack of vertically spaced-apart nanosheets (701) including a top(most) nanosheet having a top surface (inherent, Fig. 13A);
the trench (occupied by 111) has a nadir (bottommost); and
the top surface is distanced from the nadir by a vertical distance H (inherent); the trench has a width W (inherent).
Ling fails to disclose a ratio of H:W is at least 2:1 and at most 5:1.
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to arrive at a claimed H:W ratio in Ling so as to (a) ensure more nanosheets (channels) are provided in a GAA device thereby providing a higher performance transistor, (b) reducing s/d sizing to allow higher integration of devices across a wafer, and/or, (c) because it has been held that a change in size/shape is generally recognized as being within the level of ordinary skill in the art. See MPEP 2144.04 IV.
Regarding claim 5, Lin fails to disclose the method of claim 1, wherein the isolation layer (501) comprises a plurality of sublayers.
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to ensure that isolation 501 comprises a plurality of sublayers as claimed in the method of Lin so as to increase the likelihood of isolating source/drain from the substrate ([0109]) and/or because it has been held that duplicating parts of an invention involves only routine skill in the art as is prima facie obvious. See MPEP 2144.04 VI.
Regarding claim 6, Lin fails to disclose the method of claim 1, wherein the isolation layer (501) has a vertical thickness of less than 6 nanometers (nm).
Lin discloses ([0059]) “the bottom spacers 501 are formed to a third height H3 of between about 3 nm and about 30 nm, such as about 20 nm”.
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to ensure that 501 comprises a vertical thickness as claimed in the method of Lin so as to ensure that 501 isolates source/drains from the substrate ([0109]) while minimizing a size of the device, and/or, because it has been held that a change in size/shape is generally recognized as being within the level of ordinary skill in the art. See MPEP 2144.04 IV.
Regarding claim 9, Lin fails to disclose the method of claim 1, wherein the isolation structure (111) is laterally distanced from a nearest adjacent gate structure (107+) by a distance of from 22 to 34 nanometers (nm).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to arrive at a value within the claimed range in the method of Lin so as to achieve
electrical isolation in nanosheet devices ([0109]) while allowing for high density integration of said devices, and/or because it has been held that a change in size/shape is generally recognized as being within the level of ordinary skill in the art. See MPEP 2144.04 IV.
Regarding claim 27, Lin discloses a method comprising:
forming a plurality of gate structures (107+) over a semiconductor substrate (201), each gate structure comprising vertically spaced nanosheets (701, Fig. 8A);
forming source/drain regions (503) between adjacent gate structures, wherein each source/drain region is separated from the semiconductor substrate by a respective isolation layer portion (501, Fig. 8A);
selecting a gate structure for removal (Figs. 10A-11A);
etching the selected gate structure and a portion of the underlying semiconductor substrate to form a trench (1003, Figs. 10A-12A) having a depth-to-width ratio (inherent)
filling the trench with an isolation material (111, [0099]) to (inherent, MPEP 2111, 2112 and/pr 214) electrically isolate the source/drain regions on opposite sides of the trench (Fig. 13A).
Lin fails to disclose a trench (1003, Figs. 10A-12A) having a depth-to-width ratio of at least 3:1.
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to arrive a ratio value within the claimed range so as to ensure the trench is deeper than it is wider thereby extending vertically along an entirety of a GAA device while allowing for high density integration of additional devices across a wafer, and/or, because it has been held that a change in size/shape is generally recognized as being within the level of ordinary skill in the art. See MPEP 2144.04 IV.
Regarding claim 28, Lin discloses the method of claim 27, wherein the trench (occupied by 111) has a nadir (bottommost) located below an uppermost surface of the semiconductor substrate (201)
Lin fails to disclose a vertical distance that is less than 90% of a height of an uppermost nanosheet above the uppermost surface of the semiconductor substrate.
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to arrive at a value within the claimed range so as to increase the likelihood of achieving electrical isolation within GAA devices ([0109]), and/or, because it has been held that a change in size/shape is generally recognized as being within the level of ordinary skill in the art. See MPEP 2144.04 IV.
Regarding claim 29, Lin fails to disclose the method of claim 27, wherein after filling the trench, the isolation material (111) is laterally distanced from a nearest remaining gate structure (107+) by a distance of 22 to 34 nanometers at an interface between the isolation layer portion and the semiconductor substrate.
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to arrive at a value within the claimed range in the method of Lin so as to achieve
electrical isolation in nanosheet devices ([0109]) while allowing for high density integration of said devices, and/or because it has been held that a change in size/shape is generally recognized as being within the level of ordinary skill in the art. See MPEP 2144.04 IV.
Regarding claim 30, Lin discloses the method of claim 27, wherein etching the selected gate structure (Fig. 12A+) comprises:
forming a patterned mask ([0095], “a photo resist may be formed”) defining an opening over the selected gate structure ([0095], “The opening in the photo resist is formed to reveal a portion of the gate cap 801”);
performing a selective etch process ([0096])
etching to a depth
Lin fails to disclose (a) using HBr-based plasma and (b) etching to a depth of 70 to 90 nanometers from a top surface of an uppermost nanosheet.
Regarding (a), it would have been obvious to one of ordinary skill in the art, before the effective filing date, to use HBr-based plasma etching to achieve high aspect ratio features since this etching was within the capabilities of one skilled in the art and would have yielded predictable results.
Regarding (b), it would have been obvious to one of ordinary skill in the art, before the effective filing date, to etch to a value within the claimed range so as to ensure the trench is deeper than it is wider thereby extending vertically along an entirety of a GAA device while allowing for high density integration of additional devices across a wafer, and/or, because it has been held that a change in size/shape is generally recognized as being within the level of ordinary skill in the art. See MPEP 2144.04 IV.
Regarding claim 31, Lin discloses the method of claim 27, wherein each isolation layer portion (501) has a thickness
Lin fails to disclose wherein each isolation layer portion has a thickness of 3 to 10 nanometers.
Lin discloses ([0059]) “the bottom spacers 501 are formed to a third height H3 of between about 3 nm and about 30 nm, such as about 20 nm”.
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to ensure that 501 comprises a thickness as claimed in the method of Lin so as to ensure that 501 isolates source/drains from the substrate ([0109]) while minimizing a size of the device, and/or, because it has been held that a change in size/shape is generally recognized as being within the level of ordinary skill in the art. See MPEP 2144.04 IV.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 9520482 B1 to Chang et al. discloses removal of a gate metal layer (414, Figs. 5A-6B) to form a trench (610, “line-cut 610”, Fig. 6C), and forming an isolation region (715) in the trench (Fig. 7A).
US 20200006559 A1 to Mehandru et al. discloses removing a dummy gate structure (320) to form a trench (342, Fig. 8A) and forming isolation layers (315/380) in the trench (Fig. 10A).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDRES MUNOZ whose telephone number is (571)270-3346. The examiner can normally be reached 8AM-5PM Central Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571)270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Andres Munoz/Primary Examiner, Art Unit 2818