DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Applicant is suggested/reminded to disclose relevant prior art(s) or other information that may be material to the patentability of the invention in a pending application. The prior art information must be submitted in the form of an information Disclosure Statement (“IDS”) (see MPEP 609 & 2001 and 37 CFR 1.56).
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The disclosure is objected to because of the following informalities:
In [0031], lines 11 and 14, “the stop layer 206” should read --the stop layer 204-- (emphasis added).
Appropriate correction is required.
Claim Objections
Claims 12 and 18 are objected to because of the following informalities:
In claim 12, line 2, “the peripheral area surrounding the device region” should read --the peripheral region surrounding the device region-- (emphasis added).
In claim 18, line 7, “the support structures while the support structure” should read --the support structure[[s]] while the support structure-- (emphasis added).
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 8 and 17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential elements, such omission amounting to a gap between the elements. See MPEP § 2172.01.
Claim 8 recites the limitation “using an etchant with a mixture of sulfuric acid and hydrogen peroxide or HF” in lines 2-3. However, it is unclear whether the claimed etchant is:
(i) a mixture of sulfuric acid and hydrogen peroxide,
(ii) hydrofluoric acid alone, or
(iii) a mixture including sulfuric acid, hydrogen peroxide, and hydrofluoric acid.
For best understand and examination purpose, the claim will be best considered based on drawings, disclosure, and/or any applicable prior arts; and the claim limitation “using an etchant with a mixture of sulfuric acid and hydrogen peroxide or HF” will be interpreted as “using an etchant selected from the group consisting of: (a) a mixture of sulfuric acid and hydrogen peroxide; and (b) HF” in the instant Office Action.
Claim 17 recites the limitation “using an etchant with a mixture of sulfuric acid and hydrogen peroxide or HF” in lines 2-3. However, it is unclear whether the claimed etchant is:
(i) a mixture of sulfuric acid and hydrogen peroxide,
(ii) hydrofluoric acid alone, or
(iii) a mixture including sulfuric acid, hydrogen peroxide, and hydrofluoric acid.
For best understand and examination purpose, the claim will be best considered based on drawings, disclosure, and/or any applicable prior arts; and the claim limitation “using an etchant with a mixture of sulfuric acid and hydrogen peroxide or HF” will be interpreted as “using an etchant selected from the group consisting of: (a) a mixture of sulfuric acid and hydrogen peroxide; and (b) HF” in the instant Office Action.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 and 9-12 are rejected under 35 U.S.C. 103 as being unpatentable over Sarma et al. (US 5258323; hereinafter ‘Sarma’) in view of Uozumi (US 2021/0091024) and Lin et al. (US 2014/0113452; hereinafter ‘Lin’).
Regarding claim 1, Sarma teaches a method of forming a semiconductor structure (Fig. 4a-4e, col. 2, lines 49-50), comprising:
providing a first wafer (20, Fig. 4a, col. 3, line 29);
providing a second wafer (18, Fig. 4a, col. 3, lines 33-34) with a device layer (32, col. 3, line 36) sandwiched between a stop layer (30, col. 3, line 37);
bonding the first wafer (20) to the second wafer (18) to form a stacked wafer structure (24, col. 4, lines 24-25);
forming a support structure (22, Fig. 4b, col. 3, lines 51-52) between an edge of the first wafer (an edge of 20; hereinafter ‘20E’) and an edge of the second wafer (an edge of 18; hereinafter ‘18E’);
performing a thinning process (thinning operation, Fig. 4d, col. 4, line 39) on a backside of the second wafer (a surface of 18 facing away from 20) expose the stop layer of the second wafer (30) while the support structure is in place (22 presents during thinning operation, col. 4, lines 37-39);
removing the support structure (22 is removed from 20, 30, and 32, col. 3, lines 61-63).
Sarma does not teach the method of forming a semiconductor structure, comprising: providing a first wafer with a first bonding dielectric layer, and providing a second wafer with a second bonding dielectric layer; performing a first etching process to remove the second bonding dielectric layer overlying the support structure; and performing a second etching process to remove the support structure and expose the first bonding dielectric layer of the first wafer.
Uozumi teaches a method of forming a semiconductor structure (1A, FIG. 1, [0019]), comprising:
providing a first wafer (2, [0020]) with a first bonding dielectric layer (7, [0021, 0024]), and
providing a second wafer (3) with a second bonding dielectric layer (10);
performing a first process (trimming, FIG. 7, [0043]) to remove the second bonding dielectric layer (10) overlying the support structure (17); and
performing a second process (trimming) to expose the first bonding dielectric layer (7) of the first wafer (2).
As taught by Uozumi, one of ordinary skill in the art would utilize and modify the above teaching into Sarma to obtain and achieve the method of forming a semiconductor structure, comprising: providing a first wafer with a first bonding dielectric layer, and providing a second wafer with a second bonding dielectric layer; performing a first process to remove the second bonding dielectric layer overlying the support structure; and performing a second process to expose the first bonding dielectric layer of the first wafer as claimed, because the first and second bonding dielectric layers and the support structure collectively remain to preserve electrical insulation and bonding integrity of the bonded structure, while suppressing metal diffusion and preventing chipping and peeling at the outer peripheral non-bonded region [0026-0027, 0029].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Uozumi in combination with Sarma due to above reason.
Sarma in view of Uozumi does not teach the method of forming a semiconductor structure comprising performing a first etching process and performing a second etching process.
Lin teaches a method of forming a semiconductor structure [0005] in which trimming is performed by an etching process (trimming is performed by the etching process).
As taught by Lin, one of ordinary skill in the art would utilize and modify the above teaching into Sarma in view of Uozumi obtain and achieve the method of forming a semiconductor structure comprising performing a first etching process and performing a second etching process as claimed, because etching provides non-contact material removal and thus avoids particle contamination and mechanical stress inherent in grinding-based wafer edge trimming [0003-0004, 0032].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Uozumi in combination with Sarma in view of Uozumi due to above reason.
Regarding claim 2, Sarma in view of Uozumi and Lin teaches the method of claim 1, wherein the stacked wafer structure (Sarma: 24, Fig. 4b) comprises a bonding region (the region where 18 and 20 are bonded; hereinafter ‘BR’) and a non-bonding region (the edge region where 22 is applied; hereinafter ‘NBR’) surrounding the bonding region (BR).
Sarma in view of Lin does not teach the method wherein the stacked wafer structure comprises the first bonding dielectric layer is in direct contact with the second bonding dielectric layer in the bonding region, while the first bonding dielectric layer is not in contact with the second bonding dielectric layer in the non-bonding region.
Uozumi teaches the method wherein the stacked wafer structure (4, FIG. 7, [0043]) comprises the first bonding dielectric layer (7) is in direct contact with the second bonding dielectric (10) layer in the bonding region (the region where 2 and 3 are bonded; hereinafter ‘BRUOZUMI’), while the first bonding dielectric layer (7) is not in contact with the second bonding dielectric layer (10) in the non-bonding region (the edge region where 17 is applied; hereinafter ‘NBRUOZUMI’).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Uozumi to obtain and achieve the method wherein the stacked wafer structure comprises the first bonding dielectric layer is in direct contact with the second bonding dielectric layer in the bonding region, while the first bonding dielectric layer is not in contact with the second bonding dielectric layer in the non-bonding region as claimed, because bonding between the first and second dielectric layer is necessary only to ensure electrical insulation and bonding integrity in the active device region, whereas extending such bonding to the outer peripheral portion provide no benefit and interfere with defect mitigation at the non-bonded region [0025-0026, 0029].
Regarding claim 9, Sarma in view of Uozumi and Lin teaches the method of claim 1, wherein after removing the support structure (Sarma: 22 is removed from 20, 30, and 32, col. 3, lines 61-63), the method further comprises: removing the stop layer (30 is etched away, col. 3, lines 63-64, Fig. 4e), to expose the device layer (32).
Sarma in view of Lin does not teach the method further comprises: forming a backside metallization structure on the device layer.
Uozumi teaches the method further comprises: forming a backside metallization structure (38, FIG. 13, [0062]) on the device layer (as shown in FIG. 13, 3 including the device layer 14 corresponds to 23).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Uozumi to obtain and achieve the method further comprises: forming a backside metallization structure on the device layer as claimed, because it provides an external connection pad to electrically connect the array chip including the device layer to an external substrate or external devices [0063].
Regarding claim 10, Sarma teaches a method of forming a semiconductor structure (Fig. 4a-4e, col. 2, lines 49-50), comprising:
bonding a first wafer (20, Fig. 4a, col. 3, line 29) to a second wafer (18, col. 3, lines 33-34);
forming a protective structure (22, Fig. 4b, col. 3, lines 51-52) between an edge of the first wafer (an edge of 20; hereinafter ‘20E’) and an edge of the second wafer (an edge of 18; hereinafter ‘18E’) to cover a peripheral region of the first wafer (a region adjacent 20E; hereinafter ‘20P’);
when the protective structure (22) covers the peripheral region of the first wafer (20P), removing a substrate of the second wafer (thinning operation for 18, Fig. 4d, col. 4, line 39) from a backside of the second wafer (a surface of 18 facing away from 20);
performing a second process (22 is removed from 20, 30, and 32, col. 3, lines 61-63) to remove the protective structure (22) to expose the peripheral region of the first wafer (20P).
Sarma does not teach the method of forming a semiconductor structure, comprising: bonding a first wafer to a second wafer by contacting a first bonding dielectric layer of the first wafer to a second bonding dielectric layer of the second wafer; removing a substrate of the second wafer from a backside of the second wafer until the second bonding dielectric layer overlying the protective structure is exposed; performing a first etching process to remove the second bonding dielectric layer overlying the protective structure and expose the protective structure; and performing a second etching process to remove the protective structure.
Uozumi teaches a method of forming a semiconductor structure (1A, FIG. 1, [0019]), comprising:
bonding a first wafer (2, [0020]) to a second wafer (3) by contacting a first bonding dielectric layer of the first wafer (7, [0021, 0024]) to a second bonding dielectric layer of the second wafer (10);
removing a substrate of the second wafer (13, FIG. 2, [0023]) from a backside of the second wafer (a surface of 3 facing away from 2) until the second bonding dielectric layer (10) overlying the protective structure (17) is exposed (shown in FIG. 7);
performing a first process (trimming, FIG. 7, [0043]) to remove the second bonding dielectric layer (10) overlying the protective structure (17) and expose the protective structure (17).
As taught by Uozumi, one of ordinary skill in the art would utilize and modify the above teaching into Sarma to obtain and achieve the method of forming a semiconductor structure, comprising: bonding a first wafer to a second wafer by contacting a first bonding dielectric layer of the first wafer to a second bonding dielectric layer of the second wafer; removing a substrate of the second wafer from a backside of the second wafer until the second bonding dielectric layer overlying the protective structure is exposed; performing a first process to remove the second bonding dielectric layer overlying the protective structure and expose the protective structure as claimed, because the first and second bonding dielectric layers and the support structure collectively remain to preserve electrical insulation and bonding integrity of the bonded structure, while suppressing metal diffusion and preventing chipping and peeling at the outer peripheral non-bonded region [0026-0027, 0029].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Uozumi in combination with Sarma due to above reason.
Sarma in view of Uozumi does not teach the method of forming a semiconductor structure comprising performing a first etching process and performing a second etching process.
Lin teaches a method of forming a semiconductor structure [0005] in which trimming is performed by an etching process (trimming is performed by the etching process).
As taught by Lin, one of ordinary skill in the art would utilize and modify the above teaching into Sarma in view of Uozumi obtain and achieve the method of forming a semiconductor structure comprising performing a first etching process and performing a second etching process as claimed, because etching provides non-contact material removal and thus avoids particle contamination and mechanical stress inherent in grinding-based wafer edge trimming [0003-0004, 0032].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Uozumi in combination with Sarma in view of Uozumi due to above reason.
Regarding claim 11, Sarma in view of Uozumi and Lin teaches the method of claim 10, Sarma in view of Lin does not teach the method wherein after performing the second etching process, the first bonding dielectric layer still covers the peripheral region of the first wafer, so that a top surface of a substrate of the first wafer on the peripheral region is flat.
Uozumi teaches the method wherein after performing the second etching process, the first bonding dielectric layer (7, FIG. 7) still covers the peripheral region of the first wafer (a region adjacent the edge of 2; hereinafter ‘2P’), so that a top surface of a substrate of the first wafer (a surface of 11 facing 3) on the peripheral region (2P) is flat (shown in FIG. 7).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Uozumi to obtain and achieve the method wherein after performing the second etching process, the first bonding dielectric layer still covers the peripheral region of the first wafer, so that a top surface of a substrate of the first wafer on the peripheral region is flat as claimed, because it eliminates potentially defective edge regions and mitigates chipping and peeling during a subsequent process [0026, 0029].
Regarding claim 12, Sarma in view of Uozumi and Lin teaches the method of claim 10, Sarma in view of Lin does not teach the method wherein the first wafer comprises a device region and the peripheral area surrounding the device region, after performing the second etching process, a top surface of a substrate of the first wafer in the device region is substantially level with a top surface of a substrate of the first wafer in the peripheral region.
Uozumi teaches the method wherein the first wafer (2, FIG. 1) comprises a device region (12, [0022]) and the peripheral area (2P) surrounding the device region (12), after performing the second process (shown in FIG. 7), a top surface of a substrate of the first wafer (a surface of 11 facing 3) in the device region (12) is substantially level (shown in FIG. 7) with a top surface of a substrate of the first wafer in the peripheral region (2P) .
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Uozumi to obtain and achieve the method wherein the first wafer comprises a device region and the peripheral area surrounding the device region, after performing the second etching process, a top surface of a substrate of the first wafer in the device region is substantially level with a top surface of a substrate of the first wafer in the peripheral region as claimed, because it eliminates potentially defective edge regions and mitigates chipping and peeling during a subsequent process [0026, 0029].
Claims 3-4 and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Sarma (US 5258323) in view of Uozumi (US 2021/0091024) and Lin (US 2014/0113452), and further in view of Hayashishita (US 2018/01585697).
Regarding claim 3, Sarma in view of Uozumi and Lin teaches the method of claim 2, wherein the forming the support structure (Sarma: 22, Fig. 4b) comprises: injecting a sealant material (22 is EPO-TEK 301, col. 3, lines 51-52) into a gap (a gap between 20E and 18E) between the edge of the first wafer (20E) and the edge of the second wafer (18E).
Sarma in view of Lin does not teach the method the sealant material extends between the first bonding dielectric layer and the second bonding dielectric layer in the non-bonding region; and performing a curing process to cure the sealant material as the support structure.
Uozumi teaches the method the sealant material (17, FIG. 7) extends between the first bonding dielectric layer (7) and the second bonding dielectric layer (10) in the non-bonding region (NBRUOZUMI).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Uozumi to obtain and achieve the method the sealant material extends between the first bonding dielectric layer and the second bonding dielectric layer in the non-bonding region as claimed, because the sealant material filed in the non-bonded region fills a void at the outer peripheral portion and thereby functionally extends the bonding dielectric layer and protective effects of the bonding dielectric layers [0026-0027, 0029].
Sarma in view of Uozumi and Lin does not teach the method, wherein performing a curing process to cure the sealant material as the support structure.
Hayashishita teaches the method [0030], wherein performing a curing process to cure the sealant material as the support structure (heat-curing process to cure the sealant in an array configuration).
As taught by Hayashishita, one of ordinary skill in the art would utilize and modify the above teaching into Sarma in view of Uozumi and Lin obtain and achieve the method, wherein performing a curing process to cure the sealant material as the support structure as claimed, because curing a sealant after it is applied is a routine and well-known process step in semiconductor manufacturing to ensure mechanical stability and reliable sealing.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Hayashishita in combination with Sarma in view of Uozumi and Lin due to above reason.
Regarding claim 4, Sarma in view of Uozumi, Lin, and Hayashishita teaches the method of claim 3, wherein the sealant material comprises a modified epoxy-based polymer or an acrylic-based polymer (Sarma: 22 is EPO-TEK 301, that is an epoxy-based polymer).
Regarding claim 13, Sarma in view of Uozumi and Lin teaches the method of claim 10, wherein the forming the protective structure (Sarma: 22, Fig. 4b) comprises: injecting a sealant material (22 is EPO-TEK 301, col. 3, lines 51-52) into a gap (a gap between 20E and 18E) between the edge of the first wafer (20E) and the edge of the second wafer (18E).
Sarma in view of Lin does not teach the method the sealant material extends between the first bonding dielectric layer and the second bonding dielectric layer; and performing a curing process to cure the sealant material as the protective structure.
Uozumi teaches the method the sealant material (17, FIG. 7) extends between the first bonding dielectric layer (7) and the second bonding dielectric layer (10).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Uozumi to obtain and achieve the method the sealant material extends between the first bonding dielectric layer and the second bonding dielectric layer as claimed, because the sealant material filed in the non-bonded region fills a void at the outer peripheral portion and thereby functionally extends the bonding dielectric layer and protective effects of the bonding dielectric layers [0026-0027, 0029].
Sarma in view of Uozumi and Lin does not teach the method, wherein performing a curing process to cure the sealant material as the protective structure.
Hayashishita teaches the method [0030], wherein performing a curing process to cure the sealant material as the protective structure (heat-curing process to cure the sealant in an array configuration).
As taught by Hayashishita, one of ordinary skill in the art would utilize and modify the above teaching into Sarma in view of Uozumi and Lin obtain and achieve the method, wherein performing a curing process to cure the sealant material as the protective structure as claimed, because curing a sealant after it is applied is a routine and well-known process step in semiconductor manufacturing to ensure mechanical stability and reliable sealing.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Hayashishita in combination with Sarma in view of Uozumi and Lin due to above reason.
Regarding claim 14, Sarma in view of Uozumi, Lin, and Hayashishita teaches the method of claim 3, wherein the sealant material comprises a modified epoxy-based polymer or an acrylic-based polymer (Sarma: 22 is EPO-TEK 301, that is an epoxy-based polymer).
Claims 5, 7-8, and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Sarma (US 5258323) in view of Uozumi (US 2021/0091024) and Lin (US 2014/0113452), and further in view of Min et al. (US 2022/0165881; hereinafter ‘Min’).
Regarding claim 5, Sarma in view of Uozumi and Lin teaches the method of claim 1, wherein the thinning process comprises: a first thinning process including a grinding process (Sarma: grinding away a portion of 18, col. 3, lines 58-59).
Sarma in view of Uozumi and Lin does not teach the method wherein the thinning process comprises: a second thinning process including a wet etching process using an etchant with HNO3 and HF; and a third thinning process including a wet etching process using an etchant with TMAH or NH4OH.
Min teaches a method [0027] wherein the thinning process including a wet etching process using an etchant with HNO3 and HF (wet etch process using HNO3 and HF mixture, [0027]); and using an etchant with TMAH or NH4OH (wet etch process using TMAH or NH4OH).
Although, Min does not explicitly teach that the trimming process comprises two sequential steps, performing trimming in successive steps would have been obvious to a person having ordinary skill in the art, as trimming process are commonly implemented in multiple stages to achieve precise edge control and uniform material removal.
As taught by Min, one of ordinary skill in the art would utilize and modify the above teaching into Sarma in view of Uozumi and Lin obtain and achieve the method wherein the thinning process comprises: a second thinning process including a wet etching process using an etchant with HNO3 and HF and a third thinning process including a wet etching process using an etchant with TMAH or NH4OH as claimed, because HNO3, HF, TMAH, and NH4OH are well known material and widely used in the art as the etchant for wet etching process. Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Min in combination with Sarma in view of Uozumi and Lin due to above reason.
Regarding claim 7, Sarma in view of Uozumi and Lin teaches the method of claim 1, but does not teach the method wherein the first etching process comprise a wet etching process using an etchant with HF.
Min teaches a method [0027] wherein the first etching process comprise a wet etching process using an etchant with HF (wet etch process using HF, [0027]).
As taught by Min, one of ordinary skill in the art would utilize and modify the above teaching into Sarma in view of Uozumi and Lin obtain and achieve the method wherein the first etching process comprise a wet etching process using an etchant with HF as claimed, because HF is a well-known material and widely used in the art as the etchant for wet etching process. Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Min in combination with Sarma in view of Uozumi and Lin due to above reason.
Regarding claim 8, Sarma in view of Uozumi and Lin teaches the method of claim 1, but does not teach the method wherein the second etching process comprises a wet etching process using an etchant with a mixture of sulfuric acid and hydrogen peroxide or HF.
Min teaches a method [0027] wherein the second etching process comprises a wet etching process using an etchant with a mixture of sulfuric acid and hydrogen peroxide or HF (wet etch process using HF, [0027]).
As taught by Min, one of ordinary skill in the art would utilize and modify the above teaching into Sarma in view of Uozumi and Lin obtain and achieve the method wherein the second etching process comprises a wet etching process using an etchant with a mixture of sulfuric acid and hydrogen peroxide or HF as claimed, because HF is a well-known material and widely used in the art as the etchant for wet etching process. Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Min in combination with Sarma in view of Uozumi and Lin due to above reason.
Regarding claim 16, Sarma in view of Uozumi and Lin teaches the method of claim 10, but does not teach the method wherein the first etching process comprises a wet etching process using an etchant with HF.
Min teaches a method [0027] wherein the first etching process comprises a wet etching process using an etchant with HF (wet etch process using HF, [0027]).
As taught by Min, one of ordinary skill in the art would utilize and modify the above teaching into Sarma in view of Uozumi and Lin obtain and achieve the method wherein the first etching process comprises a wet etching process using an etchant with HF as claimed, because HF is a well-known material and widely used in the art as the etchant for wet etching process. Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Min in combination with Sarma in view of Uozumi and Lin due to above reason.
Regarding claim 17, Sarma in view of Uozumi and Lin teaches the method of claim 10, but does not teach the method wherein the second etching process comprises a wet etching process using an etchant with a mixture of sulfuric acid and hydrogen peroxide or HF.
Min teaches a method [0027] wherein the second etching process comprises a wet etching process using an etchant with a mixture of sulfuric acid and hydrogen peroxide or HF (wet etch process using HF, [0027]).
As taught by Min, one of ordinary skill in the art would utilize and modify the above teaching into Sarma in view of Uozumi and Lin obtain and achieve the method wherein the second etching process comprises a wet etching process using an etchant with a mixture of sulfuric acid and hydrogen peroxide or HF as claimed, because HF is a well-known material and widely used in the art as the etchant for wet etching process. Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Min in combination with Sarma in view of Uozumi and Lin due to above reason.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Sarma (US 5258323) in view of Uozumi (US 2021/0091024), Lin (US 2014/0113452), and Min (US 2022/0165881), and further in view of Kim et al. (US 2020/0135760; hereinafter ‘Kim’).
Regarding claim 6, Sarma in view of Uozumi, Lin, and Min teaches the method of claim 5, but does not teach the method wherein a removal rate of the second thinning process is greater than a removal rate of the third thinning process.
Kim teaches a method [0009] wherein a removal rate of the second thinning process is greater than a removal rate of the third thinning process (the first etching ratio is greater than a second etching ratio, [0017]).
As taught by Kim, one of ordinary skill in the art would utilize and modify the above teaching into Sarma in view of Uozumi, Lin, and Min obtain and achieve the method wherein a removal rate of the second thinning process is greater than a removal rate of the third thinning process as claimed, because it enables a relatively higher etching rate in an initial etching step to efficiently remove a bulk portion of material, and a relatively lower etching rate in a subsequent etching step to allow fine control of the etched profile.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Kim in combination with Sarma in view of Uozumi, Lin, and Min due to above reason.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Sarma (US 5258323) in view of Uozumi (US 2021/0091024), Lin (US 2014/0113452), and further in view of Zhong (US 2013/0032296).
Regarding claim 15, Sarma in view of Uozumi and Lin teaches the method of claim 10, but does not teach the method wherein the protective structure is configured to dissociate in an acidic environment.
Zhong teaches a method [0010] wherein the protective structure is configured to dissociate in an acidic environment (a temporary bonding material to dissociated in an acid, [0010-0013]).
As taught by Zhong, one of ordinary skill in the art would utilize and modify the above teaching into Sarma in view of Uozumi and Lin obtain and achieve the method wherein the protective structure is configured to dissociate in an acidic environment as claimed, because acidic solution is effectively clean the wafers by removing residual bonding material [0009].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Zhong in combination with Sarma in view of Uozumi and Lin due to above reason.
Claims 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Sarma (US 5258323) in view of Uozumi (US 2021/0091024) and Zhong (US 2013/0032296).
Regarding claim 18, Sarma teaches a method of forming a semiconductor structure (Fig. 4a-4e, col. 2, lines 49-50), comprising:
bonding a device wafer (18, Fig. 4a, col. 3, lines 33-34) onto a carrier wafer (20, Fig. 4a, col. 3, line 29);
forming a support structure (22, Fig. 4b, col. 3, lines 51-52) between an edge of the device wafer (an edge of 18; hereinafter ‘18E’) and an edge of the carrier wafer (an edge of 20; hereinafter ‘20E’), wherein the support structure (22) surrounds a device layer of the device wafer (32, col. 3, line 36) along a closed path (shown in Fig. 4b).
Sarma does not teach the method of forming a semiconductor structure comprising removing a substrate and a portion of a bonding dielectric layer of the device wafer from a backside of the device wafer to expose the support structures while the support structure is in place; and removing the support structure through an acid etchant.
Uozumi teaches a method of forming a semiconductor structure (1A, FIG. 1, [0019]), comprising: removing (trimming, FIG. 7, [0043]) a substrate (13, FIG. 2, [0023]) and a portion of a bonding dielectric layer (a portion of 10, [0021, 0024]) of the device wafer (3) from a backside of the device wafer (a surface of 3 facing away from 2; hereinafter ‘3B’) to expose the support structures (17) while the support structure is in place (shown in FIG. 7).
As taught by Uozumi, one of ordinary skill in the art would utilize and modify the above teaching into Sarma to obtain and achieve the method of forming a semiconductor structure comprising removing a substrate and a portion of a bonding dielectric layer of the device wafer from a backside of the device wafer to expose the support structures while the support structure is in place as claimed, because the first and second bonding dielectric layers and the support structure collectively remain to preserve electrical insulation and bonding integrity of the bonded structure, while suppressing metal diffusion and preventing chipping and peeling at the outer peripheral non-bonded region [0026-0027, 0029].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Uozumi in combination with Sarma due to above reason.
Sarma in view of Uozumi does not teach the method of forming a semiconductor structure comprising removing the support structure through an acid etchant.
Zhong teaches a method of forming a semiconductor structure [0010] comprising removing the support structure through an acid etchant (the bonding material is removed using a strong acidic solution, FIG. 1, [0009])
As taught by Zhong, one of ordinary skill in the art would utilize and modify the above teaching into Sarma in view of Uozumi to obtain and achieve the method of forming a semiconductor structure comprising removing the support structure through an acid etchant as claimed, because acidic solution is effectively clean the wafers by removing residual bonding material [0009].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Zhong in combination with Sarma in view of Uozumi due to above reason.
Regarding claim 19, Sarma in view of Uozumi and Zhong teaches the method of claim 18, Sarma in view of Zhong does not teach the method further comprising removing a portion of the carrier wafer in a bevel region during removing the substrate and the portion of the bonding dielectric layer of the device wafer from the backside of the device wafer, so that a surface of the carrier wafer in the bevel region has one or more recesses.
Uozumi teaches the method further comprising removing (trimming, FIG. 7, [0043]) a portion of the carrier wafer (a portion of 2) in a bevel region (a bevel region of 2) during removing the substrate (13) and the portion of the bonding dielectric layer (a portion of 10) of the device wafer (3) from the backside of the device wafer (3B), so that a surface of the carrier wafer (a surface of 2 facing 3) in the bevel region (a bevel region of 2) has one or more recesses (shown in FIG. 7).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Uozumi to obtain and achieve the method further comprising removing a portion of the carrier wafer in a bevel region during removing the substrate and the portion of the bonding dielectric layer of the device wafer from the backside of the device wafer, so that a surface of the carrier wafer in the bevel region has one or more recesses as claimed, because the bonding dielectric layers and the support structure collectively remain to preserve electrical insulation and bonding integrity of the bonded structure, while suppressing metal diffusion and preventing chipping and peeling at the outer peripheral non-bonded region [0026-0027, 0029].
Regarding claim 20, Sarma in view of Uozumi and Zhong teaches the method of claim 18, Sarma in view of Uozumi does not teach the method wherein the acid etchant comprises a mixture of sulfuric acid and hydrogen peroxide or HF.
Zhong teaches the method wherein the acid etchant comprises a mixture of sulfuric acid and hydrogen peroxide or HF (acidic solution includes sulfuric acid, [0009]).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Zhong to obtain and achieve the method wherein the acid etchant comprises a mixture of sulfuric acid and hydrogen peroxide or HF as claimed, because sulfuric acid is a well-known material and is widely used in the art as an acid etchant. Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Conclusion
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/JIYOUNG OH/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 1/12/26