DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
Acknowledgement is made of the amendment received on 04/15/2026. Claims 1-20 are pending in this application. Claims 1-2, 8, 10, 12, and 17-18 are amended.
Claim Objections
Claim 18 is objected to because of the following informalities:
In claim 18, line 8, “on the edge of the device wafer” should read --[[on]] at the edge of the device wafer-- (emphasis added).
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 and 9-12 are rejected under 35 U.S.C. 103 as being unpatentable over Sarma et al. (US 5258323; hereinafter ‘Sarma’) in view of Uozumi (US 2021/0091024) and Lin et al. (US 2014/0113452; hereinafter ‘Lin’).
Regarding claim 1, Sarma teaches a method of forming a semiconductor structure (Fig. 4a-4e, col. 2, lines 49-50), comprising:
providing a first wafer (20, Fig. 4a, col. 3, line 29);
providing a second wafer (18, Fig. 4a, col. 3, lines 33-34) with a device layer (32, col. 3, line 36) sandwiched between a stop layer (30, col. 3, line 37);
bonding the first wafer (20) to the second wafer (18) to form a stacked wafer structure (24, col. 4, lines 24-25), wherein the stacked wafer structure (24) comprises a bonding region (a bonding region contacting 20 and 18; hereinafter ‘BR’) and a non-bonding region (a non-bonding region free of bonding between 20 and 18; hereinafter ‘NBR’) surrounding the bonding region (NBR surrounding BR);
forming a support structure (22, Fig. 4b, col. 3, lines 51-52) between an edge of the first wafer (an edge of 20; hereinafter ‘20E’) and an edge of the second wafer (an edge of 18; hereinafter ‘18E’);
performing a thinning process (thinning operation, Fig. 4d, col. 4, line 39) on a backside of the second wafer (a surface of 18 facing away from 20) expose the stop layer of the second wafer (30) while the support structure is in place (22 presents during thinning operation, col. 4, lines 37-39);
removing the support structure (22 is removed from 20, 30, and 32, col. 3, lines 61-63).
Sarma does not teach the method of forming a semiconductor structure, comprising: providing a first wafer with a first bonding dielectric layer, and providing a second wafer with a second bonding dielectric layer; wherein the support structure covers the first bonding dielectric layer on a flat region of the non-bonding region, thereby exposing the first bonding dielectric layer on a bevel region of the non-bonding region; performing a first process to remove the second bonding dielectric layer overlying the support structure; and performing a second process to remove the support structure and expose the first bonding dielectric layer of the first wafer.
Uozumi teaches a method of forming a semiconductor structure (1C, FIG. 7, [0043]), comprising:
providing a first wafer (2, [0043]) with a first bonding dielectric layer (7, [0024]), and
providing a second wafer (3, [0043]) with a second bonding dielectric layer (10, [0024]);
wherein the support structure (17, [0043]) covers the first bonding dielectric layer (7) on a flat region (a portion adjacent bonded interface where 7 and 10 extend planar; hereinafter ‘FR’) of the non-bonding region (15, [0043]), thereby exposing the first bonding dielectric layer (corresponding to exposure of 7) on a bevel region (a corner/outer peripheral region caused by CMP, [0026, 0030]; hereinafter ‘15BR’) of the non-bonding region (15);
performing a first process (trimming, FIG. 7, [0043]) to remove the second bonding dielectric layer (10) overlying the support structure (17); and
performing a second process (trimming) to expose the first bonding dielectric layer (7) of the first wafer (2).
As taught by Uozumi, one of ordinary skill in the art would utilize and modify the above teaching into Sarma to obtain and achieve the method of forming a semiconductor structure, comprising: providing a first wafer with a first bonding dielectric layer, and providing a second wafer with a second bonding dielectric layer; wherein the support structure covers the first bonding dielectric layer on a flat region of the non-bonding region, thereby exposing the first bonding dielectric layer on a bevel region of the non-bonding region; performing a first process to remove the second bonding dielectric layer overlying the support structure; and performing a second process to expose the first bonding dielectric layer of the first wafer as claimed, because filling the non-bonded region with the support structure while maintaining the bonded dielectric layers suppresses metal diffusion contamination and reduce shipping and peeling at the outer peripheral region during thinning processes [0027-0029].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Uozumi in combination with Sarma due to above reason.
Sarma in view of Uozumi does not teach the method of forming a semiconductor structure comprising performing a first etching process and performing a second etching process.
Lin teaches a method of forming a semiconductor structure [0005] in which trimming is performed by an etching process (trimming is performed by the etching process).
As taught by Lin, one of ordinary skill in the art would utilize and modify the above teaching into Sarma in view of Uozumi obtain and achieve the method of forming a semiconductor structure comprising performing a first etching process and performing a second etching process as claimed, because etching provides non-contact material removal and thus avoids particle contamination and mechanical stress inherent in grinding-based wafer edge trimming [0003-0004, 0032].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Uozumi in combination with Sarma in view of Uozumi due to above reason.
Regarding claim 2, Sarma in view of Uozumi and Lin teaches the method of claim 1, Sarma in view of Lin does not teach the method wherein the stacked wafer structure comprises the first bonding dielectric layer is in direct contact with the second bonding dielectric layer in the bonding region, while the first bonding dielectric layer is not in contact with the second bonding dielectric layer in the non-bonding region, wherein the support structure covers the second bonding dielectric layer on the flat region of the non-bonding region, thereby exposing the second bonding dielectric layer on the bevel region of the non-bonding region.
Uozumi teaches the method wherein the stacked wafer structure (4, FIG. 7, [0043]) comprises
the first bonding dielectric layer (7) is in direct contact with the second bonding dielectric (10) layer in the bonding region (the region where 2 and 3 are bonded; hereinafter ‘BRUOZUMI’), while the first bonding dielectric layer (7) is not in contact with the second bonding dielectric layer (10) in the non-bonding region (the edge region where 17 is applied; hereinafter ‘NBRUOZUMI’),
wherein the support structure (17) covers the second bonding dielectric layer (10) on the flat region of the non-bonding region (15FR), thereby exposing the second bonding dielectric layer (corresponding to exposure of 10) on the bevel region of the non-bonding region (15BR).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Uozumi to obtain and achieve the method wherein the stacked wafer structure comprises the first bonding dielectric layer is in direct contact with the second bonding dielectric layer in the bonding region, while the first bonding dielectric layer is not in contact with the second bonding dielectric layer in the non-bonding region as claimed, because bonding between the first and second dielectric layer is necessary only to ensure electrical insulation and bonding integrity in the active device region, whereas extending such bonding to the outer peripheral portion provide no benefit and interfere with defect mitigation at the non-bonded region [0025-0026, 0029].
Regarding claim 9, Sarma in view of Uozumi and Lin teaches the method of claim 1, wherein after removing the support structure (Sarma: 22 is removed from 20, 30, and 32, col. 3, lines 61-63), the method further comprises: removing the stop layer (30 is etched away, col. 3, lines 63-64, Fig. 4e), to expose the device layer (32).
Sarma in view of Lin does not teach the method further comprises: forming a backside metallization structure on the device layer.
Uozumi teaches the method further comprises: forming a backside metallization structure (38, FIG. 13, [0062]) on the device layer (as shown in FIG. 13, 3 including the device layer 14 corresponds to 23).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Uozumi to obtain and achieve the method further comprises: forming a backside metallization structure on the device layer as claimed, because it provides an external connection pad to electrically connect the array chip including the device layer to an external substrate or external devices [0063].
Regarding claim 10, Sarma teaches a method of forming a semiconductor structure (Fig. 4a-4e, col. 2, lines 49-50), comprising:
bonding a first wafer (20, Fig. 4a, col. 3, line 29) to a second wafer (18, col. 3, lines 33-34);
forming a protective structure (22, Fig. 4b, col. 3, lines 51-52) between an edge of the first wafer (an edge of 20; hereinafter ‘20E’) and an edge of the second wafer (an edge of 18; hereinafter ‘18E’) to cover a peripheral region of the first wafer (a region adjacent 20E; hereinafter ‘20P’);
when the protective structure (22) covers the peripheral region of the first wafer (20P), removing a substrate of the second wafer (thinning operation for 18, Fig. 4d, col. 4, line 39) from a backside of the second wafer (a surface of 18 facing away from 20);
performing a second process (22 is removed from 20, 30, and 32, col. 3, lines 61-63) to remove the protective structure (22) to expose the peripheral region of the first wafer (20P).
Sarma does not teach the method of forming a semiconductor structure, comprising: bonding a first wafer to a second wafer by contacting a first bonding dielectric layer of the first wafer to a second bonding dielectric layer of the second wafer; a protective structure cover the first bonding dielectric layer on a peripheral region of the first wafer, thereby exposing the first bonding dielectric layer on the edge of the first wafer; removing a substrate of the second wafer from a backside of the second wafer until the second bonding dielectric layer overlying the protective structure is exposed; performing a first process to remove the second bonding dielectric layer overlying the protective structure and expose the protective structure; and performing a second process to remove the protective structure.
Uozumi teaches a method of forming a semiconductor structure (1C, FIG. 7, [0043]), comprising:
bonding a first wafer (2, [0043]) to a second wafer (3, [0043]) by contacting a first bonding dielectric layer (7, [0024]) of the first wafer (2) to a second bonding dielectric layer (10, [0024]) of the second wafer (3);
a protective structure (17, [0043]) cover the first bonding dielectric layer (7) on a peripheral region (a portion adjacent bonded interface where 7 and 10 extend planar) of the first wafer (2), thereby exposing the first bonding dielectric layer (corresponding to exposure of 7) on the edge (a corner/outer peripheral region caused by CMP, [0026, 0030]) of the first wafer (2);
removing a substrate of the second wafer (13, FIG. 2, [0023]) from a backside of the second wafer (a surface of 3 facing away from 2) until the second bonding dielectric layer (10) overlying the protective structure (17) is exposed (shown in FIG. 7);
performing a first process (trimming, FIG. 7, [0043]) to remove the second bonding dielectric layer (10) overlying the protective structure (17) and expose the protective structure (17).
As taught by Uozumi, one of ordinary skill in the art would utilize and modify the above teaching into Sarma to obtain and achieve the method of forming a semiconductor structure, comprising: bonding a first wafer to a second wafer by contacting a first bonding dielectric layer of the first wafer to a second bonding dielectric layer of the second wafer; a protective structure cover the first bonding dielectric layer on a peripheral region of the first wafer, thereby exposing the first bonding dielectric layer on the edge of the first wafer; removing a substrate of the second wafer from a backside of the second wafer until the second bonding dielectric layer overlying the protective structure is exposed; performing a first process to remove the second bonding dielectric layer overlying the protective structure and expose the protective structure as claimed, because filling the non-bonded region with the support structure while maintaining the bonded dielectric layers suppresses metal diffusion contamination and reduce shipping and peeling at the outer peripheral region during thinning processes [0027-0029].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Uozumi in combination with Sarma due to above reason.
Sarma in view of Uozumi does not teach the method of forming a semiconductor structure comprising performing a first etching process and performing a second etching process.
Lin teaches a method of forming a semiconductor structure [0005] in which trimming is performed by an etching process (trimming is performed by the etching process).
As taught by Lin, one of ordinary skill in the art would utilize and modify the above teaching into Sarma in view of Uozumi obtain and achieve the method of forming a semiconductor structure comprising performing a first etching process and performing a second etching process as claimed, because etching provides non-contact material removal and thus avoids particle contamination and mechanical stress inherent in grinding-based wafer edge trimming [0003-0004, 0032].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Uozumi in combination with Sarma in view of Uozumi due to above reason.
Regarding claim 11, Sarma in view of Uozumi and Lin teaches the method of claim 10, Sarma in view of Lin does not teach the method wherein after performing the second etching process, the first bonding dielectric layer still covers the peripheral region of the first wafer, so that a top surface of a substrate of the first wafer on the peripheral region is flat.
Uozumi teaches the method wherein after performing the second etching process, the first bonding dielectric layer (7, FIG. 7) still covers the peripheral region of the first wafer (a region adjacent the edge of 2; hereinafter ‘2P’), so that a top surface of a substrate of the first wafer (a surface of 11 facing 3) on the peripheral region (2P) is flat (shown in FIG. 7).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Uozumi to obtain and achieve the method wherein after performing the second etching process, the first bonding dielectric layer still covers the peripheral region of the first wafer, so that a top surface of a substrate of the first wafer on the peripheral region is flat as claimed, because it eliminates potentially defective edge regions and mitigates chipping and peeling during a subsequent process [0026, 0029].
Regarding claim 12, Sarma in view of Uozumi and Lin teaches the method of claim 10, Sarma in view of Lin does not teach the method wherein the first wafer comprises a device region and the peripheral region surrounding the device region, after performing the second etching process, a top surface of a substrate of the first wafer in the device region is substantially level with a top surface of a substrate of the first wafer in the peripheral region.
Uozumi teaches the method wherein the first wafer (2, FIG. 1) comprises a device region (12, [0022]) and the peripheral area (2P) surrounding the device region (12), after performing the second process (shown in FIG. 7), a top surface of a substrate of the first wafer (a surface of 11 facing 3) in the device region (12) is substantially level (shown in FIG. 7) with a top surface of a substrate of the first wafer in the peripheral region (2P) .
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Uozumi to obtain and achieve the method wherein the first wafer comprises a device region and the peripheral area surrounding the device region, after performing the second etching process, a top surface of a substrate of the first wafer in the device region is substantially level with a top surface of a substrate of the first wafer in the peripheral region as claimed, because it eliminates potentially defective edge regions and mitigates chipping and peeling during a subsequent process [0026, 0029].
Claims 3-4 and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Sarma (US 5258323) in view of Uozumi (US 2021/0091024) and Lin (US 2014/0113452), and further in view of Hayashishita (US 2018/01585697).
Regarding claim 3, Sarma in view of Uozumi and Lin teaches the method of claim 2, wherein the forming the support structure (Sarma: 22, Fig. 4b) comprises: injecting a sealant material (22 is EPO-TEK 301, col. 3, lines 51-52) into a gap (a gap between 20E and 18E) between the edge of the first wafer (20E) and the edge of the second wafer (18E).
Sarma in view of Lin does not teach the method the sealant material extends between the first bonding dielectric layer and the second bonding dielectric layer in the non-bonding region; and performing a curing process to cure the sealant material as the support structure.
Uozumi teaches the method the sealant material (17, FIG. 7) extends between the first bonding dielectric layer (7) and the second bonding dielectric layer (10) in the non-bonding region (NBRUOZUMI).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Uozumi to obtain and achieve the method the sealant material extends between the first bonding dielectric layer and the second bonding dielectric layer in the non-bonding region as claimed, because the sealant material filed in the non-bonded region fills a void at the outer peripheral portion and thereby functionally extends the bonding dielectric layer and protective effects of the bonding dielectric layers [0026-0027, 0029].
Sarma in view of Uozumi and Lin does not teach the method, wherein performing a curing process to cure the sealant material as the support structure.
Hayashishita teaches the method [0030], wherein performing a curing process to cure the sealant material as the support structure (heat-curing process to cure the sealant in an array configuration).
As taught by Hayashishita, one of ordinary skill in the art would utilize and modify the above teaching into Sarma in view of Uozumi and Lin obtain and achieve the method, wherein performing a curing process to cure the sealant material as the support structure as claimed, because curing a sealant after it is applied is a routine and well-known process step in semiconductor manufacturing to ensure mechanical stability and reliable sealing.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Hayashishita in combination with Sarma in view of Uozumi and Lin due to above reason.
Regarding claim 4, Sarma in view of Uozumi, Lin, and Hayashishita teaches the method of claim 3, wherein the sealant material comprises a modified epoxy-based polymer or an acrylic-based polymer (Sarma: 22 is EPO-TEK 301, that is an epoxy-based polymer).
Regarding claim 13, Sarma in view of Uozumi and Lin teaches the method of claim 10, wherein the forming the protective structure (Sarma: 22, Fig. 4b) comprises: injecting a sealant material (22 is EPO-TEK 301, col. 3, lines 51-52) into a gap (a gap between 20E and 18E) between the edge of the first wafer (20E) and the edge of the second wafer (18E).
Sarma in view of Lin does not teach the method the sealant material extends between the first bonding dielectric layer and the second bonding dielectric layer; and performing a curing process to cure the sealant material as the protective structure.
Uozumi teaches the method the sealant material (17, FIG. 7) extends between the first bonding dielectric layer (7) and the second bonding dielectric layer (10).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Uozumi to obtain and achieve the method the sealant material extends between the first bonding dielectric layer and the second bonding dielectric layer as claimed, because the sealant material filed in the non-bonded region fills a void at the outer peripheral portion and thereby functionally extends the bonding dielectric layer and protective effects of the bonding dielectric layers [0026-0027, 0029].
Sarma in view of Uozumi and Lin does not teach the method, wherein performing a curing process to cure the sealant material as the protective structure.
Hayashishita teaches the method [0030], wherein performing a curing process to cure the sealant material as the protective structure (heat-curing process to cure the sealant in an array configuration).
As taught by Hayashishita, one of ordinary skill in the art would utilize and modify the above teaching into Sarma in view of Uozumi and Lin obtain and achieve the method, wherein performing a curing process to cure the sealant material as the protective structure as claimed, because curing a sealant after it is applied is a routine and well-known process step in semiconductor manufacturing to ensure mechanical stability and reliable sealing.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Hayashishita in combination with Sarma in view of Uozumi and Lin due to above reason.
Regarding claim 14, Sarma in view of Uozumi, Lin, and Hayashishita teaches the method of claim 3, wherein the sealant material comprises a modified epoxy-based polymer or an acrylic-based polymer (Sarma: 22 is EPO-TEK 301, that is an epoxy-based polymer).
Claims 5, 7-8, and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Sarma (US 5258323) in view of Uozumi (US 2021/0091024) and Lin (US 2014/0113452), and further in view of Min et al. (US 2022/0165881; hereinafter ‘Min’).
Regarding claim 5, Sarma in view of Uozumi and Lin teaches the method of claim 1, wherein the thinning process comprises: a first thinning process including a grinding process (Sarma: grinding away a portion of 18, col. 3, lines 58-59).
Sarma in view of Uozumi and Lin does not teach the method wherein the thinning process comprises: a second thinning process including a wet etching process using an etchant with HNO3 and HF; and a third thinning process including a wet etching process using an etchant with TMAH or NH4OH.
Min teaches a method [0027] wherein the thinning process including a wet etching process using an etchant with HNO3 and HF (wet etch process using HNO3 and HF mixture, [0027]); and using an etchant with TMAH or NH4OH (wet etch process using TMAH or NH4OH).
Although, Min does not explicitly teach that the trimming process comprises two sequential steps, performing trimming in successive steps would have been obvious to a person having ordinary skill in the art, as trimming process are commonly implemented in multiple stages to achieve precise edge control and uniform material removal.
As taught by Min, one of ordinary skill in the art would utilize and modify the above teaching into Sarma in view of Uozumi and Lin obtain and achieve the method wherein the thinning process comprises: a second thinning process including a wet etching process using an etchant with HNO3 and HF and a third thinning process including a wet etching process using an etchant with TMAH or NH4OH as claimed, because HNO3, HF, TMAH, and NH4OH are well known material and widely used in the art as the etchant for wet etching process. Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Min in combination with Sarma in view of Uozumi and Lin due to above reason.
Regarding claim 7, Sarma in view of Uozumi and Lin teaches the method of claim 1, but does not teach the method wherein the first etching process comprise a wet etching process using an etchant with HF.
Min teaches a method [0027] wherein the first etching process comprise a wet etching process using an etchant with HF (wet etch process using HF, [0027]).
As taught by Min, one of ordinary skill in the art would utilize and modify the above teaching into Sarma in view of Uozumi and Lin obtain and achieve the method wherein the first etching process comprise a wet etching process using an etchant with HF as claimed, because HF is a well-known material and widely used in the art as the etchant for wet etching process. Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Min in combination with Sarma in view of Uozumi and Lin due to above reason.
Regarding claim 8, Sarma in view of Uozumi and Lin teaches the method of claim 1, but does not teach the method wherein the second etching process comprises a wet etching process using an etchant selected from the group consisting of: (a) a mixture of sulfuric acid and hydrogen peroxide; and (b) HF.
Min teaches a method [0027] wherein the second etching process comprises a wet etching process using an etchant selected from the group consisting of: (a) a mixture of sulfuric acid and hydrogen peroxide; and (b) HF. (wet etch process using HF, [0027]).
As taught by Min, one of ordinary skill in the art would utilize and modify the above teaching into Sarma in view of Uozumi and Lin obtain and achieve the method wherein the second etching process comprises a wet etching process using an etchant selected from the group consisting of: (a) a mixture of sulfuric acid and hydrogen peroxide; and (b) HF as claimed, because HF is a well-known material and widely used in the art as the etchant for wet etching process. Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Min in combination with Sarma in view of Uozumi and Lin due to above reason.
Regarding claim 16, Sarma in view of Uozumi and Lin teaches the method of claim 10, but does not teach the method wherein the first etching process comprises a wet etching process using an etchant with HF.
Min teaches a method [0027] wherein the first etching process comprises a wet etching process using an etchant with HF (wet etch process using HF, [0027]).
As taught by Min, one of ordinary skill in the art would utilize and modify the above teaching into Sarma in view of Uozumi and Lin obtain and achieve the method wherein the first etching process comprises a wet etching process using an etchant with HF as claimed, because HF is a well-known material and widely used in the art as the etchant for wet etching process. Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Min in combination with Sarma in view of Uozumi and Lin due to above reason.
Regarding claim 17, Sarma in view of Uozumi and Lin teaches the method of claim 10, but does not teach the method wherein the second etching process comprises a wet etching process using an etchant selected from the group consisting of: (a) a mixture of sulfuric acid and hydrogen peroxide; and (b) HF.
Min teaches a method [0027] wherein the second etching process comprises a wet etching process using an etchant selected from the group consisting of: (a) a mixture of sulfuric acid and hydrogen peroxide; and (b) HF (wet etch process using HF, [0027]).
As taught by Min, one of ordinary skill in the art would utilize and modify the above teaching into Sarma in view of Uozumi and Lin obtain and achieve the method wherein the second etching process comprises a wet etching process using an etchant with a mixture of sulfuric acid and hydrogen peroxide or HF as claimed, because HF is a well-known material and widely used in the art as the etchant for wet etching process. Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Min in combination with Sarma in view of Uozumi and Lin due to above reason.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Sarma (US 5258323) in view of Uozumi (US 2021/0091024), Lin (US 2014/0113452), and Min (US 2022/0165881), and further in view of Kim et al. (US 2020/0135760; hereinafter ‘Kim’).
Regarding claim 6, Sarma in view of Uozumi, Lin, and Min teaches the method of claim 5, but does not teach the method wherein a removal rate of the second thinning process is greater than a removal rate of the third thinning process.
Kim teaches a method [0009] wherein a removal rate of the second thinning process is greater than a removal rate of the third thinning process (the first etching ratio is greater than a second etching ratio, [0017]).
As taught by Kim, one of ordinary skill in the art would utilize and modify the above teaching into Sarma in view of Uozumi, Lin, and Min obtain and achieve the method wherein a removal rate of the second thinning process is greater than a removal rate of the third thinning process as claimed, because it enables a relatively higher etching rate in an initial etching step to efficiently remove a bulk portion of material, and a relatively lower etching rate in a subsequent etching step to allow fine control of the etched profile.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Kim in combination with Sarma in view of Uozumi, Lin, and Min due to above reason.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Sarma (US 5258323) in view of Uozumi (US 2021/0091024), Lin (US 2014/0113452), and further in view of Zhong (US 2013/0032296).
Regarding claim 15, Sarma in view of Uozumi and Lin teaches the method of claim 10, but does not teach the method wherein the protective structure is configured to dissociate in an acidic environment.
Zhong teaches a method [0010] wherein the protective structure is configured to dissociate in an acidic environment (a temporary bonding material to dissociated in an acid, [0010-0013]).
As taught by Zhong, one of ordinary skill in the art would utilize and modify the above teaching into Sarma in view of Uozumi and Lin obtain and achieve the method wherein the protective structure is configured to dissociate in an acidic environment as claimed, because acidic solution is effectively clean the wafers by removing residual bonding material [0009].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Zhong in combination with Sarma in view of Uozumi and Lin due to above reason.
Claims 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Sarma (US 5258323) in view of Uozumi (US 2021/0091024) and Zhong (US 2013/0032296).
Regarding claim 18, Sarma teaches a method of forming a semiconductor structure (Fig. 4a-4e, col. 2, lines 49-50), comprising:
bonding a device wafer (18, Fig. 4a, col. 3, lines 33-34) onto a carrier wafer (20, Fig. 4a, col. 3, line 29);
forming a support structure (22, Fig. 4b, col. 3, lines 51-52) between an edge of the device wafer (an edge of 18; hereinafter ‘18E’) and an edge of the carrier wafer (an edge of 20; hereinafter ‘20E’), wherein the support structure (22) surrounds a device layer of the device wafer (32, col. 3, line 36) along a closed path (shown in Fig. 4b).
Sarma does not teach the method of forming a semiconductor structure comprising bonding a device wafer with a bonding dielectric layer; thereby exposing the bonding dielectric layer on the edge of the device wafer; removing a substrate and a portion of the bonding dielectric layer of the device wafer from a backside of the device wafer to expose the support structure while the support structure is in place.
Uozumi teaches a method of forming a semiconductor structure (1C, FIG. 7, [0043]), comprising:
bonding a device wafer (3, [0043]) with a bonding dielectric layer (10, [0024]);
thereby exposing the bonding dielectric layer (10) on the edge (a corner/outer peripheral region caused by CMP, [0026, 0030]) of the device wafer (3);
removing (trimming, FIG. 7, [0043]) a substrate (13, FIG. 2, [0023]) and a portion of the bonding dielectric layer (a portion of 10) of the device wafer (3) from a backside of the device wafer (a surface of 3 facing away from 2; hereinafter ‘3B’) to expose the support structure (17) while the support structure is in place (shown in FIG. 7).
As taught by Uozumi, one of ordinary skill in the art would utilize and modify the above teaching into Sarma to obtain and achieve the method of forming a semiconductor structure comprising bonding a device wafer with a bonding dielectric layer; thereby exposing the bonding dielectric layer on the edge of the device wafer; removing a substrate and a portion of the bonding dielectric layer of the device wafer from a backside of the device wafer to expose the support structure while the support structure is in place as claimed, because the first and second bonding dielectric layers and the support structure collectively remain to preserve electrical insulation and bonding integrity of the bonded structure, while suppressing metal diffusion and preventing chipping and peeling at the outer peripheral non-bonded region [0026-0027, 0029].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Uozumi in combination with Sarma due to above reason.
Sarma in view of Uozumi does not teach the method of forming a semiconductor structure comprising removing the support structure through an acid etchant.
Zhong teaches a method of forming a semiconductor structure [0010] comprising removing the support structure through an acid etchant (the bonding material is removed using a strong acidic solution, FIG. 1, [0009])
As taught by Zhong, one of ordinary skill in the art would utilize and modify the above teaching into Sarma in view of Uozumi to obtain and achieve the method of forming a semiconductor structure comprising removing the support structure through an acid etchant as claimed, because acidic solution is effectively clean the wafers by removing residual bonding material [0009].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Zhong in combination with Sarma in view of Uozumi due to above reason.
Regarding claim 19, Sarma in view of Uozumi and Zhong teaches the method of claim 18, Sarma in view of Zhong does not teach the method further comprising removing a portion of the carrier wafer in a bevel region during removing the substrate and the portion of the bonding dielectric layer of the device wafer from the backside of the device wafer, so that a surface of the carrier wafer in the bevel region has one or more recesses.
Uozumi teaches the method further comprising removing (trimming, FIG. 7, [0043]) a portion of the carrier wafer (a portion of 2) in a bevel region (a bevel region of 2) during removing the substrate (13) and the portion of the bonding dielectric layer (a portion of 10) of the device wafer (3) from the backside of the device wafer (3B), so that a surface of the carrier wafer (a surface of 2 facing 3) in the bevel region (a bevel region of 2) has one or more recesses (shown in FIG. 7).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Uozumi to obtain and achieve the method further comprising removing a portion of the carrier wafer in a bevel region during removing the substrate and the portion of the bonding dielectric layer of the device wafer from the backside of the device wafer, so that a surface of the carrier wafer in the bevel region has one or more recesses as claimed, because the bonding dielectric layers and the support structure collectively remain to preserve electrical insulation and bonding integrity of the bonded structure, while suppressing metal diffusion and preventing chipping and peeling at the outer peripheral non-bonded region [0026-0027, 0029].
Regarding claim 20, Sarma in view of Uozumi and Zhong teaches the method of claim 18, Sarma in view of Uozumi does not teach the method wherein the acid etchant comprises a mixture of sulfuric acid and hydrogen peroxide or HF.
Zhong teaches the method wherein the acid etchant comprises a mixture of sulfuric acid and hydrogen peroxide or HF (acidic solution includes sulfuric acid, [0009]).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Zhong to obtain and achieve the method wherein the acid etchant comprises a mixture of sulfuric acid and hydrogen peroxide or HF as claimed, because sulfuric acid is a well-known material and is widely used in the art as an acid etchant. Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Response to Arguments
Applicant's arguments with respect to claims have been considered but are moot in view of the new ground of rejection. Response to arguments on newly added limitations are responded to in the above rejection.
Claim 1
Applicant submits, pages 12-13, “Currently, the amended claim I recites the feature of "the support structure covers the first bonding dielectric layer on a flat region of the non-bonding region, thereby exposing the first bonding dielectric layer on a bevel region of the non-bonding region" and the amended claims 10, 18 both recite similar feature, that Sarma and Uozumi both fail to disclose. … However, as shown in FIG. 1 of Uozumi, both of the asserted first bonding dielectric layer (7) and second bonding dielectric layer (10) are completely covered by the asserted support structure (17). As such, it is submitted that Uozumi fails to disclose the said feature recited in the amended claims 1, 10, and 18”.
The examiner respectfully disagrees.
As discussed in the Office Action, Uozumi teaches a non-bonded region 15 formed at an outer peripheral portion of the bonding substrate due to rounded corner portions generated by CMP processing [0026], and further teaches the support structure 17 filled within the non-bounded region 15 [0028].
The amended limitation does not define any particular dimensional boundary between the flat region and the bevel region. As shown in FIGS. 1 and 7 of Uozumi, the non-bonded region 15 transitions from bonding surface S toward the rounded outer peripheral portions. The portions adjacent bonding surface S where the bonding dielectric layers 7 and 10 extend substantially planar relative to the round outer peripheral portions reasonably correspond to the claimed flat region of the non-bonding region, while the rounded outer peripheral portions correspond to the claimed bevel region.
Claims 10 and 18
Claims 10 and 18 recite similar limitations, and the examiner relies on the same reasoning discussed above with respect to claim 1.
Accordingly, the claim rejections to claims 1, 10, and 18 are maintained.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/JIYOUNG OH/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 6/5/26
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