DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group II, Species I (Figs. 2A-17B), (claims 16-35) in the reply filed on 01/20/2026 is acknowledged.
Claim Objections
Claim 21 is objected to because of the following informalities in line 2: “an metal oxide” should be “a metal oxide”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 24-25, 27 are rejected under 35 U.S.C. 112(b), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claims 24 and 25 are claimed in opposite type in contrast to specification [0084] and will be examined as defined in specification.
Claim 27 defines “wherein the first gate structure interfaces with the second gate structure” is not clear what it means or how it is interfaced? For examination purpose it will be examined as top of each other as shown in Fig. 17A
Double Patenting
The nonstatutory double patenting rejection is based on a judicially createddoctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the "right to exclude" granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory obviousness-type double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Omum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321 (c) or 1.321(d)may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement.
Effective January 1, 1994, a registered attorney or agent of record may sign aterminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
Claim 16 is provisionally rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claim 15 of US Patent Application No. 18306101. Although the conflicting claims are not identical, they are not patentably distinct from each other.
Regarding claim 16: A method, comprising:
forming a first stack of alternating first channel layers and first sacrificial layers over a substrate; forming a second stack of alternating second channel layers and second sacrificial layers over the first stack, wherein the second channel layers are made of metal oxide;
forming first source/drain structures on opposite ends of each of the first channel layers; forming second source/drain structures on opposite ends of each of the second channel layers;
removing the first sacrificial layers;
forming a first gate structure wrapping around each of the first channel layers;
removing the second sacrificial layers; and
forming a second gate structure wrapping around each of the second channel layers.
Claim 15 of ‘6101: A method, comprising:
forming a first stack of alternating first semiconductor channel layers and first sacrificial layers over a first substrate, wherein the first semiconductor channel layers have a first crystalline orientation;
forming a second stack of alternating second semiconductor channel layers and second sacrificial layers over the first stack, wherein the first semiconductor channel layers have a second crystalline orientation different from the first crystalline orientation;
forming first source/drain epitaxy structures on opposite ends of each of the first semiconductor channel layers;
forming second source/drain epitaxy structures on opposite ends of each of the second semiconductor channel layers;
replacing the first sacrificial layers with a first gate structure, the first gate structure wrapping around each of the first semiconductor channel layers; and
replacing the second sacrificial layers with a second gate structure, the second gate structure wrapping around each of the second semiconductor channel layers.
Claim 15 of ‘6101 does not explicitly talk about removing the first and second sacrificial layers.
However claim 15 of ‘6101 teaches replacing the first sacrificial layers with a first gate structure, replacing the second sacrificial layers with a second gate structure.
Thus, it would have been obvious to one of ordinary skill in the art at the time the application was filed to realize to replacing should be equivalent to removing to form the gate structures.
Claim 21 is provisionally rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claim 29 of US Patent Application No. 18306101 in view of Dewey et al (US 2020/0105751 A1). Although the conflicting claims are not identical, they are not patentably distinct from each other.
Regarding claim 21: A method, comprising:
forming a semiconductor layer and an metal oxide layer over a substrate;
etching the semiconductor layer and the metal oxide layer to form source/drain openings; forming first source/drain structures on opposite sides of the semiconductor layer;
forming second source/drain structures on opposite sides of the metal oxide layer; and
forming a first gate structure over the semiconductor layer and a second gate structure over the metal oxide layer.
Claim 29 of ‘6101: A method, comprising:
depositing a first semiconductor channel layer over a substrate;
depositing a metal oxide layer over the first semiconductor channel layer;
depositing a second semiconductor channel layer over the metal oxide layer;
forming first source/drain structures on opposite sides of the first semiconductor channel layer; forming second source/drain structures on opposite sides of the second semiconductor channel layer; and
forming first and second gate structures over the first and second semiconductor channel layers, respectively.
Claim 29 of ‘6101 does not talk about etching the semiconductor layer and the metal oxide layer to form source/drain openings.
Dewey teaches in Fig.4a, 5a and [0058] – [0063] about etching the semiconductor layer and the metal oxide layer to form source/drain openings.
Thus, it would have been obvious to try by one of ordinary skill in the art, at the time the application was filed, to use an etching method to form the source/drain openings according to the teaching of Dewey, since it has been held that choosing from a finite number of identified, predictable solutions such as etching used to form the device, with a reasonable expectation of success is obvious. KSR Int'l v. Teleflex Inc., 127 S.Ct. 1727 (2007).
Claim 29 is provisionally rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claim 16 of US Patent Application No. 18314968 in view of Dewey et al (US 2020/0105751 A1). Although the conflicting claims are not identical, they are not patentably distinct from each other.
Regarding claim 29: A method, comprising:
forming a first channel layer and a second channel layer over a substrate, wherein the first channel layer has a crystalline structure, while the second channel layer has an amorphous structure;
etching the first channel layer and the second channel layer to form source/drain openings; forming first source/drain structures in the source/drain openings and on opposite sides of the first channel layer;
forming second source/drain structures in the source/drain openings and on opposite sides of the second channel layer; and
forming a first gate structure over the first channel layer and a second gate structure over the second channel layer.
Claim 16 of ‘4968: A method, comprising:
forming a first stack of alternating first channel layers and first sacrificial layers over a substrate; forming a second stack of alternating second channel layers and second sacrificial layers over the first stack;
forming first source/drain epitaxy structures on opposite ends of each of the first channel layers;
forming first metal silicide layers over the first source/drain epitaxy structures, respectively;
after the first metal silicide layers are formed, forming second source/drain epitaxy structures on opposite ends of each of the second channel layers;
removing the first sacrificial layers and the second sacrificial layers;
forming a first gate structure wrapping around each of the first channel layers and a second gate structure wrapping around each of the second channel layers; and
after the first and second gate structures are formed, forming second metal silicide layers over the second source/drain epitaxy structures, respectively.
Claim 16 of ‘4968 does not talk about etching the first channel layer and the second channel layer to form source/drain openings and wherein the first channel layer has a crystalline structure, while the second channel layer has an amorphous structure.
Dewey teaches in Fig.4a, 5a and [0058] – [0063] about etching the semiconductor layer and the metal oxide layer to form source/drain openings. Dewey further teaches wherein the first channel layer has a crystalline structure [0080], while the second channel layer has an amorphous structure [0033] to form NMOS and PMOS type devices.
Therefore it would have been obvious to one of ordinary skill in the art, at the time of applicant’s invention from Boyd’s teachings to arrive at the claimed invention by applying a known technique to a known device with predictable results.
< Basic Requirements of a Prima Facie Case of
Obviousness
**>The Supreme Court in KSR International Co. v. Teleflex Inc., 550 U.S. ___,
___, 82 USPQ2d 1385, 1395-97 (2007)
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 16-35 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Dewey et al (US 2020/0105751 A1).
Regarding claims 16, 21: Dewey teaches in Fig. 2a, 3a, 4a, 5a about a method, comprising:
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forming a first stack of alternating first channel layers 305 and first sacrificial layers 303 over a substrate 211 (Fig. 3a);
forming a second stack of alternating second channel layers 301 and second sacrificial layers 302 over the first stack (Fig. 3a), wherein the second channel layers are made of metal oxide [0014];
forming first source/drain structures 222/223 on opposite ends of each of the first channel layers (Fig. 2a);
forming second source/drain structures 220/221 on opposite ends of each of the second channel layers (Fig. 2a);
removing the first sacrificial layers [0045], [0062];
forming a first gate structure (506+510) wrapping around each of the first channel layers (Fig. 2a, 5a);
removing the second sacrificial layers [0045], [0062]; and
forming a second gate structure (503+504) wrapping around each of the second channel layers (Fig. 2a, 5a).
Regarding claim 17: Dewey teaches in [0038] wherein the second sacrificial layers are made of semiconductor material.
Regarding claim 18: Dewey teaches in [0038] wherein the second sacrificial layers are made of dielectric material.
Regarding claims 19, 23, 32: Dewey teaches wherein the first source/drain structures are made of epitaxy material [0034], while the second source/drain structures are made of metal [0033].
Regarding claims 20, 30: Dewey teaches in Fig. 3a, [0039] wherein the first channel layers are made of semiconductor material.
Regarding claims 29, 31: As explained in claim 16, Dewey teaches all the limitations and Dewey further teaches wherein the first channel layer has a crystalline structure [0080], while the second channel layer has an amorphous structure [0033].
Regarding claim 22: Dewey teaches in Fig. 2a wherein the metal oxide layer 202 is above the semiconductor layer 205.
Regarding claim 24: Dewey teaches in [0046] wherein the metal oxide layer, the second source/drain structures, and the second gate structure form a p-type transistor.
Regarding claim 25: Dewey teaches in [0046] wherein the semiconductor layer, the first source/drain structures, and the first gate structure form an n-type transistor.
Regarding claims 26, 34: Dewey teaches in Fig. 2a further comprising forming an isolation structure 207 covering the first source/drain structures prior to forming the second source/drain structures.
Regarding claim 27: Dewey teaches in Fig. 2a, 5a wherein the first gate structure interfaces with the second gate structure.
Regarding claim 28: Dewey teaches in [0029] wherein the metal oxide layer comprises indium oxide (InOx), gallium oxide (GaOx), zinc oxide (ZnOx), tin oxide (SnOx), cadmium oxide (CdO), nickel oxide (NiO), copper oxide (CuO), or scandium oxide (ScOx).
Regarding claim 33: Dewey teaches in [0019] wherein the first source/drain structures are doped with p-type dopants.
Regarding claim 35: Dewey teaches in Fig. 2a wherein the second source/drain structures interfaces with the isolation structure.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED SHAMSUZZAMAN whose telephone number is (571)270-1839. The examiner can normally be reached Monday-Friday 7 am -4 pm EST.
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/Mohammed Shamsuzzaman/Primary Examiner, Art Unit 2897