DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to the communications dated 10/06/2025.
Claims 1-17, and 21-23 are pending in this application.
Applicant made a provisional election without traverse to prosecute the
invention of Group II, claims 1-17, and new claims 21-23, is acknowledged.
Claims 18-20 have been cancelled from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a non-elected group there being no allowable generic or linking claim.
Applicant has the right to file a divisional application covering the subject matter of the non-elected claims.
Acknowledges
2. Receipt is acknowledged of the following items from the Applicant.
Information Disclosure Statement (IDS) filed on 04/21/2023, and 09/20/2024. The references cited on the PTOL 1449 form have been considered.
Applicant is requested to cite any relevant prior art if being aware on form PTO-1449 in accordance with the guidelines set for in M.P.E.P. 609.
Specification
3. The specification has been checked to the extent necessary to determine the presence of possible minor errors. However, the applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
4. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
5. Claims 1, 5-10, and 21-23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lu et al. (US 2013/0154048)
Regarding claim 1, Lu discloses a method, comprising:
forming active regions (comprising device elements 1161 - 1164) on a substrate 110 (see fig. 6);
forming an interconnect structure M1-Mn over the active regions, the interconnect structure including a plurality of dielectric layers 440 and a guard ring 662 disposed within the dielectric layers 440;
etching an opening (in which through via 330 is located, see para. 0020, and figs. 3-6) through the interconnect structure M1-Mn and at least a first portion of the active regions, the opening extending into the substrate 110; and
forming a via structure 330 within the opening, the via structure 3330 being surrounded by the guard ring 662 when viewed along a direction perpendicular to a top surface of the substrate 110.
Regarding claim 5, Lu discloses the method of claim 1, wherein the via structure 330 is in contact with each of the first portion of the active regions. See fig. 6.
Regarding claim 6, Lu discloses the method of claim 1, wherein the guard ring 662 overhangs and is in electrical connection with a second portion 118-1 – 1184 of the active regions. See fig. 6, and para. 0016.
Regarding claim 7, Lu discloses the method of claim 6, further comprising: forming contact plugs 224 on the second portion 118-1 – 1184 of the active regions, wherein the guard ring 662 is in contact with the contact plugs 224. See fig. 6.
Regarding claim 8, Lu discloses the method of claim 1, further comprising:
depositing a top dielectric layer 442 over the via structure 330 and the guard ring 662 (see fig. 6); and
forming a top metal feature 444 in the top dielectric layer 442 such that the top metal feature 444 spans over and contacts the via structure 330 and the guard ring, wherein the top metal feature 444 interfaces with a top surface of the via structure. See para. 0026: “The external contacts 444 ... are formed to provide electrical contact to respective ones of the electrical circuits 112 and/or through vias 330.”
Regarding claim 9, Lu discloses the method of claim 1, wherein the guard ring 662 includes metal features disposed in each of the dielectric layers 440 of the interconnect structure. See fig. 6.
Regarding claim 10, Lu discloses the method of claim 1, wherein after the forming of the via structure 330 (such as via structure 3301 in fig. 6), remaining parts of the first portion of the active regions extend out (toward guard wells 1181, 1182, or underneath the via structure) of a sidewall of the via structure for a distance of at least 0.1 µm. See fig. 6.
Regarding claim 21, Lu discloses a method, comprising:
forming a plurality of first active regions and a plurality of second active regions on a substrate 110 (see fig. 6);
forming an interconnect structure M1-Mn over the first and second active regions, the interconnect structure including a plurality of dielectric layers 440 and a guard ring 662 disposed within the dielectric layers 440 and positioned directly above the second active regions;
etching an opening (in which through via 330 is located, see para. 0020, and figs. 3-6) through the interconnect structure and the first active regions, the opening extending into the substrate 110, the opening dividing the first active regions into segments;
forming a via structure 330 within the opening, the via structure being surrounded by the guard ring 662 when viewed from top; and
thinning the substrate 110 from a backside of the substrate to expose the via structure (see para. 0028).
Regarding claim 22, Lu discloses the method of claim 21, further comprising:
forming contacts 224 over the second active regions 118, wherein the contacts 224 electrically connect the guard ring 662 to the second active regions 118. See fig. 6.
Regarding claim 23, Lu discloses the method of claim 21, wherein when viewed from top the first active regions are circled by the second active regions. See fig. 6.
Claim Rejections - 35 U.S.C. § 103
6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
7. Claims 2, and 3 are rejected under 35 U.S.C. 103 as being unpatentable over Lu et al. (US 2013/0154048) in view of Hsu et al. (US 2023/0197523).
Regarding claim 2, Lu discloses the method of claim 1, comprising all claimed limitations, except for wherein the active regions are fin-like active regions.
Hsu discloses a method comprising forming active regions 20, 22, 24 on a substrate 12, wherein the active regions are fin-like active regions. See fig. 11.
It would have been obvious to one of ordinary skills in the art at the time the invention was made to modify the invention of Lu so that the active regions being Fin-like active regions, as that/those taught by Hsu. The benefits of such Fin-like active regions are, as taught by Hsu at para. [0003]:
“Since the three-dimensional structure of a FinFET increases the overlapping area between the gate and the fin-shaped structure of the silicon substrate, the channel region can therefore be more effectively controlled. This way, the drain-induced barrier lowering (DIBL) effect and the short channel effect are reduced. The channel region is also longer for an equivalent gate length, thus the current between the source and the drain is increased. In addition, the threshold voltage of the fin FET can be controlled by adjusting the work function of the gate.”
Regarding claim 3, Lu/Hsu discloses the method of claim 2, wherein the fin-like active regions including a crystalline semiconductor material protruding continuously from the substrate. See fig. 11 of Hsu.
8. Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Lu et al. (US 2013/0154048) in view of Hsu et al. (US 2023/0197523), and further in view of Reznicek et al. (US 11,075,273)
Regarding claim 4, Lu/Hsu discloses the method of claim 2, comprising all claimed limitations, except for wherein the fin-like active regions including an epitaxial stack of first semiconductor layers and second semiconductor layers interposed one over another, the first and second semiconductor layers including different material compositions.
Reznicek discloses a method comprising fin-like active regions, as shown in figs. 10, 11, 17, wherein the fin-like active regions including an epitaxial stack of first semiconductor layers 910 (figs. 10, 11) or 1610 (fig. 17) and second semiconductor layers 140P or 1620 interposed one over another, the first and second semiconductor layers including different material compositions.
It would have been obvious to one of ordinary skills in the art at the time the invention was made to modify the invention of Lu/Hsu so that the Fin-like active regions including an epitaxial stack of first semiconductor layers and second semiconductor layers interposed one over another, the first and second semiconductor layers including different material compositions, as that/those taught by Reznicek, to provide electrostatic discharge (ESD) protection to the obtained structure. See col. 1, lines 20-51 of Reznicek.
Allowance / Reasons for Allowance
9. Claims 11-17 are allowed.
The following is an examiner’s statement of reason for allowance:
None of the references of record teaches or suggests the claimed method of forming a semiconductor device (in combination set forth in the claim) comprising:
depositing an interconnect structure over the substrate, wherein the interconnect structure includes a guard ring extending upward from the contact plugs;
etching the interconnect structure to form an opening;
extending the opening through the first fins and into the substrate; and
depositing a via structure in the opening, wherein the guard ring circles the via structure in the top view.
Conclusion
10. A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the day of this letter. Failure to respond within the period for response will cause the application to become abandoned (see M.P.E.P 710.02(b)).
A shortened time for reply may be extended up to the maximum six-month period (35 U.S.C. 133). An extension of time fee is normally required to be paid if the reply period is extended. The amount of the fee is dependent upon the length of the extension. Extensions of time are generally not available after an application has been allowed.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Dao H. Nguyen whose telephone number is (571)272-1791. The examiner can normally be reached on Monday-Friday, 9:00 AM – 5:00 PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke, can be reached on (571)272-1657. The fax numbers for all communication(s) is 571-273-8300.
Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (571)272-1633.
/DAO H NGUYEN/Primary Examiner, Art Unit 2818 November 13, 2025