Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 5/7/26 have been fully considered but they are not persuasive.
Applicant’s arguments with respect to claim(s) 1-5, and 9-13 have been considered but are moot because the new ground of rejection below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, and 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu (US 2015/0054160) in view of Kim et al. (US 2024/0030169), Lin et al. (US 2016/0314979) and Pan. (US 2005/0048772).
Regarding claim 1, Liu disclose a wafer(50) [0027] including a dielectric (44 and 54), the dielectric having a first side (upper side) and a second side (lower side) opposite the first side; at least one opening (46 and 48 are in the “opening”) etched (The limitation “etched” is a product by process limitation. MPEP 2113 I discloses “’[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same … the claim is unpatentable even though the prior product was made by a different process.’ In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985) (citations omitted).” Therefore the “etched” limitation does not distinguish the invention from the prior art.) into the first side of the dielectric; a plug seed layer (46) disposed on the first side of the dielectric; a plug (48) disposed inside the at least one opening; a first thin layer (62) disposed over the plug; and a second thin layer (74)(fig. 12) deposited over the first thin layer, wherein the first thin layer, the second thin layer, or both the first thin layer and the second thin layer are deposited using electroless deposition. (The limitation “wherein the first thin layer, the second thin layer, or both the first thin layer and the second thin layer are deposited using electroless deposition” is a product by process limitation. MPEP 2113 I discloses “’[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same … the claim is unpatentable even though the prior product was made by a different process.’ In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985) (citations omitted).” Therefore the “wherein the first thin layer, the second thin layer, or both the first thin layer and the second thin layer are deposited using electroless deposition” does not distinguish the invention from the prior art. )
Liu fails to disclose the first thin layer is nickel.
Lin et al. disclose a thin layer is selected from nickel (208) [0018].
Liu fails to disclose the second thin layer is gold.
Pan disclose a thin layer is selected from gold (pad) [0005].
Liu fails to disclose the wafer-to-wafer assembly is configured to form a bond at a temperature of about 100-150°C.
Kim et al. disclose a wafer (12)[0023] to wafer (32)[0030] bond assembly (fig.1).
The examiner submits that since the combination of Liu, Kim Lin et al. and Pan in combination would teach the structure wafer to wafer bond assembly with the first thin layer (62) is nickel the second thin layer (74) is gold. Moreover, the combination would be configured to form a bond at a temperature of about 100-150°C, because it is made of the same materials claimed and disclosed. MPEP 2112.01 I discloses “[w]here the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433”.
The prior art included each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference.
One of ordinary skill in the art could have combined the elements as claimed by known methods (using a metal conductive layer as noted by Liu “consist essentially of, or consist of one or more of various metals ”[0034] and“consist essentially of, or consist of one or more of various metals ”[0042] and wafer to wafer bonding), and that in combination, each element merely performs the same function as it does separately.
One of ordinary skill in the art would have recognized that the results of the combination were predictable (the specific metals would conduct electricity and wafer-to-wafer bonding would result in high density stacking of the chips [Kim, 0003]).
Regarding claim 3, Liu disclose a height of the plug (48) corresponds to a depth of the opening such that an outer surface of the plug is flush with an outer surface of the dielectric (44) (fig. 16).
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu (US 2015/0054160) in view of Kim et al. (US 2024/0030169), Lin et al. (US 2016/0314979) and Pan. (US 2005/0048772) as applied to claim 1 above in view of Cohen (US 2006/0249849).
Liu, Kim Lin et al. and Pan disclose the invention supra.
Liu Kim Lin et al. and Pan disclose fail to disclose a height of the plug exceeds a depth of the opening such that the plug extends above an outer surface of the dielectric.
Lin et al. disclose a height of the plug(228) exceeds a depth of the opening such that the plug extends above an outer surface of the dielectric(204) (fig. 7).
The prior art included each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference.
One of ordinary skill in the art could have combined the elements as claimed by known methods (depositing the plug above the insulation layer), and that in combination, each element merely performs the same function as it does separately.
One of ordinary skill in the art would have recognized that the results of the combination were predictable (the plug above the insulation layer would conduct electricity).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu (US 2015/0054160) in view of Kim et al. (US 2024/0030169), Lin et al. (US 2016/0314979) and Pan. (US 2005/0048772) as applied to claim 1 above in view of Cohen (US 2006/0249849).
Liu, Kim Lin et al. and Pan disclose the invention supra.
Liu Kim Lin et al. and Pan disclose fail to disclose a height of the plug is less than a depth of the opening such that the plug is recessed below an outer surface of the dielectric.
Cohen disclose a height of the plug (18) is less than a depth of the opening such that the plug is recessed below an outer surface of the dielectric (11) (fig. 1a).
The prior art included each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference.
One of ordinary skill in the art could have combined the elements as claimed by known methods (depositing the plug below the insulation layer), and that in combination, each element merely performs the same function as it does separately.
One of ordinary skill in the art would have recognized that the results of the combination were predictable (the plug below the insulation layer would conduct electricity).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu (US 2015/0054160) in view of Kim et al. (US 2024/0030169), Lin et al. (US 2016/0314979) and Pan. (US 2005/0048772) as applied to claim 1 above in view of Cohen (US 2006/0249849).
Liu, Kim Lin et al. and Pan disclose the invention supra.
Liu Kim Lin et al. and Pan disclose fail to disclose a thickness of the first thin layer in combination with the second thin layer is about 2-7 nm.
Cohen disclose a thickness of the first thin layer (upper portion of 12) in combination with the second thin layer (lower portion of 12) is about 2-7 nm [0023, layer 12 is 30 angstroms which is equivalent to 3nm].
The prior art included each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference.
One of ordinary skill in the art could have combined the elements as claimed by known methods (depositing the plug below the insulation layer), and that in combination, each element merely performs the same function as it does separately.
One of ordinary skill in the art would have recognized that the results of the combination were predictable (the plug below the insulation layer would conduct electricity).
Claim(s) 9-10, and 12-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu (US 2015/0054160) in view of Kim et al. (US 2024/0030169), Lin et al. (US 2016/0314979) and Pan. (US 2005/0048772) as applied to claim 1 above.
Liu, Kim Lin et al. and Pan disclose the invention supra.
Liu and Pan fail to disclose the wafer is a first wafer, the assembly further comprising a second wafer, wherein the second wafer comprises: a second dielectric having a third side, and a fourth side opposite the third side; a second at least one opening etched into the third side of the second dielectric; a second plug seed layer disposed on the third side of the second dielectric; a second plug disposed in the second at least one opening; a third thin layer deposited over the second plug; and a fourth thin layer deposited over the third thin layer, wherein the bond is formed between the second thin layer and the fourth thin layer.
The examiner submits one could duplicate the structure in Liu (MPEP 2144.04 VI B “the court held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced”) and flip the structure in fig. 12 of Liu upside down in order to “a second dielectric having a third side, and a fourth side opposite the third side; a second at least one opening etched (MPEP 2113 I discloses “’[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same … the claim is unpatentable even though the prior product was made by a different process.’ In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985) (citations omitted).”) into the third side of the second dielectric; a second plug seed layer (46) disposed on the third side of the second dielectric; a second plug (48) disposed in the second at least one opening; a third thin layer (62) deposited over the second plug; and a fourth thin layer (74) deposited over the third thin layer (fig 12 upside down).
Moreover Kim et al. disclose the wafer is a first wafer(12)[0023], the assembly further comprising a second wafer (32)[0030] bond assembly (fig.1).
The combination Liu and Pan Lin and Kim would result in the bond is formed between the second thin layer and the fourth thin layer.
The prior art included each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference.
One of ordinary skill in the art could have combined the elements as claimed by known methods (wafer to wafer bonding), and that in combination, each element merely performs the same function as it does separately.
One of ordinary skill in the art would have recognized that the results of the combination were predictable (wafer-to-wafer bonding would result in high density stacking of the chips [Kim, 0003]).
Regarding claim 10, the bond is a first bond, and wherein a second bond is formed between outer dielectric surfaces of the first side of the first dielectric and the third side of the second dielectric, and wherein the second bond is based on Van der Waal forces. The duplication of the structure in Liu that is turned upside down would have the same structure and therefore would inherently result in the second bond is based on Van der Waal forces. MPEP 2112.01 V discloses “[T]he PTO can require an applicant to prove that the prior art products do not necessarily or inherently possess the characteristics of his [or her] claimed product. Whether the rejection is based on ‘inherency’ under 35 U.S.C. 102, on ‘prima facie obviousness’ under 35 U.S.C. 103, jointly or alternatively, the burden of proof is the same.” In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433-34 (CCPA 1977).
Regarding claim 12, Lin et al. disclose a thin layer is selected from nickel (208) [0018].
Regarding claim 13, Pan disclose a thin layer is selected from gold (pad) [0005].
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu (US 2015/0054160) in view of Kim et al. (US 2024/0030169), Lin et al. (US 2016/0314979) and Pan. (US 2005/0048772) as applied to claim 9 above in view of Cohen (US 2006/0249849).
Liu, Kim Lin et al. and Pan disclose the invention supra.
Liu Kim Lin et al. and Pan disclose fail to disclose a thickness of the third thin layer in combination with the second thin layer is about 2-7 nm.
Cohen disclose a thickness of the thin layer (upper portion of 12) in combination with the second thin layer (lower portion of 12) is about 2-7 nm [0023, layer 12 is 30 angstroms which is equivalent to 3nm]. The thin layer of Cohen could be used for the third thin layer.
The prior art included each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference.
One of ordinary skill in the art could have combined the elements as claimed by known methods (depositing the plug below the insulation layer), and that in combination, each element merely performs the same function as it does separately.
One of ordinary skill in the art would have recognized that the results of the combination were predictable (the plug below the insulation layer would conduct electricity).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRADLEY K SMITH whose telephone number is (571)272-1884. The examiner can normally be reached Monday-Friday, 10am-6pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/BRADLEY SMITH/Primary Examiner, Art Unit 2817
Prosecution Insights