DETAILED ACTION
This Office action responds to Applicant’s RCE amendments on 06/02/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination Under 37 CFR 1.114
A request for continued examination (RCE) under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection mailed on 04/02/2026. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 06/02/2026 has been entered.
Amendment Status
The amendment filed as an RCE submission on 06/02/2026, responding to the Office action mailed on 04/02/2026 has been entered. The present Office action is made with all previously suggested amendments being fully considered. Accordingly, pending in this Office action are claims 16, and 21-39.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 16, 21-39 are rejected under 35 U.S.C. 103 as being unpatentable over Cho (US 2021/0057308) in view of Chien (US 2019/0043904) in further view of Cool (US 2020/0096686).
Regarding claim 16, Cho shows (see, e.g., Cho: fig. 1M that is inverted) most aspects of a method of forming a package, comprising:
Forming a backside redistribution layer (RDL) RDL1/RDL2, comprising:
A first polymer layer 28a/18a (see, e.g., Cho: par. [0036], and [0037])
A first RDL RDL1
A backside connector 14/54 extending from a distal side of the first RDL RDL1 comprising:
A tapered portion having a width that decreases in a direction away from the first RDL RDL1, wherein the tapered portion comprises a contact surface at the end of the tapered portion
A pillar structure 14 connected to the contact surface
Attaching a semiconductor die 45 to the backside RDL structure RDL1/RDL2
Forming an encapsulation layer 48a around the semiconductor die 45 on the backside RDL structure RDL1/RDL2
Forming a frontside RDL structure RDL10/RDL20/RDL30 on the semiconductor die 45 and the encapsulation layer 48a
However, Cho fails (see, e.g., Cho: fig. 1M that is inverted) to show that the first polymer layer includes a dark material. Chien, in a similar device to Cho, shows (see, e.g., Chien: figs. 4A-4B) a polymer layer 490 that includes a black material (see, e.g., Chien: par. [0034], and claim 10). Moreover, Chien shows (see, e.g., Chien: figs. 4A-4B) that the polymer layer is part of the RDL, it has a low reflectivity value and reduces or prevents the incoming light from reflecting or falling on to the edges of the device by reducing or eliminating the edge flares (see, e.g., Chien: par. [0033]).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the polymer layer with dark material of Chien in the method of Cho, to provide low reflectivity values, and to reduce or prevent the incoming light from reflecting or falling on to the edges of the device by reducing or eliminating the edge flares.
However, Cho in view of Chien fails to (see, e.g., Chien: figs. 4A-4B) show that the dark material (see, e.g., Chien: par. [0034], and claim 10) includes a dye. Cho in view of Chien is actually silent about the content of the dark material (see, e.g., Chien: par. [0034], and claim 10). Cool, in a similar device to Cho in view of Chien, shows (see, e.g., Cool: fig. 3) that inactive border area IA may contain circuits, signal lines, and other structures that do not emit light for forming images. To hide circuitry and other components in border area IA from view by a user of device 10, the underside of the outermost layer of display 14 (e.g., the display cover layer or other display layer) may be coated with an opaque masking material. Cool also shows that the dark material from the opaque masking material is a black ink with a dye (e.g., a polymer containing visible-light-absorbing dye and/or pigment that imparts a black color to the polymer) (see, e.g., Cool: par. [0029]).
Therefore, it would have been obvious at the time of the invention to one of ordinary skill in the art to use either the dark material of Cho in view of Chien or the dark material with a dye of Cool because these were recognized in the semiconductor art for their use as materials for opaque mask structures in semiconductor device packages, as taught by Cho in view of Chien and by Cool, and selecting between known equivalents would be within the level of ordinary skill in the art. KSR International Co. v. Teleflex Inc., 550 U.S.--,82 USPQ2d 1385 (2007).
Regarding claim 21, Cho in view of Chien in view of Cool shows (see, e.g., Cho: fig. 1M that is inverted) that the forming of the backside RDL structure RDL1/RDL2 comprises:
Forming the pillar structure 14 of the backside connector 14/54 in the first polymer layer 28a/18a
Regarding claim 22, Cho in view of Chien in view of Cool shows (see, e.g., Cho: fig. 1M that is inverted) that the forming of the backside RDL structure RDL1/RDL2 comprises:
Forming a second polymer layer PM1 on the first polymer layer 28a/18a
Forming the tapered portion of the backside connector 14/54 in the second polymer layer PM1, such that a contact surface of the tapered portion contacts the pillar structure 14
Regarding claim 23, Cho in view of Chien in view of Cool shows (see, e.g., Cho: fig. 1M that is inverted) that the forming of the tapered portion comprises forming the tapered portion such that a width of the contact surface is less than a width of the pillar structure 14.
Regarding claim 24, Cho in view of Chien in view of Cool shows (see, e.g., Cho: fig. 1M that is inverted) that the forming of the backside RDL structure RDL1/RDL2 further comprises forming the first RDL RDL1 on the second polymer layer PM1 and in contact with the tapered portion, such that the second polymer layer PM1 is between the first RDL RDL1 and the pillar structure 14.
Regarding claim 25, Cho in view of Chien in view of Cool shows (see, e.g., Cho: fig. 1M that is inverted) that forming a through silicon via (TSV) 37 on the backside RDL structure RDL1/RDL2 such that the TSV 37 is electrically coupled to the pillar structure 14, wherein the attaching of the semiconductor die 45 to the backside RDL structure RDL1/RDL2 is performed such that the semiconductor die 45 is adjacent the TSV 37 on the backside RDL structure RDL1/RDL2.
Regarding claim 27, Cho in view of Chien in view of Cool shows (see, e.g., Cho: fig. 1M that is inverted) that the forming of the encapsulation layer 48a comprises forming the encapsulation layer 48a around the semiconductor die 45 and the TSV 37.
Regarding claim 28, Cho in view of Chien in view of Cool shows (see, e.g., Cho: fig. 1M that is inverted) that:
Forming a solder ball 56 (see, e.g., Cho: par. [0058]) on an under-bump metallurgy (UBM) layer RDL40 (see, e.g., Cho: par. [0057], and [0056]) of the frontside RDL structure RDL10/RDL20/RDL30
Forming a solder ball 54 (see, e.g., Cho: par. [0060]) on a pillar structure 14 of the backside RDL structure RDL1/RDL2
Regarding claim 29, Cho shows (see, e.g., Cho: fig. 1M that is inverted) most aspects of a method of forming a package, comprising:
Forming a backside redistribution layer (RDL) structure RDL1/RDL2 including a first dielectric layer 28a/18a and a pillar structure 14 in the first dielectric layer 28a/18a
Forming a molded portion 48a including a semiconductor die 45 on the backside RDL structure RDL1/RDL2
Forming a frontside RDL structure RDL10/RDL20/RDL30 on the molded portion 48a
However, Cho fails (see, e.g., Cho: fig. 1M that is inverted) to show that the first dielectric layer includes a dark material. Chien, in a similar device to Cho, shows (see, e.g., Chien: figs. 4A-4B) a dielectric layer 490 that includes a black material (see, e.g., Chien: par. [0034], and claim 10). Moreover, Chien shows (see, e.g., Chien: figs. 4A-4B) that the dielectric layer is part of the RDL, it has a low reflectivity value and reduces or prevents the incoming light from reflecting or falling on to the edges of the device by reducing or eliminating the edge flares (see, e.g., Chien: par. [0033]).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the dielectric layer with dark material of Chien in the method of Cho, to provide low reflectivity values, and to reduce or prevent the incoming light from reflecting or falling on to the edges of the device by reducing or eliminating the edge flares.
However, Cho in view of Chien fails to (see, e.g., Chien: figs. 4A-4B) show that the dark material (see, e.g., Chien: par. [0034], and claim 10) includes a dye. Cho in view of Chien is actually silent about the content of the dark material (see, e.g., Chien: par. [0034], and claim 10). Cool, in a similar device to Cho in view of Chien, shows (see, e.g., Cool: fig. 3) that inactive border area IA may contain circuits, signal lines, and other structures that do not emit light for forming images. To hide circuitry and other components in border area IA from view by a user of device 10, the underside of the outermost layer of display 14 (e.g., the display cover layer or other display layer) may be coated with an opaque masking material. Cool also shows that the dark material from the opaque masking material is a black ink with a dye (e.g., a polymer containing visible-light-absorbing dye and/or pigment that imparts a black color to the polymer) (see, e.g., Cool: par. [0029]).
Therefore, it would have been obvious at the time of the invention to one of ordinary skill in the art to use either the dark material of Cho in view of Chien or the dark material with a dye of Cool because these were recognized in the semiconductor art for their use as materials for opaque mask structures in semiconductor device packages, as taught by Cho in view of Chien and by Cool, and selecting between known equivalents would be within the level of ordinary skill in the art. KSR International Co. v. Teleflex Inc., 550 U.S.--,82 USPQ2d 1385 (2007).
Regarding claim 30, Cho in view of Chien in view of Cool shows (see, e.g., Cho: fig. 1M that is inverted) that:
Forming the first dielectric layer 28a/18a on a carrier substrate PM1/PM2/PM3
Forming the pillar structure 14 in the first dielectric layer 28a/18a
Forming a second dielectric layer PM1 on the first dielectric layer 28a/18a
Forming a via in the second dielectric layer PM1 such that a contact surface of the via contacts the pillar structure 14
Regarding claim 31, Cho in view of Chien in view of Cool shows (see, e.g., Cho: fig. 1M that is inverted) that:
The forming of the backside RDL structure RDL1/RDL2 comprises forming a first RDL RDL1 on the second dielectric layer PM1 and connected to the via
The forming of the via is performed such that a width of the via decreases in a direction away from the first RDL RDL1
Regarding claim 32, Cho in view of Chien in view of Cool shows (see, e.g., Cho: fig. 1M that is inverted) that the forming of the first RDL RDL1 is performed such that the second dielectric layer PM1 is between the first RDL RDL1 and the pillar structure 14.
Regarding claim 33, Cho in view of Chien in view of Cool shows (see, e.g., Cho: fig. 1M that is inverted) that the forming of the via comprises forming the via such that the width of the contact surface of the via is less than the width of the pillar structure 14.
Regarding claim 34, Cho in view of Chien in view of Cool shows (see, e.g., Cho: fig. 1M that is inverted) that the forming of the molded portion 48a comprises:
Forming a through silicon via (TSV) 37 on the backside RDL structure RDL1/RDL2 and electrically coupled to the pillar structure 14
Attaching the semiconductor die 45 to the backside RDL structure RDL1/RDL2 such that the semiconductor die 45 is adjacent to the TSV on the backside RDL structure RDL1/RDL2
Regarding claim 36, Cho in view of Chien in view of Cool shows (see, e.g., Cho: fig. 1M that is inverted) that the forming of the molded portion 48a comprises forming an encapsulation layer 48a of the molded portion 48a around the semiconductor die 45 and the TSV 37.
Regarding claim 37, Cho in view of Chien in view of Cool shows (see, e.g., Cho: fig. 1M that is inverted) that:
Forming a solder ball 56 (see, e.g., Cho: par. [0057], and [0058]) on an under-bump metallurgy (UBM) layer RDL40 (see, e.g., Cho: par. [0056]) of the frontside RDL structure RDL10/RDL20/RDL30
Forming a solder ball 54 (see, e.g., Cho: par. [0060]) on a pillar structure 14 of the backside RDL structure RDL1/RDL2
Regarding claim 38, Cho shows (see, e.g., Cho: fig. 1M that is inverted) all aspects of a method of forming a package, comprising:
Forming a first distribution layer (RDL) structure RDL1 including a first polymer layer 28a/18a (see, e.g., Cho: par. [0036], and [0037]), a backside connector 14/54 comprising a metal pillar 14 and a via connected to the metal pillar 14 (see, e.g., Cho: par. [0013])
Forming a molded portion 48a including a through silicon via (TSV) 37 on the backside RDL structure RDL1/RDL2, wherein the TSV 37 is electrically coupled to the backside connector 15/54
Forming a second RDL structure RDL2 on the molded portion 48a
However, Cho fails (see, e.g., Cho: fig. 1M that is inverted) to show that the first polymer layer includes a dark material. Chien, in a similar device to Cho, shows (see, e.g., Chien: figs. 4A-4B) a polymer layer 490 that includes a black material (see, e.g., Chien: par. [0034], and claim 10). Moreover, Chien shows (see, e.g., Chien: figs. 4A-4B) that the polymer layer is part of the RDL, it has a low reflectivity value and reduces or prevents the incoming light from reflecting or falling on to the edges of the device by reducing or eliminating the edge flares (see, e.g., Chien: par. [0033]).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the polymer layer with dark material of Chien in the method of Cho, to provide low reflectivity values, and to reduce or prevent the incoming light from reflecting or falling on to the edges of the device by reducing or eliminating the edge flares.
However, Cho in view of Chien fails to (see, e.g., Chien: figs. 4A-4B) show that the dark material (see, e.g., Chien: par. [0034], and claim 10) includes a dye. Cho in view of Chien is actually silent about the content of the dark material (see, e.g., Chien: par. [0034], and claim 10). Cool, in a similar device to Cho in view of Chien, shows (see, e.g., Cool: fig. 3) that inactive border area IA may contain circuits, signal lines, and other structures that do not emit light for forming images. To hide circuitry and other components in border area IA from view by a user of device 10, the underside of the outermost layer of display 14 (e.g., the display cover layer or other display layer) may be coated with an opaque masking material. Cool also shows that the dark material from the opaque masking material is a black ink with a dye (e.g., a polymer containing visible-light-absorbing dye and/or pigment that imparts a black color to the polymer) (see, e.g., Cool: par. [0029]).
Therefore, it would have been obvious at the time of the invention to one of ordinary skill in the art to use either the dark material of Cho in view of Chien or the dark material with a dye of Cool because these were recognized in the semiconductor art for their use as materials for opaque mask structures in semiconductor device packages, as taught by Cho in view of Chien and by Cool, and selecting between known equivalents would be within the level of ordinary skill in the art. KSR International Co. v. Teleflex Inc., 550 U.S.--,82 USPQ2d 1385 (2007).
Regarding claim 39, Cho in view of Chien in view of Cool shows (see, e.g., Cho: fig. 1M that is inverted) that
Forming a solder ball 56 (see, e.g., Cho: par. [0057], and [0058]) on an under-bump metallurgy (UBM) layer RDL40 (see, e.g., Cho: par. [0056]) of the frontside RDL structure RDL10/RDL20/RDL30
Forming a solder ball 54 (see, e.g., Cho: par. [0060]) on a pillar structure 14 of the backside RDL structure RDL1/RDL2
Regarding claims 26 and 35, Cho in view of Chien in view of Cool shows (see, e.g., Cho: fig. 1M that is inverted) most aspects of a method of forming a package, comprising forming of the TSV 37 and of the pillar structure 14.
Cho in view of Chien in view of Cool shows (see, e.g., Cho: fig. 1M that is inverted) that forming of the TSV 37 is performed such that a width of the pillar structure 14 is in a range from 80% to 120% of the width of the TSV 37.
However, differences in the width ranges will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such width range values are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955).
Accordingly, since the applicant has not established the criticality (see next paragraph) of ranges of the width of the pillar structure and of the width of the TSV, it would have been obvious to one of ordinary skill in the art to use these values in the device of Cho in view of Chien in view of Cool.
CRITICALITY
The specification contains no disclosure of either the critical nature of the claimed width range values or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Response to Arguments
Examiner has read and considered Applicants’ arguments, and finds them not persuasive in view of the new grounds of rejection. Applicants’ arguments for claims 16, 29, and 38 have been considered but are moot in view of the new grounds of rejection.
The applicants argue:
Cho in view of Chien fails to anticipate or render obvious the amended limitation of "… a first polymer layer that includes dark material that includes a dye", as recited in claims 16, 29, and 38.
The examiner responds:
In view of the new grounds of rejection, Cool, in a similar device to Cho in view of Chien, shows (see, e.g., Cool: fig. 3) that inactive border area IA may contain circuits, signal lines, and other structures that do not emit light for forming images. To hide circuitry and other components in border area IA from view by a user of device 10, the underside of the outermost layer of display 14 (e.g., the display cover layer or other display layer) may be coated with an opaque masking material. Cool also shows that the dark material from the opaque masking material is a black ink with a dye (e.g., a polymer containing visible-light-absorbing dye and/or pigment that imparts a black color to the polymer) (see, e.g., Cool: par. [0029]).
Therefore, it would have been obvious at the time of the invention to one of ordinary skill in the art to use either the dark material of Cho in view of Chien or the dark material with a dye of Cool because these were recognized in the semiconductor art for their use as materials for opaque mask structures in semiconductor device packages, as taught by Cho in view of Chien and by Cool, and selecting between known equivalents would be within the level of ordinary skill in the art. KSR International Co. v. Teleflex Inc., 550 U.S.--,82 USPQ2d 1385 (2007).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIBERIU DAN ONUTA whose telephone number is (571) 270-0074 and between the hours of 9:00 AM to 5:00 PM (Eastern Standard Time) Monday through Friday or by e-mail via Tiberiu.Onuta@uspto.gov. If attempts to reach the examiner by telephone or email are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705.
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/TIBERIU DAN ONUTA/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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