Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 05/11/2026 has been entered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5, and 7-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Farrar (Patent No.: US 6,509,590 B1).
Regarding Claim 1, Farrar discloses a semiconductor device, comprising: an active region comprising one or more active semiconductor cells (Col. 3, L 27 – Col. 4, L 67; Figs. 1-5 – active region comprising transistors 14a and 14b); a metallization structure on the active region (Col. 3, L 27 – Col. 4, L 67; Figs. 1-5 – metallization structure comprising layer 22’); and wherein the metallization structure comprises an aluminum-beryllium alloy (Col. 3, L 27 – Col. 4, L 67; Figs. 1-5 – metallization structure 22’ comprising aluminum-beryllium alloy).
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Regarding Claim 2, Farrar, as applied to claim 1, discloses
the semiconductor device, wherein the metallization structure is one or more of a contact, interconnect, or bonding pad for the semiconductor device (Col. 3, L 27 – Col. 4, L 67; Figs. 1-5 – contact and/or interconnect and/or bonding pad).
Regarding Claim 3, Farrar, as applied to claim 1, discloses
the semiconductor device, wherein the metallization structure further comprises copper (Col. 3, L 27 – Col. 4, L 67; Figs. 1-5 - metallization structure 22 comprises copper, beryllium and aluminum).
Regarding Claim 5, Farrar, as applied to claim 1, discloses
the semiconductor device, wherein the metallization structure comprises a range of about 0.1% beryllium to about 3% beryllium (Col. 3, L 27 – Col. 4, L 67; claim 7; Figs. 1-5 – claim 7 of this prior art teaches that the metallization structure 22’ comprises, at least, in one embodiment, 1% of beryllium).
Regarding Claim 7, Farrar, as applied to claim 1, discloses
the semiconductor device, wherein the metallization structure comprises a ternary beryllium alloy (Col. 3, L 27 – Col. 4, L 67; also see Table 1 – alloy comprising beryllium, aluminum, copper).
Regarding Claim 8, Farrar, as applied to claim 7, discloses
the semiconductor device, wherein the ternary beryllium alloy comprises aluminum, beryllium, and a ternary element, wherein the ternary element comprises silver, copper, magnesium, silicon, titanium, vanadium, or zinc (Col. 4, L 8-40 – copper).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 6, 10 and 16-17 are rejected under 35 U.S.C. as obvious over Farrar (Patent No.: US 6,509,590 B1), as applied to claim 1.
Regarding Claim 6, Farrar, as applied to claim 1, does not disclose
the semiconductor device, wherein the metallization structure comprises a range of about 0.2% beryllium to about 0.5% beryllium.
However, Farrar teaches
the semiconductor device, wherein the metallization structure comprises a range of about 1% to 40% (Col. 3, L 27 – Col. 4, L 67; claims 1-29). This prior art teaches that adding beryllium to aluminum enhances stiffness while maintaining a low mass density. However, it is also understood that adding too much beryllium would increase electrical resistance and it is also toxic Thus, the optimal amount of beryllium to add depends on the specific application in which it will be used. Farrar discloses the claimed invention except for the semiconductor device, wherein the metallization structure comprises a range of about 0.2% beryllium to about 0.5% beryllium. It would have been obvious to one having ordinary skill in the art at the time the invention was filed to adapt the semiconductor device, wherein the metallization structure comprises a range of about 0.2% beryllium to about 0.5% beryllium, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
Regarding Claim 10, Farrar, as applied to claim 1, discloses
the semiconductor device, wherein the metallization structure comprises a contact and/or an interconnect for a transistor (Col. 3, L 27 – Col. 4, L 67; Figs. 1-5 – this prior art teaches an interconnect connecting two transistors). Farrar does not explicitly disclose
the semiconductor device, wherein the metallization structure comprises a source contact, a drain contact, or a gate contact for a MOSFET.
In short, whereas Farrar teaches materials used for contacts or interconnects used in integrated circuit devices, the instant application teaches potential materials for source contacts, drain contacts etc. for MOSFET type. It would have been obvious to a person of ordinary skills in the art at the time the invention was effectively filed that the contact materials used by Farrar for transistors could also be potentially used for the source and drain contacts for a MOSFET device.
Farrar discloses the claimed invention except for the semiconductor device, wherein the metallization structure comprises a source contact, a drain contact, or a gate contact for a MOSFET. It would have been obvious to one having ordinary skill in the art at the time the invention was filed to adapt the semiconductor device, wherein the metallization structure comprises a source contact, a drain contact, or a gate contact for a MOSFET, since it has been held to be within the general skill of a worker in the art to employ/use a known technique to improve similar devices (methods, products) in the same way is obvious. KSR International Co. v Teleflex Inc., 550 U.S.__, __, 82 USPQ2d 1385, 1395-97 (2007)
Regarding Claim 16, Farrar, as applied to claim 1, does not explicitly disclose the semiconductor device, wherein the one or more active semiconductor cells comprise one or more silicon carbide-based MOSFETs (this prior art teaches a metallization structure comprising aluminum-beryllium alloy to connect two transistors of an integrated circuit; it does not expressly state that the active semiconductor cells comprise one or more silicon carbide-based MOSFETs; it however, mentions that the metallization structure might be formed on silicon-on-insulator, silicon-on-sapphire, and other advanced structure (Col. 3, L 10 – Col. 4, L 67)).
In short, whereas Farrar teaches the one or more active semiconductor cells comprise one or more of silicon-on-insulator-based, silicon-on-sapphire-based and other advanced structure-based transistors , the instant application teaches the one or more active semiconductor cells comprise one or more silicon carbide-based MOSFETs. It would have been obvious to a person of ordinary skills in the art at the time the invention was effectively filed that the contact materials used by Farrar for transistors could also be potentially used for contacts/interconnects in silicon carbide-based MOSFETs.
Farrar discloses the claimed invention except for the semiconductor device, wherein the one or more active semiconductor cells comprise one or more silicon carbide-based MOSFETs. It would have been obvious to one having ordinary skill in the art at the time the invention was filed to adapt wherein the one or more active semiconductor cells comprise one or more silicon carbide-based MOSFETs, since it has been held to be within the general skill of a worker in the art to apply a known technique to a known device (method, or product) ready for improvement to yield predictable results is obvious. KSR International Co. v Teleflex Inc., 550 U.S.__, __, 82 USPQ2d 1385, 1395-97 (2007)
Regarding Claim 17, Farrar, as applied to claim 1, does not explicitly disclose the semiconductor device, wherein the one or more active semiconductor cells comprise one or more silicon carbide-based Schottky diodes (this prior art teaches a metallization structure comprising aluminum-beryllium alloy to connect two transistors of an integrated circuit; it does not expressly state that the active semiconductor cells comprise one or more silicon carbide-based MOSFETs; it however, mentions that the metallization structure might be formed on silicon-on-insulator, silicon-on-sapphire, and other advanced structure (Col. 3, L 10 – Col. 4, L 67)).
In short, whereas Farrar teaches the one or more active semiconductor cells comprise one or more of silicon-on-insulator-based, silicon-on-sapphire-based and other advanced structure-based transistors , the instant application teaches the one or more active semiconductor cells comprise one or more silicon carbide-based Schottky diodes. It would have been obvious to a person of ordinary skills in the art at the time the invention was effectively filed that the contact materials used by Farrar for transistors could also be potentially used for contacts/interconnects in silicon carbide-based Schottky diodes.
Farrar discloses the claimed invention except for the semiconductor device, wherein the one or more active semiconductor cells comprise one or more silicon carbide-based Schottky diodes. It would have been obvious to one having ordinary skill in the art at the time the invention was filed to adapt wherein the one or more active semiconductor cells comprise one or more silicon carbide-based Schottky diodes, since it has been held to be within the general skill of a worker in the art to apply a known technique to a known device (method, or product) ready for improvement to yield predictable results is obvious. KSR International Co. v Teleflex Inc., 550 U.S.__, __, 82 USPQ2d 1385, 1395-97 (2007)
Claims 11-12, 15 and 18 are rejected under 35 U.S.C. as obvious over Farrar (Patent No.: US 6,509,590 B1), as applied to claim 1, further in view of Chen et al. (Patent No.: US 10,964,788 B1).
Regarding Claim 11, Farrar, as applied to claim 1, does not explicitly disclose
the semiconductor device, wherein the semiconductor device further comprises a passivation layer.
However, Chen et al. teaches
the semiconductor device, wherein the semiconductor device further comprises a passivation layer (Col. 11, L 21 – 39; Fig. 5 – passivation layer 138 (protective layer) is formed on metallization structure comprising source electrode 128 to protect the metallization structure from moisture, for example). It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings of Chen et al. to adapt the semiconductor device, wherein the semiconductor device of Farrar further comprises a passivation layer in order to protect the underlying metallization structure from the influx of moisture.
Regarding Claim 12, modified Farrar, as applied to claim 11, discloses
the semiconductor device, wherein the passivation layer comprises silicon nitride (Chen et al - Col. 11, L 21 – 39).
Regarding Claim 15, Farrar, as applied to claim 1, does not explicitly disclose the semiconductor device, wherein the one or more active semiconductor cells comprise a wide band gap semiconductor (this prior art teaches a metallization structure comprising aluminum-beryllium alloy to connect two transistors of an integrated circuit; it does not expressly state that the active semiconductor cells comprise a wide band gap semiconductor; it however, mentions that the metallization structure might be formed on silicon-on-insulator, silicon-on-sapphire, and other advanced structures (Col. 3, L 10 – Col. 4, L 67)).
However, Chen et al. teaches
the semiconductor device, wherein the one or more active semiconductor cells comprise a wide band gap semiconductor (Col. 4, L 5 – 38 – silicon carbide or aluminum nitride or gallium nitride).
In short, Farrar discloses an aluminum-beryllium metallization structure formed on one or more active semiconductor cells; with the active semiconductor cells comprising silicon-on-insulator or silicon-on-sapphire or other advanced structures. Chen et al., on the other hand, explicitly discloses forming a beryllium containing metallization structure on semiconductor cells comprising a wide band gap semiconductor.
Farrar discloses the claimed invention except for the semiconductor device, wherein the one or more active semiconductor cells comprise a wide band gap semiconductor. It would have been obvious to one having ordinary skill in the art at the time the invention was filed to adapt the semiconductor device, wherein the one or more active semiconductor cells comprise a wide band gap semiconductor, since it has been held to be within the general skill of a worker in the art to apply a known technique to a known device (method, or product) ready for improvement to yield predictable results is obvious. KSR International Co. v Teleflex Inc., 550 U.S.__, __, 82 USPQ2d 1385, 1395-97 (2007)
Regarding Claim 18, Farrar, as applied to claim 1, does not explicitly disclose the semiconductor device, wherein the one or more active semiconductor cells comprise one or more Group III-nitride based high electron mobility transistor devices (this prior art teaches a metallization structure comprising aluminum-beryllium alloy to connect two transistors of an integrated circuit; it does not expressly state that the active semiconductor cells comprise a wide band gap semiconductor; it however, mentions that the metallization structure might be formed on silicon-on-insulator, silicon-on-sapphire, and other advanced structure (Col. 3, L 10 – Col. 4, L 67)).
However, Chen et al. teaches
the semiconductor device, wherein the one or more active semiconductor cells comprise one or more Group III-nitride based high electron mobility transistor devices (Col. 4, L 5- Col. 5, L 8). In short, Farrar discloses an aluminum-beryllium metallization structure formed on one or more active semiconductor cells; with the active semiconductor cells comprising silicon-on-insulator or silicon-on-sapphire or other advanced structures. Chen et al., on the other hand, explicitly discloses forming a beryllium containing metallization structure on semiconductor cells comprising one or more Group III-nitride based high electron mobility transistor devices.
Farrar discloses the claimed invention except for the semiconductor device, wherein the one or more active semiconductor cells comprise one or more Group III-nitride based high electron mobility transistor devices. It would have been obvious to one having ordinary skill in the art at the time the invention was filed to adapt the semiconductor device, wherein the one or more active semiconductor cells comprise one or more Group III-nitride based high electron mobility transistor devices, since it has been held to be within the general skill of a worker in the art to apply a known technique to a known device (method, or product) ready for improvement to yield predictable results is obvious. KSR International Co. v Teleflex Inc., 550 U.S.__, __, 82 USPQ2d 1385, 1395-97 (2007)
Claim 9 is rejected under 35 U.S.C. 103 as obvious over Farrar (Patent No.: US 6,509,590 B1), as applied to claim 7, further in view of Zhou et al. (“Precipitation behavior and properties of aged Cu-0.23Be-0.84Co alloy” - 2015)
Regarding Claim 9, Farrar, as applied to claim 7, discloses
the semiconductor device, wherein the ternary beryllium alloy comprises aluminum, beryllium, and a ternary element, (Col. 3, L 27 – Col. 4, L 67; also see Table 1 – beryllium, aluminum, copper)
Farrar does not explicitly disclose
the semiconductor device, wherein the ternary element comprises cobalt. However, Zhou et al. teaches the semiconductor device, wherein the ternary element comprises cobalt (Page 920; Introduction Section – this prior art teaches Cu-Be alloys with a small amount of cobalt are widely used, wherein the alloy has good electrical and thermal conductivity, high strength and hardness and low elastic modulus). It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings of Zhou et al. to adapt the semiconductor device, wherein the ternary element of Farar comprises cobalt in order to form an electrical contact with proper hardness and electrical and thermal properties.
Claims 13-14 are rejected under 35 U.S.C. 103 as obvious over Farrar (Patent No.: US 6,509,590 B1), as applied to claim 11, further in view of Weyers (Pub. No.: US 2020/0243505 A1)
Regarding Claim 13, modified Farrar, as applied to claim 11, does not explicitly disclose
the semiconductor device, wherein the passivation layer comprises a polymer. However, Weyers teaches the semiconductor device, wherein the passivation layer comprises a polymer (Par. 0031; Fig. 6 – this prior art teaches that a passivation layer such as a polyimide may be arranged over the gate and source pads). In a nutshell, Modified Farrar teaches the passivation layer comprises silicon nitride. Weyers, on the other hand teaches that the passivation layer comprises a polymer. In other words, use of silicon nitride as well as polymers in passivation layers have been well-documented before this invention was effectively filed. Modified Farrar discloses the claimed invention except for the semiconductor device, wherein the passivation layer comprises a polymer. It would have been obvious to one having ordinary skill in the art at the time the invention was filed to adapt the semiconductor device, wherein the passivation layer comprises a polymer, since it has been held that the simple substitution of one known element for another to obtain predictable results is obvious.
Regarding Claim 14, modified Farrar, as applied to claim 13, discloses
the semiconductor device, wherein the polymer comprises polyimide (Weyers - Par. 0031).
Claim 19 is rejected under 35 U.S.C. 103 as obvious over Nakano (Pub. No.: US 2012/0049202 A1) in view of Zhou et al. (“Precipitation behavior and properties of aged Cu-0.23Be-0.84Co alloy” - 2015) and Farrar (Patent No.: US 6,509,590 B1).
Regarding Claim 19, Nakano discloses a semiconductor device, comprising: an active region comprising one or more silicon carbide-based MOSFETs (abstract; Par. 0152-0157; Fig, 3 - active region comprising silicon carbide-based MOSFETs); one or more metallization structures on the active region, the one or more metallization structures comprising a bonding pad associated with a source contact and a backside metallization structure associated with a drain contact for the semiconductor device (Par. 0152-0157; Fig. 3 – backside metallization structure 37; frontside metallization structure 34 associated with source contact; both the metallization structures are made of aluminum (Al), gold (Au), silver (Ag), copper (Cu), an alloy thereof or a metallic material containing the same); and wherein the one or more metallization structure comprises copper (Cu) or aluminum (Al) or an alloy thereof (Par. 0152-0157; Fig. 3).
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Nakano does not explicitly disclose
wherein the one or more metallization structures comprise beryllium.
However, Zhou et al., at least, implicitly teaches
wherein the one or more metallization structures comprise beryllium (Page 920; Introduction Section – this prior art teaches Cu-Be alloys are widely used in the components of electronics industry wherein the alloy comprises 0.2 – 2.0 wt% Be; this alloy has good electrical and thermal conductivity, high strength and hardness and low elastic modulus). Furthermore, Farrar teaches
wherein the one or more metallization structures comprise beryllium (Col. 3, L 27 – Col. 4, L 67 - this prior art teaches that adding beryllium to aluminum enhances stiffness while maintaining a low mass density). It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings of Zhou et al. and Farrar to adapt the semiconductor device, wherein the one or more metallization structures of Nakano comprise beryllium in order to tailor the properties of the metallization structure to meet the demand of the specific application where it will be used.
Claim 35 is rejected under 35 U.S.C. as obvious over Farrar (Patent No.: US 6,509,590 B1) in view of Chen et al. (Patent No.: US 10,964,788 B1).
Regarding Claim 35, Farrar discloses a method, comprising: depositing a metallization structure on an active region comprising one or more semiconductor cells (Col. 3, L 27 – Col. 4, L 67; Figs. 1-5 – active region comprising transistors 14a and 14b; metallization structure 22); and wherein the metallization structure comprises an aluminum-beryllium alloy (Col. 3, L 27 – Col. 4, L 67; Figs. 1-5 – metallization structure 22’ comprising aluminum-beryllium alloy).
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Farrar does not explicitly disclose the method, comprising: an active region comprising one or more wide band gap semiconductor cells (this prior art teaches a metallization structure comprising aluminum-beryllium alloy to connect two transistors of an integrated circuit; it does not expressly state that the active semiconductor cells comprise a wide band gap semiconductor; it however, mentions that the metallization structure might be formed on silicon-on-insulator, silicon-on-sapphire, and other advanced structure (Col. 3, L 10 – Col. 4, L 67)).
However, Chen et al. teaches
the method, comprising: an active region comprising one or more wide band gap semiconductor cells (Col. 4, L 5 – 38, – silicon carbide or aluminum nitride or gallium nitride; Col. 4, L 48 – Col. 5, L 8; Fig. 5 – active region comprising channel layer 106; Col. 8, L 25 – Col. 9, L 50; Fig. 5 – metallization structure comprising source electrode 128)). In short, Farrar discloses an aluminum-beryllium metallization structure formed on one or more active semiconductor cells; with the active semiconductor cells comprising silicon-on-insulator or silicon-on-sapphire or other advanced structures. Chen et al., on the other hand, explicitly discloses forming a beryllium containing metallization structure on semiconductor cells comprising a wide band gap semiconductor.
Farrar discloses the claimed invention except for the method, comprising: an active region comprising one or more wide band gap semiconductor cells. It would have been obvious to one having ordinary skill in the art at the time the invention was filed to adapt the method, comprising: an active region comprising one or more wide band gap semiconductor cells, since it has been held to be within the general skill of a worker in the art to apply a known technique to a known device (method, or product) ready for improvement to yield predictable results is obvious. KSR International Co. v Teleflex Inc., 550 U.S.__, __, 82 USPQ2d 1385, 1395-97 (2007)
Response to Arguments
Applicants’ arguments filed on 05/11/20256 have been fully considered but they are moot because of the new grounds of rejection necessitated by amendments made to the claims.
Conclusion
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05/28/2026
/SYED I GHEYAS/Primary Examiner, Art Unit 2893