DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I / Species I and claims 1-14 in the reply filed on 10/13/2025 is acknowledged. Applicant amended Claims 15-20 so that the claims are directed to Invention I.
Claim 5 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 10/13/2025.
Applicant's election with traverse of Modification 1A in the reply filed on 10/13/2025 is acknowledged. The traversal is on the ground(s) that the embodiments in “Modification 1A and Modification 1B are not mutually exclusive to each other”. This is not found persuasive because in Modification 1A as shown in Figs. 23A/B and 24, the backside contact 392a does not contact and does not overlap multiple S/D regions. While in Modification 1B as shown in Fig 25, the backside contact 392b contacts and overlaps with multiple S/D regions. Thus, the above modifications are independent and distinct as described above. There will be a serious search and/or examination burden for the patentably distinct species as set forth above because at least the following reason(s) apply:
the species or groupings of patentably indistinct species require a different field of search (e.g., employing different search strategies or search queries); and/or
the prior art applicable to one species would not likely be applicable to another species.
The requirement is still deemed proper and is therefore made FINAL.
Additionally, claims 4, 8 and 18 are also withdrawn as they are not directed to the elected species.
Claim 4 recites the limitation, “wherein the first backside conductive feature extends along a direction to also form on the exposed bottom surface of the second epitaxial S/D feature.” This is directed to Modification 1B as shown in Fig. 25. The elected species is Modification 1A as shown in Figs. 23A/B and 24.
Claim 8 recites the limitation, “wherein after the forming of the first backside conductive feature (392d/392e/392f in Figs. 49/50/51 respectively), a portion of the dielectric feature (700) remains over a bottom surface of the first epitaxial S/D feature (800a).” This is directed to Species II as shown in Figs. 49, 50 and 51. In the elected Species I, Modification 1A, no portion of dielectric feature is remaining as shown in Figs. 23A/B and 24.
Claim 18 recites the limitation, “further comprising a silicon nitride cap (700) on a first portion of the bottom surface of the S/D feature (800a), wherein the backside via (392d/392e/392f in Figs. 49/50/51 respectively) is disposed on a second portion of the bottom surface of the S/D feature.” This is directed to Species II as shown in Figs. 49, 50 and 51. In the elected Species I, Modification 1A, no portion of dielectric feature is remaining as shown in Figs. 23A/B and 24.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims.
Claim 3 recites the limitation, “forming a second backside trench that exposes a bottom surface of the second epitaxial S/D feature; and forming a second backside conductive feature in the second backside trench and on the exposed bottom surface of the second epitaxial S/D feature, wherein a top surface of the second backside conductive feature is formed under the bottommost surface of the gate stack.” This feature is not shown in any drawings.
Therefore, the features of the claim described above must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
In the “Amendments to the Specification”, filed on 10/13/2025, in Pg-2, the applicant incorrectly indicated to replace paragraph [0018] with paragraph [0040].
The examiner believes that the applicant meant to replace the old paragraph [0040] with the new paragraph [0040].
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 9-12, 14-17 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Yuh et al. (US 2023/0067715 A1), and further in view of Huang et al. (US 2022/0045052 A1).
Re Claim 1, Yuh teaches a method of forming a semiconductor device, comprising:
receiving a workpiece (Fig. 5A, para [0053]) having an active region (122+124, Fig. 5A, para [0042]) extending from a substrate (110, Fig. 5A, para [0041]), the active region is surrounded by an isolation structure (140, Fig. 5A, para [0051]), and portions of the active region (122+124) protrudes above a top surface of the isolation structure (140, see Fig. 5A);
forming a gate stack (220, Fig. 10A, para [0069]) over a channel region (122, Fig. 10A, para [0069]) of the active region;
forming a first source/drain (S/D) trench (recess R1, Fig. 6, para [0056]) adjacent the channel region (122) and extending into the substrate (110) below the top surface of the isolation structure (recess R1 extends below the top surface of 121 in Fig. 6, the top surface of 121 is at the same height as the top surface of isolation structure 140, compare Figs. 4 / 5A with Fig. 6);
forming a first epitaxial S/D feature (S/D 180+190, Fig. 7, para [0062]) in the first S/D trench (recess R1);
forming a first frontside metal contact (250, Fig. 11, para [0075]) over the first epitaxial S/D feature (S/D 180+190, Fig. 11);
forming a first backside trench (opening O2, Fig. 16, paras [0083] – [0084]) that exposes a bottom surface of the first epitaxial S/D feature (S/D 180+190, Fig. 16); and
forming a first backside conductive feature (360+340+350, Fig. 18, paras [0084] - [0086]) in the first backside trench (opening O2) and on the exposed bottom surface of the first epitaxial S/D feature (S/D 180+190).
Yuh shows that the top surface of the first backside conductive feature (360) is above the bottommost surface of the gate stack (220) in Fig. 18, and hence does not disclose a top surface of the first backside conductive feature is under the bottommost surface of the gate stack.
Related art, Huang discloses that a top surface of the backside conductive feature (138, Fig. 13, para [0054]) can be under the bottommost surface of the gate stack (112+114, Fig. 13, para [0026]).
One of ordinary skill in the art would realize that there are only two predictable outcomes - the top surface of the backside conductive feature can be above the bottommost surface of the gate stack as shown by Yuh or the top surface of the backside conductive feature can be under the bottommost surface of the gate stack as shown by Huang. Therefore, a person of ordinary skill has good reason to pursue both the known options and reach the claimed limitation with anticipated success, see KSR, 550 U.S. at 421, 82 USPQ2d at 1397.
Re Claim 2, Yuh modified by Huang teaches the method of claim 1, further comprising:
forming a second S/D trench (2nd recess R1, Fig. 6, para [0056]) adjacent the channel region (122) and extending into the substrate (110) below the top surface of the isolation structure (recess R1 extends below the top surface of 121 in Fig. 6, the top surface of 121 is at the same height as the top surface of isolation structure 140, compare Figs. 4 / 5A with Fig. 6);
forming a second epitaxial S/D feature (2nd S/D 180+190, Fig. 7, para [0062]) in the second S/D trench (2nd recess R1, Fig. 6); and
forming a second frontside metal contact (2nd 250, Fig. 11, para [0075]) over the second epitaxial S/D feature (2nd S/D 180+190).
Re Claim 3, Yuh modified by Huang teaches the method of claim 2, further comprising:
forming a second backside trench (trench where 360s will be formed, Fig 24, para [0111], also see Figs. 16-18, on how the backside trench and contacts are formed) that exposes a bottom surface of the second epitaxial S/D feature (bottom surface of 190s, which is 2nd S/D 180+190, , Fig. 24); and
forming a second backside conductive feature (360s, Fig. 24, para [0111]) in the second backside trench and on the exposed bottom surface of the second epitaxial S/D feature (bottom surface of 190s, which is 2nd S/D 180+190, , Fig. 24).
Yuh shows that the top surface of the second backside conductive feature (360s, Fig. 24) is above the bottommost surface of the gate stack (220) in Fig. 24, and hence does not disclose a top surface of the second backside conductive feature is under the bottommost surface of the gate stack.
Related art, Huang discloses that a top surface of the backside conductive feature (138, Fig. 13, para [0054]) can be under the bottommost surface of the gate stack (112+114, Fig. 13, para [0026]).
One of ordinary skill in the art would realize that there are only two predictable outcomes - the top surface of the backside conductive feature can be above the bottommost surface of the gate stack as shown by Yuh or the top surface of the backside conductive feature can be under the bottommost surface of the gate stack as shown by Huang. Therefore, a person of ordinary skill has good reason to pursue both the known options and reach the claimed limitation with anticipated success, see KSR, 550 U.S. at 421, 82 USPQ2d at 1397.
Re Claim 9, Yuh modified by Huang teaches the method of claim 1, wherein the forming of the first backside conductive feature (360+340+350, Fig. 18) further includes forming a dielectric barrier layer (340) along sidewalls of the first backside trench (see Fig. 18).
Re Claim 10, Yuh modified by Huang teaches the method of claim 1, wherein the first epitaxial S/D feature (S/D 180+190, Fig. 7) has a lightly doped outer layer (180, para [0062]) and a heavily doped inner layer (190, see Examiner notes below), and the first backside conductive feature (360+340+350, Fig. 18) is in direct contact with the heavily doped inner layer (190) of the first epitaxial S/D feature (S/D 180+190, Figs. 7 and 18).
Examiner notes that the term “heavily doped” is not quantifiable and reference art teaches that layer 180 is lightly doped compared to layer 190, which implies that 190 is doped heavier than 180, thus satisfying the claim limitation. The claim language does not preclude this treatment.
Re Claim 11, Yuh teaches a method of forming a semiconductor device, comprising:
receiving a semiconductor stack (stack 120, Fig. 4, para [0042]) having interleaved first (122, Fig. 4, para [0042]) and second semiconductor layers (124, Fig. 4, para [0042]), wherein the semiconductor stack extends above an isolation structure (140, Fig. 4, para [0051]) over a substrate (110, Fig. 4, para [0041]);
performing a deep etch to first and second S/D regions of the semiconductor stack to form deep S/D trenches (recess R1, Fig. 6, para [0056]) exposing side surfaces of the semiconductor stack (see Fig. 6, para [0056]), wherein the deep S/D trenches (recess R1) penetrate below a bottommost surface of the semiconductor stack (120) by an etch distance (marked “d1” in annotated Fig. 6 below);
forming S/D features (S/D 180+190, Fig. 7, para [0062]) in the deep S/D trenches,
removing the second semiconductor layers (removing layers 124 to create openings O1, Fig. 9 , para [0065]) from the semiconductor stack to form suspended semiconductor channels (122, see Fig. 9, para [0065]) in a channel region of the semiconductor stack;
forming a metal gate structure (220, Fig. 10A, para [0069]) over the channel region (122, Fig. 10A) and wrapping around each of the suspended semiconductor channels to form wrapped semiconductor channels (see Figs. 10A and 10B, para [0069]); and
forming a backside S/D trench by etching from a backside of the substrate (opening O2, Fig. 16, paras [0083] – [0084]) to expose a bottom surface of one of the S/D features (bottom surface of S/D 180+190, Fig. 16).
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Yuh does not explicitly state that a ratio of the etch distance to a thickness of any one of the first or the second semiconductor layers ranges between about 2 to 5. However, one of ordinary skill in the art would realize that the ratio of “d1” to the thickness of 122 or 124 in Fig. 6 is about 2. It would have been obvious to one of ordinary skill in the art, at the time of invention, to optimize the ratio and arrive at the claimed range. With respect to the limitations of the claim, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955). The optimization of the claimed ratio would have been obvious to one of ordinary skill in the art.
Additionally, Yuh shows that the bottom surface of the S/D (bottom surface of S/D 180+190 in Fig. 16) is above a bottommost portion of the metal gate structure (220, Fig. 16) wrapping around a bottommost layer of the wrapped semiconductor channels (122), and hence does not disclose that the bottom surface of the S/D is below a bottommost portion of the metal gate structure.
Related art, Huang discloses that a bottom surface of the S/D region (116PS, Fig. 13, para [0054]) is below a bottommost portion of the metal gate structure (112+114, Fig. 13, para [0026]).
One of ordinary skill in the art would realize that there are only two predictable outcomes - the bottom surface of the S/D can be above the bottommost surface of the gate stack as shown by Yuh or the bottom surface of the S/D can be under the bottommost surface of the gate stack as shown by Huang. Therefore, a person of ordinary skill has good reason to pursue both the known options and reach the claimed limitation with anticipated success, see KSR, 550 U.S. at 421, 82 USPQ2d at 1397.
Re Claim 12, Yuh modified by Huang teaches The method of claim 11, further comprising forming a backside via (360+340+350, Fig. 18, paras [0084] - [0086], Yuh) on the exposed bottom surface of the one of the S/D features (bottom surface of S/D 180+190, Fig. 18).
Re Claim 14, Yuh modified by Huang teaches the method of claim 11, wherein forming the metal gate structure (220, Fig. 10A, para [0069], Yuh) includes:
forming a dummy gate stack (150, Figs. 5A-5B, para [0053]) over the channel region of the semiconductor stack (122, Figs. 5A-5B and 10A);
performing a side etch on sidewalls of each of the second semiconductor layers (etching performed to form recess R2 in the second semiconductor layers 124, Fig. 6, para [0057]) in the deep S/D trenches (recess R1, Fig. 6), thereby forming air gaps (recess R2, Fig. 6);
forming inner spacers (170, Fig. 6, para [0059]) in the air gaps;
removing the dummy gate stack (removal of dummy gate 150, Fig. 9, para [0065]) to expose side surfaces of the semiconductor stack (side surfaces of 122 are exposed, Fig. 9); and
after the removing of the second semiconductor layers (removal of second semiconductor layers 124, Fig. 9, para [0065]), replacing the dummy gate stack and each of the removed second semiconductor layers with a metal gate feature (220, Figs. 10A and 10B, para [0069]).
Re Claim 15, Yuh teaches a method of forming a semiconductor device, comprising:
forming an active region (122+124, Fig. 5A, para [0042]) protruding from a substrate (110, Fig. 5A, para [0041]) and disposed between portions of an isolation structure (140, Fig. 5A, para [0051]);
forming a gate stack (220, Fig. 10A, para [0069]) disposed on a channel region (122, Fig. 10A, para [0069]) of the active region;
forming a source/drain (S/D) feature over a source/drain region of the active region (S/D 180+190, Fig. 7, para [0062]), wherein the S/D feature has an entrenched portion that extends below a top surface of the substrate (S/D 180+190 extends below a top surface of substrate 110, see Fig. 7);
forming a backside silicide layer (350, Fig. 18, para [0085]) on a bottom surface of the S/D feature (bottom surface of S/D 180+190); and
forming a backside via (360, Fig. 18, para [0086]) on a bottom surface of the backside silicide layer (350).
Yuh shows that the top surface of the first backside via (360) is above the bottommost surface of the gate stack (220) in Fig. 18, and hence does not disclose a top surface of the first backside via is below the bottommost surface of the gate stack.
Related art, Huang discloses that a top surface of the backside via (138, Fig. 13, para [0054]) can be below the bottommost surface of the gate stack (112+114, Fig. 13, para [0026]).
One of ordinary skill in the art would realize that there are only two predictable outcomes - the top surface of the backside via can be above the bottommost surface of the gate stack as shown by Yuh or the top surface of the backside conductive feature can be below the bottommost surface of the gate stack as shown by Huang. Therefore, a person of ordinary skill has good reason to pursue both the known options and reach the claimed limitation with anticipated success, see KSR, 550 U.S. at 421, 82 USPQ2d at 1397.
Re Claim 16, Yuh modified by Huang teaches the method of claim 15, wherein the S/D feature (S/D 180+190, Fig. 7, para [0062]) has a lightly doped outer layer (180, para [0062]) and a heavily doped inner layer (190, see Examiner notes below), and the backside via (360, Fig. 18) is in electrical contact with the heavily doped inner layer (190) by directly contacting the backside silicide layer (350, see Fig. 18).
Examiner notes that the term “heavily doped” is not quantifiable and reference art teaches that layer 180 is lightly doped compared to layer 190, which implies that 190 is doped heavier than 180, thus satisfying the claim limitation. The claim language does not preclude this treatment.
Re Claim 17, Yuh modified by Huang teaches the method of claim 15, wherein a width of the backside via along a lengthwise direction of the active region is smaller than a width of the S/D feature (portion of 360 has a width smaller than the width of 180+190 along the lengthwise direction, see Fig. 18).
Re Claim 19, Yuh modified by Huang teaches the method of claim 15, further comprising a silicon nitride barrier layer (340, Fig. 18, para [0084]) on sidewalls of the backside via (360, Fig. 18).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Yuh et al. (US 2023/0067715 A1) and Huang et al. (US 2022/0045052 A1), and further in view of Wei et al. (US 2022/0139911 A1).
Re Claim 13, Yuh modified by Huang teaches the method of claim 11, but does not disclose the following:
before the forming of the S/D features, forming dielectric caps in the deep S/D trenches, wherein the forming of the backside S/D trench includes etching through a dielectric cap in one of the deep S/D trenches.
.
However, related art Wei teaches formation of dielectric caps (364, Fig. 3H, para [0081]) before the formation of S/D features, followed by etching through the dielectric caps to form backside S/D trench (see Fig. 3O, para [0106]). Wei discloses that the dielectric caps provide sufficient “etch selectivity”, especially during the formation of backside trench, where etchants can selectively etch one material over the other, and thus define the boundaries of S/D regions more accurately (para [0059]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to incorporate the dielectric caps into the S/D trenches of Yuh as taught by Wei, because the dielectric caps provide sufficient “etch selectivity”, especially during the formation of backside trench, where etchants can selectively etch one material over the other, and thus define the boundaries of S/D regions more accurately (para [0059], Wei).
Rejection 2
Claims 15 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Wei et al. (US 2022/0139911 A1), and further in view of Yu et al. (US 2021/0408249 A1).
Re Claim 15, Wei teaches a method of forming a semiconductor device, comprising:
forming an active region (357, Fig. 3C, para [0063]) protruding from a substrate (350, Fig. 3C, para [0063]);
forming a gate stack (371, Fig. 3K, para [0095]) disposed on a channel region (375, Fig. 3K, para [0095]) of the active region;
forming a source/drain (S/D) feature (left 366 S/D, Fig. 3I, para [0089]) over a source/drain region of the active region, wherein the S/D feature has an entrenched portion that extends below a top surface of the substrate (left 366 S/D extends below the top surface of 350, see Fig. 3I);
forming a backside via (378, Fig. 3P, para [0108]), wherein a top surface of the backside via is below a bottommost portion of the gate stack (top surface of 378 is below the bottommost portion of the gate stack 371, see Fig. 3P).
Wei only shows details of one active semiconductor fin and hence does not disclose an isolation structure disposed between multiple fins.
However, related art Yu discloses that one can form multiple active fins (66, Fig. 1, para [0011]) on the substrate (50, Fig. 1, para [0011]), which are isolated by shallow trench isolation (STI) structures (68, Fig. 1, para [0011]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to form multiple active fins which are isolated by STI structures in the device of Wei, as taught by Yu. Thus, one can form multiple transistors on the same substrate, thus improving efficiency and reducing cost. Moreover, the STI structures isolate each of the transistors, thus eliminating any cross-talk between each transistor region.
Wei also does not disclose formation of silicide layer between the S/D feature and the backside via.
Related art Yu teaches a formation of silicide layer (129, Fig. 29B, para [0087]) between the S/D region (92, Fig. 29B, para [0087]) and the backside via (130, Fig. 29B, para [0089]). The silicidation layer is useful for better contact resistance and increasing thermal stability, resulting in better device performance (para [0009]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to form silicide layer between the S/D region and the backside via of Wei, as taught by Yu, because the silicidation layer provides better contact resistance and increasing thermal stability, resulting in better device performance (para [0009], Yu).
Re Claim 20, Wei modified by Yu teaches the method of claim 15, wherein the S/D feature is a first S/D feature (left 366 S/D, Fig. 3P, para [0089]), and the method further comprises:
forming a second S/D feature (right 366 S/D, Fig. 3P, para [0089]) over a second source/drain region of the active region; and
forming a backside dielectric cap (right 364, Fig. 3P, para [0081]) on a bottom surface of the second S/D feature (right 366 S/D, Fig. 3P), wherein the bottom surface of the of the first S/D feature is below the bottom surface of the second S/D feature (bottom surface of left 366 S/D is below the bottom surface of right 366 S/D, see Fig. 3P).
Allowable Subject Matter
Claims 6-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 6 is allowable at least for the reasons of, “before the forming of the first epitaxial S/D feature, forming a dielectric feature on a bottom surface of the first S/D trench, wherein the forming of the dielectric feature includes: conformally depositing a dielectric layer into the first S/D trench, performing a plasma treatment on a top surface of the dielectric layer, and selectively etching away the dielectric layer on sidewalls of the first S/D trench”. Yuh does not disclose formation of a dielectric layer on the bottom surface of the S/D trenches. Related art, Wei et al. (US 2022/0139911 A1) teaches formation of dielectric caps (364, Fig. 3H, para [0081]) on the bottom surface of the S/D trench, which includes conformally depositing a dielectric liner (364, Fig. 3G and selectively etching away the dielectric layer on sidewalls of the first S/D trench (364, Fig. 3H, para [0081]). However, Wei does not disclose “performing a plasma treatment on a top surface of the dielectric layer”. The prior art of record taken either single or in combination fails to teach or reasonably suggest the above limitation when taken in context of the independent claim 1, as a whole.
Claim 7 depends from claim 6 and is allowable at least for the reasons above.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Ganguly et al. (US 2021/0408246 A1) shows a similar method of forming a similar device as the applicant.
Chiu et al. (US 2022/0344464 A1) shows a similar method of forming a similar device as the applicant.
Xie et al. (US 2024/0186374 A1) shows a similar method of forming a similar device as the applicant.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PINAKI DAS whose telephone number is (703)756-5641. The examiner can normally be reached M-F 8-5 EST.
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/P.D./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898