DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-3, 6-7, 9-17 and 19-20 are pending in this application. Claims 4-5, 8 and 18 were withdrawn.
Drawings
Prior objection to drawing is withdrawn in view of amendments to claim 3.
Specification
Prior objection to specification is withdrawn in view of amendments to the specification.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US 2022/0037193 A1, newly cited).
Re Claim 1, Yu teaches a method of forming a semiconductor device, comprising:
receiving a workpiece (Fig. 2) having an active region (64, Fig. 2, para [0018]) extending from a substrate (50, Fig. 2, para [0018]), the active region is surrounded by an isolation structure (68, Fig. 4, para [0011]), and portions of the active region (64) protrude above a top surface of the isolation structure (top surface of 68, see Fig. 4);
forming a gate stack (100+102, Fig. 17A, para [0012]) over a channel region (54, Fig. 17A, paras [0021] and [0055] – [0056]) of the active region, the channel region having one or more channel layers (see Fig. 17A);
forming a first source/drain (S/D) trench (87, Fig. 9C, para [0039]) adjacent the channel region (channels 54) and extending into the substrate (50) below the top surface of the isolation structure (68, see Fig. 9B);
forming a first epitaxial S/D feature (92, Fig. 12C, para [0044]) in the first S/D trench (trench 87);
forming a first frontside metal contact (112, Fig. 20C, para [0065]) over the first epitaxial S/D feature (S/D 92);
forming a first backside trench (128, Fig. 25C, para [0082]) that exposes a bottom surface of the first epitaxial S/D feature (para [0082]); and
forming a first backside conductive feature (backside vias 130, Fig. 26C, para [0084]) in the first backside trench (128, Fig. 25C) and on the exposed bottom surface of the first epitaxial S/D feature (Fig. 26C), wherein a topmost surface of the first backside conductive feature is under a bottommost surface of the gate stack (topmost surface of 130 is under a bottommost surface of gate stack 100+102, Fig. 26C) by a vertical spacing (see Fig. 26C)
Yu does not explicitly state that the vertical spacing (see Fig. 26C) between the topmost surface of backside via 130 and the bottommost surface of the gate stack (100+102) is at least equal to a thickness of one of the one or more channel layers in the channel region (thickness of channels 54). However, referring to Fig. 26C, it would be obvious to one of ordinary skill in the art that the vertical spacing is nearly equal to the vertical thickness of the channels 54, satisfying the claim limitation. Additionally, it would also have been obvious to one of ordinary skill in the art, at the time of invention, to optimize the vertical spacing depending on the design needs of the transistor device and arrive at the claimed range. With respect to the limitations of the claim, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955). The optimization of the claimed the vertical spacing would have been obvious to one of ordinary skill in the art.
Re Claim 2, Yu teaches the method of claim 1, further comprising:
forming a second S/D trench (2nd trench 87, Fig. 9B, para [0039]) adjacent the channel region (channels 54) and extending into the substrate (50) below the top surface of the isolation structure (68, see Fig. 9B);
forming a second epitaxial S/D feature (2nd S/D 92, Fig. 12B, para [0044]) in the second S/D trench (2nd trench 87); and
forming a second frontside metal contact (2nd 112, Fig. 20B, para [0065]) over the second epitaxial S/D feature (2nd S/D 92).
Re Claim 15, Yu teaches a method of forming a semiconductor device, comprising:
forming an active region (64, Fig. 2, para [0018]) protruding from a substrate (50, Fig. 2, para [0018]) and disposed between portions of an isolation structure (68, Fig. 4, para [0011]);
forming a gate stack (100+102, Fig. 17A, para [0012]) disposed on a channel region (54, Fig. 17A, paras [0021] and [0055] – [0056]) of the active region;
forming inner spacers (90, Fig. 11C, para [0041]) between channel layers in the channel region (54, Fig. 11C):
forming a source/drain (S/D) feature (92, Fig. 12C, para [0044]) over a source/drain region of the active region, wherein the S/D feature has an entrenched portion that extends below a top surface of the substrate (top surface of substrate 50, see Fig. 12C);
forming a backside silicide layer (129, Fig. 26C, para [0082]) on a bottom surface of the S/D feature (92, Fig. 26C); and
forming a backside via (backside vias 130, Fig. 26C, para [0084]) on a bottom surface of the backside silicide layer (129), wherein a topmost surface of the backside via is below a bottommost portion of the gate stack (100+102, see Fig. 26C) by a vertical spacing (see Fig. 26C).
Yu does not explicitly state that the vertical spacing (see Fig. 26C) between the topmost surface of backside via 130 and the bottommost surface of the gate stack (100+102) is greater than a thickness of the inner spacers (90, Fig. 26C) and less than 3 times the thickness of the inner spacers. However, referring to Fig. 26C, it would be obvious to one of ordinary skill in the art that the vertical spacing is nearly equal to the vertical thickness of the inner spacers 90. Additionally, it would also have been obvious to one of ordinary skill in the art, at the time of invention, to optimize the vertical spacing depending on the design needs of the transistor device and arrive at the claimed range. With respect to the limitations of the claim, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955). The optimization of the claimed the vertical spacing would have been obvious to one of ordinary skill in the art.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US 2022/0037193 A1, newly cited), and further in view of Wei et al. (US 2022/0139911 A1, of record).
Re Claim 3, Yu teaches the method of claim 2, but does not disclose the following:
forming a dielectric cap on a bottom surface of the second trench, wherein the second epitaxial S/D feature is formed over the dielectric cap,
wherein the dielectric cap is vertically spaced away from the bottommost surface of the gate stack by a bottom portion of the second epitaxial S/D feature.
However, Yu discloses a sacrificial first epitaxial layer 91 (Fig. 12C, para [0044]) which has different etch selectivity compared to the S/D feature 92, and will help during the etching process while making the backside contact.
Related art Wei teaches an alternate material for the future etching step, where dielectric caps (364, Fig. 3H, para [0081]) are being formed before the formation of S/D features. Wei discloses that the dielectric caps provide sufficient “etch selectivity” (similar to the function performed by sacrificial first epitaxial layer of Yu), especially during the formation of backside trench, where etchants can selectively etch one material over the other, and thus define the boundaries of S/D regions more accurately (para [0059]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to substitute the first epitaxial layer of Yu with the dielectric cap as taught by Wei, as it will provide the same functionality of “etch selectivity” during the formation of backside trench, where etchants can selectively etch one material over the other, and thus define the boundaries of S/D regions more accurately (para [0059], Wei). The substitution of a known material for its known purpose to yield predictable results is prima facie obvious. Also see KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Thus, Yu modified by Wei teaches,
forming a dielectric cap (364, Fig. 3H, para [0081], Wei) on a bottom surface of the second trench (2nd trench 87, Fig. 9B, Yu), wherein the second epitaxial S/D feature (2nd S/D 92) is formed over the dielectric cap,
wherein the dielectric cap (364, Fig. 3H, Wei) is vertically spaced away from the bottommost surface of the gate stack (100+102, Fig. 17C, Yu) by a bottom portion of the second epitaxial S/D feature (see Fig. 19C, Examiner notes that the cap 364 will be formed below the layer 92, instead of the epitaxial layer 91 in Fig. 17C of Yu, and thus the cap will be vertically spaced from the gate stack by a lower portion of the S/D feature 92).
Claims 9 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US 2022/0037193 A1, newly cited), and further in view of Wang et al. (US 2021/0343639 A1, newly cited).
Re Claim 9, Yu teaches the method of claim 1, but does not disclose forming of the first backside conductive feature (backside vias 130, Fig. 26C, para [0084]) further includes forming a dielectric barrier layer along sidewalls of the first backside trench.
Related art Wang teaches a formation of backside dielectric via spacer (290, Fig. 23B, para [0088]) along the sidewalls of the opening (“O5”, Fig. 23B, para [0088]), which will protect the via during future manufacturing processes (para [0088]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to form a dielectric spacer layer along the sidewalls of the backside trench of the device of Yu, as taught by Wang, as that will protect the opening during future manufacturing processes (para [0088], Wang).
Re Claim 19, Yu teaches the method of claim 15, but does not disclose forming a silicon nitride barrier layer on sidewalls of the backside via.
Related art Wang teaches a formation of backside dielectric via spacer (290, Fig. 23B, para [0088]) along the sidewalls of the opening (“O5”, Fig. 23B, para [0088]), which will protect the via during future manufacturing processes (para [0088]). The dielectric via spacer (290, Fig. 23B) can be made of silicon nitride (para [0088]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to form a silicon nitride dielectric spacer layer along the sidewalls of the backside trench of the device of Yu, as taught by Wang, as that will protect the opening during future manufacturing processes (para [0088], Wang).
Rejection 2
Claims 15, 17 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Wei et al. (US 2022/0139911 A1, of record), and further in view of Yu et al. (US 2022/0037193 A1, newly cited).
Re Claim 15, Wei teaches a method of forming a semiconductor device, comprising:
forming an active region (357, Fig. 3C, para [0063]) protruding from a substrate (350, Fig. 3C, para [0063]);
forming a gate stack (371, Fig. 3K, para [0095]) disposed on a channel region (375, Fig. 3K, para [0095]) of the active region;
forming inner spacers (362, Fig. 3F, para [0079]) between channel layers in the channel region (see Fig. 3F);
forming a source/drain (S/D) feature (left 366 S/D, Fig. 3I, para [0089]) over a source/drain region of the active region, wherein the S/D feature has an entrenched portion that extends below a top surface of the substrate (left 366 S/D extends below the top surface of 350, see Fig. 3I);
forming a backside via (378, Fig. 3P, para [0108]), wherein a topmost surface of the backside via is below a bottommost portion of the gate stack (top surface of 378 is below the bottommost portion of the gate stack 371, see Fig. 3P).
Wei only shows details of one active semiconductor fin and hence does not disclose an isolation structure disposed between multiple fins.
However, related art Yu discloses that one can form multiple active fins (64, Fig. 4, para [0018]) on the substrate (50, Fig. 4, para [0018]), which are isolated by shallow trench isolation (STI) structures (68, Fig. 4, para [0011]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to form multiple active fins which are isolated by STI structures in the device of Wei, as taught by Yu. Thus, one can form multiple transistors on the same substrate, thus improving efficiency and reducing cost. Moreover, the STI structures isolate each of the transistors, thus eliminating any cross-talk between each transistor region.
Wei also does not disclose formation of silicide layer between the S/D feature and the backside via.
Related art Yu teaches a formation of silicide layer (129, Fig. 26C, para [0082]) between the S/D region (92, Fig. 26C, para [0084]) and the backside via (130, Fig. 26C, para [0084]). The silicidation layer is useful for better contact resistance and increasing thermal stability, resulting in better device performance. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to form silicide layer between the S/D region and the backside via of Wei, as taught by Yu, because the silicidation layer provides better contact resistance and increasing thermal stability, resulting in better device.
Furthermore, Wei does not explicitly state that the vertical spacing between the topmost surface of backside via (378, Fig. 3P) and the bottommost surface of the gate stack (371) is greater than a thickness of the inner spacers (262, Fig. 3P) and less than 3 times the thickness of the inner spacers. However, in Fig. 3P, Wei shows, that the vertical spacing is about one-half the thickness of the inner spacers 262. Related art, Yu discloses a similar structure where the vertical spacing between the topmost surface of backside via (130, Fig. 26C, Yu) and the bottommost surface of the gate stack (100+102, Fig. 26C, Yu) is nearly equal to the vertical thickness of the inner spacers (90, Fig. 26C), within the claimed range. Examiner notes that the vertical spacing is a design choice and one of ordinary skill in the art, at the time of invention, would optimize the vertical spacing depending on the design needs of the transistor device and arrive at the claimed range. With respect to the limitations of the claim, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955). The optimization of the claimed the vertical spacing would have been obvious to one of ordinary skill in the art.
Re Claim 17, Wei modified by Yu teaches The method of claim 15, wherein a width of the backside via (width of via 378, marked “w1” in annotated Fig. 3P below, Wei) along a lengthwise direction of the active region (see Fig. 3P, Wei) is smaller than a width of the S/D feature (width of left 366 S/D, marked “w2” in annotated Fig. 3P below, Wei).
PNG
media_image1.png
377
714
media_image1.png
Greyscale
Re Claim 20, Wei modified by Yu teaches the method of claim 15, wherein the S/D feature is a first S/D feature (left 366 S/D, Fig. 3P, para [0089], Wei), and the method further comprises:
forming a second S/D feature (right 366 S/D, Fig. 3P, para [0089], Wei) over a second source/drain region of the active region; and
forming a backside dielectric cap (right 364, Fig. 3P, para [0081], Wei) on a bottom surface of the second S/D feature (right 366 S/D, Fig. 3P), wherein the bottom surface of the of the first S/D feature is below the bottom surface of the second S/D feature (bottom surface of left 366 S/D is below the bottom surface of right 366 S/D, see Fig. 3P, Wei).
Allowable Subject Matter
Claims 11-14 are allowed.
Claims 6-7, 10 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 11 is allowable for the following reasons. Most of the limitations of claim 11 are taught by Yuh et al. (US 2023/0067715 A1, of record), and further in view of Huang et al. (US 2022/0045052 A1, of record), as stated in the office action dated 2/4/2026. However, Yuh modified by Huang, fails to teach the newly added limitation, wherein, “after forming the backside S/D trench, lower sidewall portions of the S/D features remain over sidewalls of the penetrated substrate”. This limitation is neither anticipated nor made obvious by the prior art of record in the Examiner’s opinion, when viewed in the context of the whole claim. Claims 12-14 depend from claim 11 and are allowable for at least the reasons above.
Claim 6 is allowable at least for the reasons of, “before the forming of the first epitaxial S/D feature, forming a dielectric feature on a bottom surface of the first S/D trench, wherein the forming of the dielectric feature includes: conformally depositing a dielectric layer into the first S/D trench, performing a plasma treatment on a top surface of the dielectric layer, and selectively etching away the dielectric layer on sidewalls of the first S/D trench”. Yu does not disclose formation of a dielectric layer on the bottom surface of the S/D trenches. Related art, Wei et al. (US 2022/0139911 A1, of record) teaches formation of dielectric caps (364, Fig. 3H, para [0081]) on the bottom surface of the S/D trench, which includes conformally depositing a dielectric liner (364, Fig. 3G and selectively etching away the dielectric layer on sidewalls of the first S/D trench (364, Fig. 3H, para [0081]). However, Wei does not disclose “performing a plasma treatment on a top surface of the dielectric layer”. The prior art of record taken either single or in combination fails to teach or reasonably suggest the above limitation when taken in context of the entire claim 6 and in view of the independent claim 1, as a whole.
Claim 7 depends from claim 6 and is allowable at least for the reasons above.
Claim 10 is allowable at least for the reasons of, “wherein the first epitaxial S/D feature has a lightly doped outer layer and a heavily doped inner layer, and the first backside conductive feature is in direct contact with the heavily doped inner layer of the first epitaxial S/D feature”. Yu discloses that the S/D feature 92 can include multiple layers, like the lightly doped 92A layer and the heavily doped 92B layer (Fig. 12C, para [0050]), but does not teach that the backside contact (130, Fig. 26C, para [0084]) is in direct contact with the heavily doped inner layer. Related art, Yuh et al. (US 2023/0067715 A1, of record) teaches a S/D feature (S/D 180+190, Fig. 7) that has a lightly doped outer layer (180, para [0062]) and a heavily doped inner layer (190), and the first backside conductive feature (360+340+350, Fig. 18) is in direct contact with the heavily doped inner layer (190) of the first epitaxial S/D feature (S/D 180+190, Figs. 7 and 18). However, it would not have been obvious to a person of ordinary skill in the art to combine the above teachings to reach the combined limitation recited in claim 10, when viewed in context of the independent claim 1, as a whole.
Claim 16 is allowable at least for the reasons of, “wherein the S/D feature has a lightly doped outer layer and a heavily doped inner layer, and the backside via is in electrical contact with the heavily doped inner layer by directly contacting the backside silicide layer.” Yu discloses that the S/D feature 92 can include multiple layers, like the lightly doped 92A layer and the heavily doped 92B layer (Fig. 12C, para [0050]), but does not teach that the backside contact (130, Fig. 26C, para [0084]) is in direct contact with the heavily doped inner layer. Related art, Yuh et al. (US 2023/0067715 A1, of record) teaches a S/D feature (S/D 180+190, Fig. 7) that has a lightly doped outer layer (180, para [0062]) and a heavily doped inner layer (190), and the first backside conductive feature (360+340+350, Fig. 18) is in direct contact with the heavily doped inner layer (190) of the first epitaxial S/D feature (S/D 180+190, Figs. 7 and 18). However, it would not have been obvious to a person of ordinary skill in the art to combine the above teachings to reach the combined limitation recited in claim 16, when viewed in context of the independent claim 15, as a whole.
Response to Arguments
Applicant’s arguments with respect to claims 1 and 15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PINAKI DAS whose telephone number is (703)756-5641. The examiner can normally be reached M-F 8-5 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JULIO MALDONADO can be reached at (571)272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/P.D./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
Prosecution Insights