DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 10-20 are cancelled in the Response filed 10/08/2025. Thus, the restriction is rescinded, as current claims 1-9 are directed to only the device.
Claim Objections
Claim 1 is objected to because of the following informalities:
Claim 1 recites “A semiconductor structure comprising: a semiconductor structure, comprising:…” Examiner has interpreted this as an accidental typo, and the claim will be interpreted such that there is only one semiconductor structure. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US 20200203354 A1, hereinafter Lee)
With regards to claim 1, Lee discloses a semiconductor structure comprising:
a plurality of bitline structures (bit line BLS) on a substrate; (substrate 100)
a spacer structure (spacer structure SS) on side walls of each of the plurality of bitline structures, wherein the spacer structure comprises an inner sub-spacer, (spacer 131) an outer sub-spacer, (spacer 134) and an air gap (air gap 136) between the inner sub-spacer and the outer sub-spacer; (See FIG. 1b)
a plurality of conductive structures ((contact 153 and landing pads LPa/LPb) on the substrate, wherein each of the plurality of conductive structures is separated from the other by the plurality of bitline structures; (see FIG. 1b) and
a dielectric layer (dielectric 170/171) between the plurality of bitline structures and the plurality of conductive structures,
wherein a first portion (dielectric 171 and portion of dielectric 170 above 171) of the dielectric layer that is in direct contact with the plurality of bitline structures has a first maximum height, a second portion (dielectric 170 directly contacting LPb) of the dielectric layer that is in direct contact with the plurality of conductive structures has a second maximum height, and the first maximum height is larger than the second maximum height. (see Annotated FIG. 1b, where the portion of the dielectric 170/171 having a first height is greater than the second height of portion of dielectric 170, see also Response to Arguments)
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With regards to claim 2, Lee discloses the semiconductor structure of claim 1, wherein the dielectric layer is in direct contact with the air gap of the spacer structure. (See FIG. 1b, showing the direct contact)
With regards to claim 3, Lee discloses the semiconductor structure of claim 1, wherein an upper surface of the air gap of the spacer structure is lower than upper surfaces of the plurality of bitline structures. (See FIG. 1b, showing the air spacer 136 lower than the top of the bit line BLS)
With regards to claim 4, Lee discloses the semiconductor structure of claim 1, wherein the plurality of conductive structures is in direct contact with active regions (regions 1b/1a of active region ACT) of the substrate. (See FIG. 1b)
With regards to claim 5, Lee discloses the semiconductor structure of claim 1, wherein a portion of the spacer structure that is directly below the first portion of the dielectric layer has a first upper surface, (upper surface of spacer 136)
a portion of each of the plurality of conductive structures that is directly below the second portion of the dielectric layer has a second upper surface, (upper surface of landing pad LPa) and
the first upper surface is lower than the second upper surface. (See FIG. 1b)
With regards to claim 6, Lee discloses the semiconductor structure of claim 1, wherein the inner sub-spacer of the spacer structure comprises silicon nitride, and the outer sub-spacer of the spacer structure comprises silicon nitride. (Paragraphs [0056] and [0058]: “…the formation of the first spacer 131 may include depositing a spacer layer filling the depressions 111…The spacer layer may include a first nitride layer, an oxide layer, and a second nitride layer…The second spacer 134 may be formed of, for example, a silicon nitride layer and/or a silicon oxynitride layer…” Thus both 131 and 134 can be made of SiN)
With regards to claim 7, Lee discloses the semiconductor structure of claim 1, wherein the dielectric layer comprises silicon nitride. (Paragraph [0033]: “The second interlayer dielectric layer 170 may include, for example, a silicon nitride layer.”)
With regards to claim 8, Lee discloses the semiconductor structure of claim 1, wherein each of the plurality of conductive structures comprises a metal layer, a metal silicide layer, and a polysilicon layer from top to bottom.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 20200203354 A1, hereinafter Lee), as applied to claim 1, and further in view of YOON et al. (US 20220181457 A1, hereinafter Yoon)
With regards to claim 9, Lee discloses the semiconductor structure of claim 1, wherein each of the plurality of bitline structures comprises a dielectric layer, (cap 125) a metal layer, (metal 123) …and a polysilicon layer (polysilicon 121) from top to bottom.
However, while Lee teaches a metal silicide (metal silicide 122) between the metal 123 and the polysilicon 121, Lee does not explicitly teach a metal nitride.
Yoon teaches that metal silicides can be substituted for metal nitrides in conductive layers. (Paragraph [0172]: “In some example embodiments, the plurality of first conductive lines 220 may include doped polysilicon, a metal, conductive metal nitride, conductive metal silicide, conductive metal oxide…”)
It would have been obvious to one of ordinary skill in the art to modify the device of Lee to have the metal nitride of Yoon, as both references are in the same field of endeavor.
One of ordinary skill would appreciate that using a metal nitride is substituting one known element for another to achieve a predictable result, namely conduction.
Response to Arguments
Applicant's arguments filed 01/26/2026 have been fully considered but they are not persuasive.
Applicant suggests that the bit line is entirely covered from the dielectric 170/171 by the spacer 131. However, Examiner notes that both the current Specification and Lee et al. recite the bit line structure (BS/BLS) includes the capping pattern (106/125, See FIG. 1 of the current Specification and FIG. 1B of Lee). Therefore, Lee discloses that there is a portion of 170 which directly contacts the capping pattern 125 of the bit line structure BLS, which meets the limitations of claim 1. While Applicant appears to understand this interpretation in “2.” of the Response to Arguments of 01/26/2026, an amended FIG. 1B has been provided which further illustrates the portion of 170/171 being the first portion having a first maximum height directly contacting the bit line structure BLS and the portion of dielectric 171 being the second portion having a second maximum height.
Examiner further notes that the claim does not require the first maximum height be in direct contact with the bit line. The claim instead suggests that the first portion is in direct contact with the bit line structure, and that the first portion has a maximum height. There is no limitation that requires “the first maximum height is in direct contact with the bit line,” as Applicant suggests. Thus, Lee discloses at least this limitation of claim 1.
With regards to the “reduces parasitic capacitance” portion of the Arguments, Examiner recommends more closely amending the claims to recite physical features of the device that would overcome the rejection, as benefits of the device are not read into the claims from the Specification in US practice.
Therefore, claim 1 is properly rejected, and claims 2-9 are rejected for at least their dependencies.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. CHUNG et al. (US 20200168614 A1) – different shaped spacer 191/192 on bit line 12.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN M Page whose telephone number is (571)272-3249. The examiner can normally be reached M-F: 10:00AM-6:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8548. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STEVEN M PAGE/Primary Patent Examiner, Art Unit 2812