DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. This Non-Final office action is in response to application 18/305,382, application filed on 04/24/2023. Claims 1-15 are currently pending in this application.
Information Disclosure Statement
3. The information disclosure statement (IDS) submitted on 04/24/2023, 07/31/2023 and 12/11/2023, respectively, is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
4. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
5. Claim(s) 1-15 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Murali et al. (US PG Pub No. 2009/0313592).
6. With respect to independent claim 1, Murali teaches:
A method for guiding physical generation of a NoC from a synthesized representation (high-level application modeling to physical layout level implementation, para 5; establishing physical connectivity between elements of a NoC, Abstract; modeling area, power, timing of the network components of switches and links for topology synthesis process, para 30; topology design to back-end physical design phase, para 40), the method comprising:
receiving, at a tool, at least one constraint parameter for the NoC (using tool to optimize parameters from designer such as NoC power consumption, area, timing, para 27, 66-67; parameters of the target design space, para 38; performance constraints, para 41; parameters like power consumption, area and delay of network components, para 42), the at least one constraint parameter is selected from a group of constraint parameters including at least one physical constraint and at least one performance constraint (performance constraint – power, delay, physical constraint, area, para 42-45; selecting one or more metrics from power consumption, area, length of wires, para 12);
augmenting, using the tool, a physical floorplan for the NoC with information, which meets performance criteria supplied, that guides a physical implementation of the NoC (augmenting/improving parameters such as power consumption, area, timing, para 65-68; changing physical size of NoC components, increasing can result in increase in critical path, para 42-45; information about constraints/parameters used in NoC floorplanning process to compute metrics, see Murali, claim 14; applying parameters to the NoC, para 48; updating NoC by using pipeline components for wires that violate physical and performance constraints, see Murali, claim 18); and
constraining, using the physical floorplan, the physical implementation of a connection to a location on the physical floorplan based on the at least one constraint parameter (constraining design by establishing connectivity between two pairs of communicating elements by using switches, pipelines, Abstract; constraining from delay caused by using pipeline components and switches, see Murali, claim 18, para 12, 30-35; NoC floor-planning process to compute metrics, see Murali, claim 14).
7. With respect to independent claim 4, Murali teaches:
A method for guiding a physical implementation of a synthesized topology of a NoC (high-level application modeling to physical layout level implementation, para 5; establishing physical connectivity between elements of a NoC, Abstract; modeling area, power, timing of the network components of switches and links for topology synthesis process, para 30; topology design to back-end physical design phase, para 40), the method comprising:
receiving, at a tool, at least one timing requirement for the NoC (using tool to optimize parameters from designer such as NoC power consumption, area, timing, para 27, 66-67; meeting required delay, see Murali, claim 18; failure to meet timing requirements, para 31, 38);
receiving, at the tool, at least one performance constraint for the NoC (using tool to optimize parameters from designer such as NoC power consumption, area, timing, para 27, 66-67; parameters of the target design space, para 38; performance constraints, para 41; parameters like power consumption, area and delay of network components, para 42);
augmenting, using the tool, a physical floorplan for the NoC with information, which meets performance criteria, to guide the physical implementation (augmenting/improving parameters such as power consumption, area, timing, para 65-68; changing physical size of NoC components, increasing can result in increase in critical path, para 42-45; information about constraints/parameters used in NoC floorplanning process to compute metrics, see Murali, claim 14; applying parameters to the NoC, para 48; updating NoC by using pipeline components for wires that violate physical and performance constraints, see Murali, claim 18; satisfying constraints on the NoC, para 38);
implementing a timing estimation configured to determine if a length between a first component and a second component placed on the physical floorplan exceeds the at least one timing requirement (see timing estimation, para 29; for wires that are too long in the floorplan and thus do not meet constraint requirements and cannot support required speed and timing, see Murali, claim 18); and
inserting, in response to exceeding the at least one timing requirement, at least one link in the physical floorplan (for the wires that are long, use pipeline logic and consider delay from pipeline wire crossings, see Murali, claim 18; see adding additional connections when established connections do not satisfy requirements, see Murali, claim 12).
8. With respect to claim 2, Murali teaches:
The method of claim 1, wherein a gate of the connection is oriented, using the tool, at a shortest routing distance from the connection compared to a listing of routing distances between the gate and the connection detected by the tool (see shortest path algorithm for orienting component paths, size of switches and chosen paths, para 58; pipeline logical components, see Murali, claim 18).
9. With respect to claim 3, Murali teaches:
The method of claim 1 further comprising dividing, using the tool, a logical interconnect into a plurality of portions, whereby, the plurality of portions of the logical interconnect are calibrated to a size of the tool (segmenting wires into multiple smaller wires using pipeline logical components, see Murali, claim 18).
10. With respect to claim 5, Murali teaches:
The method of claim 4, wherein the at least one link is inserted using a wire delay technology-specific parameter (see delay associated with inserting pipeline logic components as described in Murali claim 18).
11. With respect to claim 6, Murali teaches:
The method of claim 4 further comprising creating, at the tool, at least one module region, wherein the at least one link of the NoC is assigned to the at least one module region (see link/pipeline inserted into region where wires are long, see Murali, claim 18).
12. With respect to claim 7, Murali teaches:
The method of claim 4 further comprising receiving an area-estimation for the first component and the second component (estimates of wire length of the NoC wires are obtained, para 31; accurate estimate of the design area, para 38).
13. With respect to claim 8, Murali teaches:
The method of claim 7 further comprising performing a balance to the at least one timing requirement in an optimization of the NoC to identify that at least one gate of the NoC can be placeable into at least a portion of the physical floorplan (for the wires that are long, use pipeline logic and consider delay/timing from pipeline wire crossings, see Murali, claim 18; see adding additional connections when established connections do not satisfy timing requirements, see Murali, claim 12; see link/pipeline logic/gate inserted into region where wires are long, see Murali, claim 18).
14. With respect to claim 9, Murali teaches:
The method of claim 7 further comprising performing a balance to the at least one performance constraint in an optimization of the NoC to identify that at least one gate of the NoC can be placeable into at least a portion of the physical floorplan (for the wires that are long, use pipeline logic and consider delay/timing from pipeline wire crossings, see Murali, claim 18; see adding additional connections when established connections do not satisfy timing requirements, see Murali, claim 12; see link/pipeline logic/gate inserted into region where wires are long, see Murali, claim 18).
15. With respect to claim 10, Murali teaches:
The method of claim 4 further comprising receiving a power requirement for the NoC (see constraints on power consumption, para 27).
16. With respect to claim 11, Murali teaches:
The method of claim 10 further comprising performing a balance to the at least one timing requirement in an optimization of the NoC to identify that the NoC will not exceed the power requirement specified in the at least one timing requirement (minimizing power consumption, para 27-30; relationships to leverage models for area, power and timing, para 30).
17. With respect to claim 12, Murali teaches:
The method of claim 10 further comprising performing a balance to the at least one performance constraint in an optimization of the NoC to identify that the NoC will not exceed the power requirement specified in the at least one performance constraint (minimizing power consumption, para 27-30; relationships to leverage models for area, power and timing, para 30).
18. With respect to claim 13, Murali teaches:
The method of claim 4 further providing physical routing congestion data (cost of routing flow, crowded routing, para 59; increasing size of NoC components and increasing critical area constraint values, para 43).
19. With respect to claim 14, Murali teaches:
The method of claim 13 further comprising performing a balance to the at least one timing requirement in an optimization of the NoC to identify that the NoC can be routable into at least a portion of the physical floorplan (cost of routing flow, crowded routing, para 59; increasing size of NoC components and increasing critical area constraint values, para 43).
20. With respect to claim 15, Murali teaches:
The method of claim 13 further comprising performing a balance to the at least one performance constraint in an optimization of the NoC to identify that at least one gate of the NoC can be routable into at least a portion of the physical floorplan (cost of routing flow, crowded routing, para 59; increasing size of NoC components and increasing critical area constraint values, para 43).
Conclusion
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/SUCHIN PARIHAR/
Primary Examiner, Art Unit 2851