DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 6-11, 13, 17, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Zhong et al (US Publication 20200176431) in view of Cheah et al (US Publication 20200128673).
Regarding claim 1, Zhong teaches a semiconductor structure, comprising:
a first substrate including a first surface and a second surface opposite the first surface (Fig. 1, 102);
a die disposed over the second surface of the first substrate (Fig. 1, 110);
a plurality of first conductive bumps disposed between the first substrate and the die (Fig. 1, 112);
a second substrate disposed below the first surface of the first substrate (Fig. 1, 150 and 130);
a plurality of second conductive bumps disposed between the first substrate and the second substrate (Fig. 1, 132);
an in-package voltage regulator (PVR) chip disposed over the second substrate (Fig. 1, 140, para 23, passive device voltage regulation); and
an integrated passive die (IPD) chip comprising a capacitive device disposed in one or more trenches in a semiconductor substrate of the IPD chip, the semiconductor substrate of the IPD chip being arranged between the first substrate and the second substrate (Fig. 1, 140 one of the other multiple 140s, para 23, IPD capacitor array).
Zhong does not specifically teach wherein a plane extends in parallel with an upper or lower surface of the PVR chip and traverses a sidewall of the PVR chip and also traverses a sidewall of the first substrate.
Cheah teaches wherein a plane extends in parallel with an upper or lower surface of the PVR chip and traverses a sidewall of the PVR chip and also traverses a sidewall of the first substrate (Fig. 5, plane parallel to upper surface of 516 traverses sidewall of 516 and 20).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Zhong to include the PVR chip as taught by Cheah in order to improve the manufacturing operations and reliability of the device.
Regarding claim 2, Zhong as modified teaches the limitations of claim 1 upon which claim 2 depends.
Zhong teaches wherein the PVR chip is arranged laterally adjacent to the first substrate (Fig. 1, 140 attached to 102 laterally adjacent to 110), and is connected to the second substrate through some of the plurality of second conductive bumps (Fig. 1, 142, para 26, 140 may also be mounted using solder bumps 142).
Regarding claim 3, Zhong as modified teaches the limitations of claim 2 upon which claim 3 depends.
Zhong teaches wherein the IPD chip is laterally surrounded by the plurality of second conductive bumps (Fig. 1, 140 laterally surrounded by 132).
Regarding claim 6, Zhong as modified teaches the limitations of claim 1 upon which claim 6 depends.
Zhong teaches wherein the PVR chip is arranged between the first substrate and the second substrate, and is laterally surrounded by the plurality of second conductive bumps (Fig. 1, 140 between 130 and 102 surrounded by 132).
Regarding claim 7, Zhong as modified teaches the limitations of claim 1 upon which claim 7 depends.
Zhong teaches further comprising: a plurality of third conductive bumps disposed below the second substrate (Fig. 1, 134).
Regarding claim 8, Zhong as modified teaches the limitations of claim 7 upon which claim 8 depends.
Zhong teaches wherein the PVR chip is arranged under the second substrate, and is laterally surrounded by the plurality of third conductive bumps (Fig. 1, 140 under 130 and surrounded by 134).
Regarding claim 9, Zhong as modified teaches the limitations of claim 1 upon which claim 9 depends.
Zhong teaches wherein the PVR chip is arranged over the first substrate (Fig. 1, 140 over 102).
Regarding claim 10, Zhong as modified teaches the limitations of claim 1 upon which claim 10 depends.
Zhong teaches wherein the IPD chip is laterally surrounded by the plurality of second conductive bumps (Fig. 1, 140 surrounded by 132 and 122).
Regarding claim 11, Zhong as modified teaches the limitations of claim 10 upon which claim 11 depends.
Zhong teaches wherein the die includes a processor (para 18, logic die 110), the PVR chip provides power to the processor through the first conductive bumps, the first substrate, and the second conductive bumps (Fig. 1, 140, para 23), and wherein the IPD chip is placed directly beneath the processor (Fig. 1, 140 directly beneath 110).
Regarding claim 13, Zhong as modified teaches the limitations of claim 1 upon which claim 13 depends.
Zhong teaches wherein the first substrate is a first interposer substrate devoid of active semiconductor devices (para 22, substrate 102); and wherein the second substrate is a second interposer substrate devoid of active semiconductor devices (para 23, substrate 130).
Regarding claim 17, Zhong teaches a semiconductor structure, comprising:
a first substrate including a first surface and a second surface opposite the first surface (Fig. 1, 102);
a die disposed over the second surface of the first substrate (Fig. 1, 110);
a plurality of first conductive bumps disposed between the first substrate and the die (Fig. 1, 112);
a second substrate disposed below the first surface of the first substrate (Fig. 1, 130 and 150);
a voltage regulator chip disposed over the second substrate (Fig. 1, 104 disposed over 130); and
a plurality of second conductive bumps disposed between the first substrate and the second substrate (Fig. 1, 132).
Zhong does not specifically teach wherein a plane extends in parallel with an upper or lower surface of the voltage regulator chip, traverses a sidewall of the voltage regulator chip, and also traverses a sidewall of the first substrate.
Cheah teaches wherein a plane extends in parallel with an upper or lower surface of the voltage regulator chip, traverses a sidewall of the voltage regulator chip, and also traverses a sidewall of the first substrate (Fig. 5, plane parallel to upper surface of 516 traverses sidewall of 516 and 20).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Zhong to include the PVR chip as taught by Cheah in order to improve the manufacturing operations and reliability of the device.
Regarding claim 18, Zhong teaches the limitations of claim 17 upon which claim 18 depends.
Zhong teaches further comprising: an integrated passive device (IPD) die comprising a capacitive device disposed in one or more trenches in a semiconductor substrate of the IPD die (Fig. 1, 140, para 23, IPD capacitor array), the semiconductor substrate of the IPD die being arranged between the first substrate and the second substrate and being laterally surrounded by the plurality of second conductive bumps (Fig. 1, 140 between 102 and 130 surrounded by 132 and 122).
Claims 4, 12, 14-16, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Zhong et al (US Publication 20200176431) in view of Cheah et al (US Publication 20200128673) and further in view of Meyers et al (US Publication 20170092602).
Regarding claim 4, Zhong as modified teaches the limitations of claim 1 upon which claim 4 depends.
Zhong does not specifically teach a molding material disposed over the first substrate and surrounding the die, the plurality of first conductive bumps, the plurality of second conductive bumps, and the PVR chip; wherein the molding material directly contacts sidewalls of the PVR chip and is disposed between and contacts nearest neighboring sidewalls of the PVR chip and the first substrate.
Meyers teaches a molding material disposed over the first substrate and surrounding the die, the plurality of first conductive bumps, the plurality of second conductive bumps, and the PVR chip (Fig. 3C, 365, para 19); wherein the molding material directly contacts sidewalls of the PVR chip and is disposed between and contacts nearest neighboring sidewalls of the PVR chip and the first substrate (Fig. 3C, 365 contacts sidewalls of 318 (para 29, voltage regulator) and contacts first substrate 330c).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Zhang as modified to include a molding material as taught by Meyers in order to yield a more robust and environmentally protected device.
Regarding claim 12, Zhang as modified teaches the limitations of claim 1 upon which claim 12 depends.
Zhang teaches wherein the first substrate is an interposer substrate devoid of active semiconductor devices (Fig. 1, 102, para 22, coreless module substrate).
Zhang does not specifically teach and wherein the interposer substrate includes a decoupling capacitor structure disposed in a series of trenches in a surface of the interposer substrate.
Meyers teaches and wherein the interposer substrate includes a decoupling capacitor structure disposed in a series of trenches in a surface of the interposer substrate (Fig. 7, para 52, decoupling capacitors).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Zhang as modified to include the decoupling capacitor structure as taught by Meyers in order to improve the reliability and operability of the device.
Regarding claim 14, Zhang as modified teaches a semiconductor structure, comprising:
a first substrate including a first surface and a second surface opposite the first surface (Fig. 1, 102);
a die disposed over the second surface of the first substrate (Fig. 1, 110);
a plurality of first conductive bumps disposed between the first substrate and the die (Fig. 1, 112);
a second substrate disposed below the first surface of the first substrate (Fig. 1, 130 and 150);
a plurality of second conductive bumps disposed between the first substrate and the second substrate (Fig. 1, 132); and
a voltage regulator chip disposed over a semiconductor substrate (Fig. 1, 140over substrate 130 and/or 102), the voltage regulator chip being arranged between the first substrate and the second substrate (Fig. 1, 140 between 130 and 102).
Zhang does not specifically teach a voltage regulator chip including an inductor, and wherein a plane extending in parallel with an upper or lower surface of the voltage regulator chip, traverses a sidewall of the voltage regulator chip, and also traverses a sidewall of the first substrate.
Meyers teaches a voltage regulator chip including an inductor (Fig. 3C, 318, para 29, "including any of various capacitors, inductors, resistors, voltage regulators and/or the like").
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Zhang as modified to include a voltage regulator including an inductor as taught by Meyers in order to control voltage with minimal energy loss and improve thermal efficiency of the device.
Zhang as modified still lacks wherein a plane extends in parallel with an upper or lower surface of the voltage regulator chip, traverses a sidewall of the voltage regulator chip, and also traverses a sidewall of the first substrate.
Cheah teaches wherein a plane extends in parallel with an upper or lower surface of the voltage regulator chip, traverses a sidewall of the voltage regulator chip, and also traverses a sidewall of the first substrate (Fig. 5, plane parallel to upper surface of 516 traverses sidewall of 516 and 20).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Zhong to include the PVR chip as taught by Cheah in order to improve the manufacturing operations and reliability of the device.
Regarding claim 15, Zhong as modified teaches the limitations of claim 14 upon which claim 15 depends.
Zhong does not specifically teach a molding material disposed over the first substrate and surrounding the die, surrounding the plurality of first conductive bumps, surrounding the plurality of second conductive bumps, and surrounding the voltage regulator chip.
Meyers teaches a molding material disposed over the first substrate and surrounding the die, surrounding the plurality of first conductive bumps, surrounding the plurality of second conductive bumps, and surrounding the voltage regulator chip (Fig. 3C, 365, para 19).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Zhang as modified to include a molding material as taught by Meyers in order to yield a more robust and environmentally protected device.
Regarding claim 16, Zhang as modified teaches the limitations of claim 14 upon which claim 16 depends.
Zhang teaches a first underfill material disposed over the first substrate and surrounding the plurality of first conductive bumps (Fig. 1, 118, para 26).
Zhang does not specifically teach a second underfill material disposed over the second substrate and surrounding the plurality of second conductive bumps and the voltage regulator chip. It would be reasonable to assume that the underfill disposed over the first substrate could also be disposed over the second substrate and associated conductive bumps.
Meyers teaches a second underfill material disposed over the second substrate and surrounding the plurality of second conductive bumps and the voltage regulator chip (Fig. 3C, package material 365 over 310 and surrounding 318 and associated conductive connections).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Zhang as modified to include an underfill material disposed on the second substrate and associated conductive bumps as taught by Meyers in order to yield a more robust and mechanically sound device.
Regarding claim 19, Zhang as modified teaches the limitations of claim 17 upon which claim 19 depends.
Zhang teaches wherein the first substrate is an interposer substrate devoid of active semiconductor devices (Fig. 1, 102, para 22, coreless module substrate).
Zhang does not specifically teach wherein the interposer substrate includes a decoupling capacitor structure disposed in a series of trenches in a surface of the interposer substrate.
Meyers teaches wherein the interposer substrate includes a decoupling capacitor structure disposed in a series of trenches in a surface of the interposer substrate (Fig. 7, para 52, decoupling capacitors).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Zhang as modified to include the decoupling capacitor structure as taught by Meyers in order to improve the reliability and operability of the device.
Regarding claim 20, Zhang as modified teaches the limitations of claim 17 upon which claim 20 depends.
Zhang does not specifically teach wherein the voltage regulator chip comprises an inductor, and there is no active circuitry in the voltage regulator chip directly above or directly below the inductor, and there is no active circuitry in the second substrate directly above or directly below the inductor.
Meyers teaches wherein the voltage regulator chip comprises an inductor (Fig. 3C, 318, para 29, "including any of various capacitors, inductors, resistors, voltage regulators and/or the like").
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Zhang as modified to include a voltage regulator including an inductor as taught by Meyers in order to control voltage with minimal energy loss and improve thermal efficiency of the device.
Zhang as modified teaches there is no active circuitry in the voltage regulator chip directly above or directly below the inductor, and there is no active circuitry in the second substrate directly above or directly below the inductor (Fig. 1, 140 on 102 with no active circuity above or below it).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Zhong et al (US Publication 20200176431) in view of Cheah et al (US Publication 20200128673) and further in view of Dang et al (US Publication 20090194864).
Regarding claim 5, Zhong as modified teaches the limitations of claim 2 upon which claim 5 depends.
Zhong does not specifically teach further comprising: a thermal insulating material (TIM) disposed over and contacting an upper surface of the die, and disposed over and contacting an upper surface of the PVR chip.
Dang teaches further comprising: a thermal insulating material (TIM) disposed over and contacting an upper surface of the die, and disposed over and contacting an upper surface of the PVR chip (para 18, TIM in contact with die 106 and cooling cap 124, Fig. 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Zhang as modified to include a TIM disposed over and contacting an upper surface of the die and PVR as taught by Dang in order to improve the thermal response and management of the device.
Response to Arguments
Applicant’s arguments with respect to claims 1, 14, and 17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Noting that it is agreed that the amended language is not taught by the original reference Zhong et al., but as can be seen in the new rejection above, a new reference to Cheah et al (US Publication 20200128673) was found to teach the amended limitation.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS HUTSON whose telephone number is (571)270-1750. The examiner can normally be reached Mon-Fri 8am-5pm.
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/NICHOLAS LELAND HUTSON/ Examiner, Art Unit 2818
/JEFF W NATALINI/ Supervisory Patent Examiner, Art Unit 2818