DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of group I, claims 1-15, in the reply filed on 5/25/2026 is acknowledged. Claims 16-20 have been canceled. Claims 21-25 have been added.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4, 9-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liu (US 2018/0144987 A1).
Regarding claim 1, Liu teaches a method (method in Figs. 1-6 of Liu) for forming a semiconductor device structure (structure in Fig. 6 of Liu), comprising:
forming an expansion film (the unlabeled liner on top surface of substrate 10) over a substrate (10), wherein the substrate has a base portion (bottom portion of the substrate 10), a first fin (first fin to the left group of fins 11 in Fig. 3), and a second fin (second fin in the left group of fins 11) over the base portion;
forming an isolation layer (14) over the expansion film;
annealing (annealing process 15 in [0021] of Liu) the expansion film, the substrate, and the isolation layer, wherein a first average distance (distance between the top portion of the first fin and the top portion of the second fin after the annealing process) between a first upper portion of the first fin and a second upper portion of the second fin after the expansion film, the substrate, and the isolation layer are annealed is greater than a second average distance (distance between the top portion of the first fin and the top portion of the second fin before the annealing process) between the first upper portion of the first fin and the second upper portion of the second fin before the expansion film, the substrate, and the isolation layer are annealed (as described in [0021] of Liu the shrinking of isolation layer 14 in trench 12 is greater than that in the trench 13, thus, the first and second fins are bent in such a way that the top portions are bent away from each other);
partially removing the isolation layer and the expansion film to expose the first upper portion of the first fin and the second upper portion of the second fin (as shown in Fig. 5 of Liu); and
forming a gate stack (17 in Fig. 6 of Liu) wrapping around the first upper portion of the first fin and the second upper portion of the second fin.
Regarding claim 2, Liu teaches all limitations of the method for forming the semiconductor device structure as claimed in claim 1, and also teaches wherein after the expansion film, the substrate, and the isolation layer are annealed, a central axis (central axis of the first fin defined in claim 1) of the first fin rotates in a direction away from the second fin in a cross-sectional view of the substrate (as described in [0021] of Liu the shrinking of isolation layer 14 in trench 12 is greater than that in the trench 13, thus, the first and second fins are bent in such a way that the top portions are rotated away from each other).
Regarding claim 4, Liu teaches all limitations of the method for forming the semiconductor device structure as claimed in claim 1, and also teaches wherein a first central axis of the first upper portion of the first fin is not parallel to a second central axis of the second upper portion of the second fin after the expansion film, the substrate, and the isolation layer are annealed and before the gate stack is formed (as the first and second fins in Fig. 3-4 of Liu are bent away from each other, their central axes are not parallel to each other).
Regarding claim 9, Liu teaches all limitations of the method for forming the semiconductor device structure as claimed in claim 1, and also teaches wherein the expansion film is conformally formed over the substrate (as shown in Fig. 3 of Liu).
Regarding claim 10, Liu teaches all limitations of the method for forming the semiconductor device structure as claimed in claim 1, and also teaches wherein a first thickness of the expansion film after the expansion film, the substrate, and the isolation layer are annealed is greater than a second thickness of the expansion film before the expansion film, the substrate, and the isolation layer are annealed (as described in [0021] the distance between the first and second fins increase after annealing, so the thickness of the expansion layer in this lateral direction also increases).
Regarding claim 11, Liu teaches a method (method in Figs. 1-6 of Liu) for forming a semiconductor device structure, comprising:
forming an expansion film (the unlabeled liner on top surface of substrate 10) over a substrate (10), wherein the substrate has a base portion (bottom portion of the substrate 10), a first fin (leftmost fin 11 in Fig. 4) and a second fin (second to the left fin 11) over the base portion;
forming an isolation layer (14) over the expansion film; and
annealing (annealing process 15 in [0021] of Liu) the expansion film, the substrate, and the isolation layer, wherein after the expansion film, the substrate, and the isolation layer are annealed, a first central axis of the first fin rotates in a first direction away from the second fin, a second central axis of the second fin rotates in a second direction away from the first fin in a cross-sectional view of the substrate (as described in [0021] of Liu the shrinking of isolation layer 14 in trench 12 is greater than that in the trench 13, thus, the first and second fins are bent in such a way that the top portions are bent away from each other), and a thickness of the expansion film is increased (as a result of the expansion of the distance between the fins).
Regarding claim 12, Liu teaches all limitations of the method for forming the semiconductor device structure as claimed in claim 11, and further comprising:
partially removing the isolation layer and the expansion film to expose a first upper portion of the first fin and a second upper portion of the second fin (as shown in Fig. 5 of Liu); and
forming a gate stack (17 in Fig. 6) wrapping around the first upper portion of the first fin and the second upper portion of the second fin.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Liu, and further in view of Dove (US 8216904 B2).
Regarding claim 13, Liu teaches all limitations of the method for forming the semiconductor device structure as claimed in claim 11, but does not teach wherein a first density of the expansion film is greater than a second density of the isolation layer.
Dove teaches a strain-inducing structure (24 and 26 in Fig. 6 of Liu) comprising: a silicon oxynitride liner (24; other materials are disclosed column 4 lines 23-30 but appropriate material is selected to achieve desired amount of stress on the channel) and a low-k dielectric fill (26).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have used Dove’s materials in order to impart appropriate stress/strain for the channel of the device.
The materials of the expansion film and the isolation layer are the same as the materials disclosed in the specification of the published application, thus, the first and second densities are as required by the claim.
Regarding claim 14, Liu teaches all limitations of the method for forming the semiconductor device structure as claimed in claim 11, but does not teach wherein a first density of the expansion film before the expansion film, the substrate, and the isolation layer are annealed is greater than a second density of the expansion film after the expansion film, the substrate, and the isolation layer are annealed.
Dove teaches a strain-inducing structure (24 and 26 in Fig. 6 of Liu) comprising: a silicon oxynitride liner (24; other materials are disclosed column 4 lines 23-30 but appropriate material is selected to achieve desired amount of stress on the channel) and a low-k dielectric fill (26).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have used Dove’s materials in order to impart appropriate stress/strain for the channel of the device.
As incorporated, the densities and response to thermal annealing are properties of materials. Since the materials of the expansion film and the isolation layer are the same as the materials disclosed in the specification of the published application, thus, the first and second densities are as required by the claim.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Liu.
Regarding claim 15, Liu teaches all limitations of the method for forming the semiconductor device structure as claimed in claim 11, but does not teach that wherein the substrate further has a third fin between the first fin and the second fin, and after the expansion film, the substrate, and the isolation layer are annealed, a third central axis of the third fin is steeper than the first central axis of the first fin in a cross-sectional view of the substrate.
However, it is typical that groups of fins can have many fins, not just two fins as illustrated in the Figures of Liu. As such, the first and second fins can be the two fins at opposite edges of the group while a fin in the middle can be the third fin. As implied in [0021] of Liu, the fins at the edges of the groups are closest to portions of isolation layer that have the largest amount of shrinking. As a result, these fins are bent the most while the fins in the middle are bent the least. In terms of central axis, the central axis of the third fin is steeper than that of the fins at the edge.
Claims 21-23 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Liu, and further in view of Dove (US 8216904 B2).
Regarding claim 21, Liu teaches a method (method in Figs. 1-6 of Liu) for forming a semiconductor device structure (structure in Fig. 6 of Liu), comprising:
forming a first protruding structure (leftmost fin 11 in Fig. 2) and a second protruding structure (second fin 11 to the left);
forming an expansion film (the unlabeled liner on top surface of substrate 10) extending along sidewalls of the first protruding structure and the second protruding structure;
forming an isolation layer (14) over the expansion film;
annealing (annealing process 15 in [0021] of Liu) the expansion film such that the first protruding structure and the second protruding structure are bent (as described in [0021] of Liu the shrinking of isolation layer 14 in trench 12 is greater than that in the trench 13, thus, the first and second fins are bent in such a way that the top portions are bent away from each other);
at least partially removing the isolation layer and the expansion film to at least partially expose the first protruding structure and the second protruding structure (Fig. 5 of Liu); and
forming a gate stack (17 in Fig. 6) over the first protruding structure and the second protruding structure.
But Liu does not teach that wherein a first density of the expansion film is greater than a second density of the isolation layer.
Dove teaches a strain-inducing structure (24 and 26 in Fig. 6 of Liu) comprising: a silicon oxynitride liner (24; other materials are disclosed column 4 lines 23-30 but appropriate material is selected to achieve desired amount of stress on the channel) and a low-k dielectric fill (26).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have used Dove’s materials in order to impart appropriate stress/strain for the channel of the device.
As incorporated, the densities and response to thermal annealing are properties of materials. Since the materials of the expansion film and the isolation layer are the same as the materials disclosed in the specification of the published application, thus, the first and second densities are as required by the claim.
Regarding claim 22, Liu in view of Dove teaches all limitations of the method for forming the semiconductor device structure as claimed in claim 21, and also teaches wherein after the expansion film is annealed, a first central axis of the first fin rotates in a first direction away from the second fin (as a consequence of the discussion in [0021] of Liu), a second central axis of the second fin rotates in a second direction away from the first fin in a cross-sectional view of the substrate (as a consequence of the discussion in [0021] of Liu), and a thickness of the expansion film is increased (as described in [0021] the distance between the first and second fins increase after annealing, so the thickness of the expansion layer in this lateral direction also increases).
Regarding claim 23, Liu in view of Dove teaches all limitations of the method for forming the semiconductor device structure as claimed in claim 21, and also teaches wherein the expansion film and the isolation layer are made of different materials (as taught in claim 21 above).
Regarding claim 25, Liu in view of Dove teaches all limitations of the method for forming the semiconductor device structure as claimed in claim 21, but does not explicitly teach wherein the gate stack comprises a gate electrode layer made of polysilicon.
In a different embodiment, Liu discloses that the gate is made of polysilicon (see [0094] of Liu).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have made the gate stack from polysilicon in order to have withstand higher temperature.
Allowable Subject Matter
Claims 3, 5-8, 24 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 3, the prior art of record does not disclose or fairly suggest a method for forming a semiconductor device satisfying the requirement “wherein a third average distance between the first upper portion of the first fin and the second upper portion of the second fin after the gate stack is formed is less than the first average distance between the first upper portion of the first fin and the second upper portion of the second fin after the expansion film, the substrate, and the isolation layer are annealed and before the gate stack is formed” along with other limitations of the claim 1.
Regarding claim 5, the prior art of record does not disclose or fairly suggest a method for forming a semiconductor device satisfying the requirement “wherein the first central axis of the first upper portion of the first fin is substantially parallel to the second central axis of the second upper portion of the second fin after the gate stack is formed” along with other limitations of claim 4.
Regarding claim 6, the prior art of record does not disclose or fairly suggest a method for forming a semiconductor device satisfying the requirement “wherein a first central axis of the first upper portion of the first fin is parallel to a second central axis of a lower portion of the first fin after the expansion film, the substrate, and the isolation layer are annealed and before the gate stack is formed” along with other limitations of claim 1.
Regarding claim 24, the prior art of record does not disclose or fairly suggest a method for forming a semiconductor device satisfying the requirement “wherein the first protruding structure and the second protruding structure are bent away from each other after the expansion film is annealed, and the first protruding structure and the second protruding structure are bent toward each other after the gate stack is formed” along with other limitations of claim 21.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUAN A HOANG whose telephone number is (571)270-0406. The examiner can normally be reached Monday-Friday 8-9am, 10am-6pm EST.
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/Tuan A Hoang/ Primary Examiner, Art Unit 2898
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