DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-15 and 26-30 in the reply filed on 03/25/2026 is acknowledged.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 13-15 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a law of nature without significantly more. The claims recite, respectively, that the magnitude of the induced eddy current is based on the thickness of the layer where the eddy current is formed, the rotational velocity of the wafer, and the distance between the wafer and the conductive coil that generates the applied magnetic field that causes the formation of the eddy current. These limitations can be understood to describe Faraday’s Law of induction, which describes the relationship between a magnetic field and the induced electrical current, and Ohm’s Law and the equations for magnetic field energy density, which can be used to derive equations which relate the strength of an eddy current with the properties of a material within which an eddy current is formed and the distance between a material within which an eddy current is formed and the source of a magnetic field that is forming the eddy current. This judicial exception is not integrated into a practical application because they are directed to a law of nature. The claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception because they do not have any additional elements within the claims. In each case the claims merely require that the “magnitude of the eddy current induced in the layer” be “based on” some aspect of the operation which, by the laws of nature, will always be determinative of the magnitude of the eddy current.
Claim Rejections - 35 USC § 103
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3 and 5-12 are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura et al. (US-20170057051-A1) in view of Sung et al. (US-20230078095-A1) and Oppenlaender et al. (DE-10336007-A1).
Regarding Claim 1, Nakamura teaches a method (Paragraph [0112] method of polishing including controlling parameters during polishing taught), comprising:
securing a semiconductor wafer to a polishing head of a planarization tool (Paragraph [0046-0048] Figure 1 a top ring (element 1-1), equivalent to claimed polishing head, holds a semiconductor wafer (element W)); and
pressing, using the polishing head, the semiconductor wafer against a polishing pad to planarize a layer on the semiconductor wafer in a planarization operation (Paragraph [0046-0048] Figure 1 A polishing pad (element 1-101) polishes the wafer, when the wafer is pressurized against it. Paragraph [0012] the goal of this technique is to create a flat wafer),
wherein a thickness of the layer is monitored during the planarization operation using a magnetometer device (Paragraph [0110] an eddy current sensor is used to determine the thickness of a film on the wafer. Paragraph [0063] the eddy current detects a magnetic field of an eddy current, and therefore can be considered a magnetometer device).
Nakamura fails to teach that the polishing head is in a processing chamber.
Sung teaches a semiconductor processing system (Paragraph [0002]). Sung teaches that chemical mechanical polishing processes can be conducted within a polishing processing chamber of a semiconductor processing apparatus (Paragraph [0131]).
It would have been obvious to one of ordinary skill in the art to have modified the method of Nakamura by utilizing a planarization tool where the polishing head was inside of a polishing processing chamber and the polishing process was conducted inside of a polishing processing chamber.
This modification would have been obvious to one of ordinary skill in the art because a contained polishing processing chamber would provide the benefit of containing any debris created by the polishing process and allow for easier control of the immediate environmental conditions during the polishing process. Further this modification could be considered the combination of prior art elements according to known methods to yield predictable results. This combination would provide the predictable result of allowing the polishing processing to occur within a specific chamber suitable for holding a polishing process and the necessary equipment. See MPEP 2143(I)(A).
Modified Nakamura fails to teach that the magnetometer device is a superconductor-based magnetometer device.
Oppenlaender teaches matters related to magnetometers (Paragraph [0001]. Oppenlaender teaches that in the current state of the art, magnetometers based on superconducting current loops called superconducting quantum interference detectors (SQUIDs) are used (Paragraph [0002]).
It would have been obvious to one of ordinary skill in the art to have modified the method of modified Nakamura by utilizing a superconductor-based magnetometer as taught by Oppenlaender, as the magnetometer within the method of modified Nakamura.
One of ordinary skill in the art would have been motivated to make this modification because Oppenlaender teaches that superconductor-based magnetometers allow for high-precision measurement of magnetic fields (Paragraph [0002]). Further this modification would have been obvious as it would have been the simple substitution of one known element for another to obtain predictable results. The method of Nakamura teaches the use of a magnetometer device that could have been replaced with the type of magnetometer device taught by Oppenlaender. See MPEP 2143(I)(B).
Regarding Claims 2 and 3, modified Nakamura teaches all the limitations of claim 1 as outlined above. Nakamura further teaches wherein one or more parameters of the planarization operation are modified during the planarization operation based on a change in the thickness of the layer as monitored during the planarization operation, as required by claim 2, and wherein the one or more parameters comprise: a rotational velocity of the semiconductor wafer, a downward force that is used to press the semiconductor wafer against the polishing pad, or a polishing path along which the semiconductor wafer traverses in the planarization operation, as required by claim 3 (Paragraph [0115-0118] figure 14 the pressure applied to the force the semiconductor wafer against the polishing pad is adjusted depending on the measurement of the thickness of the film during processing).
Regarding Claim 5, modified Nakamura teaches all the limitations of claim 1 as outlined above. Modified Nakamura further teaches wherein the thickness of the layer is monitored based on a voltage signal; and wherein the voltage signal is based on a voltage drop across the superconductor-based magnetometer device (Oppenlaender teaches in Paragraph [0002] that in the use of a superconducting quantum interference detector (SQUID) there is a voltage drop across the device that can be used in the measurement of the magnetic field. Nakamura teaches a magnetometer device is used to monitor the thickness, as outline in the rejection of claim 1).
Regarding Claim 6, modified Nakamura teaches all the limitations of claims 1 and 5 as outlined above. Modified Nakamura further teaches wherein a magnitude of the voltage drop across the superconductor-based magnetometer device is based on a field strength of an induced magnetic field (Oppenlaender Paragraph [0002] the voltage drop is related to the strength of the magnetic field and is used to measure the magnetic field); and wherein the field strength of the induced magnetic field is based on the thickness of the layer (Nakamura Paragraph [0139] a magnetic field is generated by the eddy current. Examiner takes the position that the field strength of an induced magnetic field is always based on the magnitude of the current that induces that field and the strength of an eddy current is always based, in part, on the thickness of the conductive material where the eddy current is formed. Although this claim has not been rejected under 35 U.S.C. 101 due to the additional limitation included within the claim, the particular limitation “wherein the field strength of the induced magnetic field is based on the thickness of the layer” can be considered a recitation of the same laws of nature outlined in the section of 35 U.S.C. 101 rejections).
Regarding Claim 7, modified Nakamura teaches all the limitations of claims 1 and 5 as outlined above. Modified Nakamura further teaches wherein a magnitude of the voltage drop across the superconductor-based magnetometer device is based on a field strength of an induced magnetic field (Oppenlaender Paragraph [0002] the voltage drop is related to the strength of the magnetic field and is used to measure the magnetic field); and wherein the induced magnetic field is generated as the semiconductor wafer moves through an applied magnetic field during the planarization operation (Nakamura Paragraphs [0107-0110] the eddy current is measured as the wafer is moving through the magnetic field that generates the eddy current during the polishing process).
Regarding Claim 8, modified Nakamura teaches all the limitations of claims 1, 5, and 7 as outlined above. Modified Nakamura further teaches wherein the applied magnetic field causes an eddy current to be induced in the layer on the semiconductor wafer as the semiconductor wafer moves through the applied magnetic field; and wherein the eddy current causes the induced magnetic field to be generated (Nakamura Paragraph [0072] a magnetic field is formed by voltage from an AC signal source, which forms the eddy current. Paragraphs [0107-0110] the eddy current is measured as the wafer is moving through the magnetic field that generates the eddy current during the polishing process. Paragraph [0139] a magnetic field is generated by the eddy current and is measured).
Regarding Claim 9, modified Nakamura teaches all the limitations of claims 1 as outlined above. Modified Nakamura further teaches wherein the applied magnetic field is generated by providing a direct current or an alternating current through a conductive coil in the processing chamber (Nakamura Paragraph [0072] a magnetic field is formed by voltage from an AC signal source applied to a coil, which forms the eddy current).
Regarding Claim 10, Nakamura teaches a method (Paragraph [0112] method of polishing including controlling parameters during polishing taught), comprising:
securing a semiconductor wafer to a polishing head of a planarization tool (Paragraph [0046-0048] Figure 1 a top ring (element 1-1), equivalent to claimed polishing head, holds a semiconductor wafer (element W)); and
pressing, using the polishing head, the semiconductor wafer against a polishing pad to planarize a layer on the semiconductor wafer in a planarization operation (Paragraph [0046-0048] Figure 1 A polishing pad (element 1-101) polishes the wafer, when the wafer is pressurized against it. Paragraph [0012] the goal of this technique is to create a flat wafer),
wherein a completion time for the planarization operation is based on a threshold for a thickness of the layer (Paragraphs [0112-0118] an end point detection controller ends the polishing based on the thickness of the film measured and a target value for the remaining film - therefore a completion time of the polishing process is based on a threshold value for the film being polished), and
wherein a thickness of the layer is monitored during the planarization operation using a magnetometer device (Paragraph [0110] an eddy current sensor is used to determine the thickness of a film on the wafer. Paragraph [0063] the eddy current detects a magnetic field of an eddy current, and therefore can be considered a magnetometer device).
Nakamura fails to teach that the polishing head is in a processing chamber.
Sung teaches a semiconductor processing system (Paragraph [0002]). Sung teaches that chemical mechanical polishing processes can be conducted within a polishing processing chamber of a semiconductor processing apparatus (Paragraph [0131]).
It would have been obvious to one of ordinary skill in the art to have modified the method of Nakamura by utilizing a planarization tool where the polishing head and polishing process was conducted inside of a polishing processing chamber.
This modification would have been obvious to one of ordinary skill in the art because a contained polishing processing chamber would provide the benefit of containing any debris created by the polishing process and allow for easier control of the immediate environmental conditions around the polishing process. Further this modification could be considered the combination of prior art elements according to known methods to yield predictable results. This combination would provide the predictable result of allowing the polishing processing to occur within a specific chamber suitable for holding a polishing process and the necessary equipment. See MPEP 2143(I)(A).
Modified Nakamura fails to teach that the magnetometer device is a superconductor-based magnetometer device.
Oppenlaender teaches matters related to magnetometers (Paragraph [0001]. Oppenlaender teaches that in the current state of the art, magnetometers based on superconducting current loops called superconducting quantum interference detectors (SQUIDs) are used (Paragraph [0002]).
It would have been obvious to one of ordinary skill in the art to have modified the method of modified Nakamura by utilizing a superconductor-based magnetometer as taught by Oppenlaender.
One of ordinary skill in the art would have been motivated to make this modification because Oppenlaender teaches that superconductor-based magnetometers allow for high-precision measurement of magnetic fields (Paragraph [0002]). Further this modification would have been obvious as it would have been the simple substitution of one known element for another to obtain predictable results. The method of Nakamura teaches the use of a magnetometer device that could have been replaced with the type of magnetometer device taught by Oppenlaender. See MPEP 2143(I)(B).
Regarding Claim 11, modified Nakamura teaches all the limitations of claim 10 as outlined above. Modified Nakamura further teaches wherein the thickness of the layer is monitored based on a voltage drop across the superconductor-based magnetometer device; wherein a magnitude of the voltage drop across the superconductor-based magnetometer device is based on a field strength of an induced magnetic field (Oppenlaender Paragraph [0002] the voltage drop is related to the strength of the magnetic field and is used to measure the magnetic field); and wherein the induced magnetic field is generated as the semiconductor wafer moves through an applied magnetic field during the planarization operation (Nakamura Paragraphs [0107-0110] the eddy current is measured as the wafer is moving through the magnetic field that generates the eddy current during the polishing process).
Regarding Claim 12, modified Nakamura teaches all the limitations of claims 10 and 11 as outlined above. Modified Nakamura further teaches wherein the applied magnetic field causes an eddy current to be induced in the layer on the semiconductor wafer as the semiconductor wafer moves through the applied magnetic field (Nakamura Paragraphs [0107-0110] the eddy current is measured as the wafer is moving through the magnetic field that generates the eddy current during the polishing process); and wherein the field strength of the induced magnetic field is based on a magnitude of the eddy current induced in the layer on the semiconductor wafer (Examiner takes the position that the field strength of an induced magnetic field is always based on the magnitude of the current that induces that field. Although this claim has not been rejected under 35 U.S.C. 101 due to the additional limitation included within the claim, the particular limitation “wherein the field strength of the induced magnetic field is based on a magnitude of the eddy current induced in the layer on the semiconductor wafer” can be considered a recitation of the same laws of nature outlined in the section of 35 U.S.C. 101 rejections).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Nakamura in view of Sung and Oppenlaender, and further in view of Deshpande et al (US-20220193858-A1).
Regarding Claim 4, modified Nakamura teaches all the limitations of claims 1 and 2 as outlined above.
Modified Nakamura fails to teach wherein a machine learning model is used to modify the one or more parameters of the planarization operation based on the change in the thickness of the layer as monitored during the planarization operation.
Deshpande teaches methods of polishing (Paragraph [0002]). Deshpande teaches that a machine learning AI model can be used to adjust control parameters of the process based on measurements gathered during processing (Paragraph [0088]).
It would have been obvious to one of ordinary skill in the art to have modified the method of modified Nakamura by implementing the machine learning AI model taught by Deshpande to assist in the adjustment of control parameters during the process.
One of ordinary skill in the art would have been motivated to make this modification because it would have allowed for improved planarization performance (Deshpande Paragraph [0031]). Further, this modification could have been considered the combination of prior art elements according to known methods to yield predictable results. This modification would have had the predictable result of allowing the machine learning AI model to make adjustments to the process parameters to improve the process results. See MPEP 2143(I)(A).
Claims 26-27 and 29-30 are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura in view of Sung.
Regarding Claim 26, Nakamura teaches a method (Paragraph [0112] method of polishing including controlling parameters during polishing taught), comprising:
securing a semiconductor wafer to a polishing head of a planarization tool (Paragraph [0046-0048] a top ring (element 1-1), equivalent to claimed polishing head, holds a semiconductor wafer (element W)); and
pressing, using the polishing head, the semiconductor wafer against a polishing pad to planarize a layer on the semiconductor wafer in a planarization operation (Paragraph [0046-0048] A polishing pad (element 1-101) polishes the wafer, when the wafer is pressurized against it. Paragraph [0012] the goal of this technique is to create a flat wafer),
wherein a thickness of the layer is monitored during the planarization operation (Paragraph [0110] an eddy current sensor is used to determine the thickness of a film on the wafer. Paragraph [0063] the eddy current detects a magnetic field of an eddy current, and therefore can be considered a magnetometer device).
Nakamura fails to teach that the polishing head is in a processing chamber.
Sung teaches a semiconductor processing system (Paragraph [0002]). Sung teaches that chemical mechanical polishing processes can be conducted withing a polishing processing chamber of a semiconductor processing apparatus (Paragraph [0131]).
It would have been obvious to one of ordinary skill in the art to have modified the method of Nakamura by utilizing a planarization tool where the polishing head and polishing process was conducted inside of a polishing processing chamber.
This modification would have been obvious to one of ordinary skill in the art because a contained polishing processing chamber would provide the benefit of containing any debris created by the polishing process and allow for easier control of the immediate environmental conditions around the polishing process. Further this modification could be considered the combination of prior art elements according to known methods to yield predictable results. This combination would provide the predictable result of allowing the polishing processing to occur within a specific chamber suitable for holding a polishing process and the necessary equipment. See MPEP 2143(I)(A).
Regarding Claim 27, modified Nakamura teaches all the limitations of claim 26 as outlined above. Nakamura teaches that the method further comprises: modifying one or more parameters of the planarization operation (Paragraph [0115-0118] figure 14 the pressure applied to the force the semiconductor wafer against the polishing pad is adjusted depending on the measurement of the thickness of the film during processing).
Regarding Claim 29, modified Nakamura teaches all the limitations of claim 26 as outlined above. Nakamura teaches that the method further comprises: wherein the one or more parameters of the planarization operation are modified based on the thickness of the layer being modified during the planarization operation (Paragraph [0115-0118] figure 14 the pressure applied to the force the semiconductor wafer against the polishing pad is adjusted depending on the measurement of the thickness of the film during processing).
Regarding Claim 30, modified Nakamura teaches all the limitations of claim 26 as outlined above. Nakamura further teaches wherein pressuring the semiconductor wafer against the polishing pad comprises: modifying a downward force of the semiconductor wafer against the polishing pad based on the one or more parameters (Paragraph [0115-0118] figures 11 and 14 the pressure applied to the force the semiconductor wafer against the polishing pad is adjusted depending on the measurement of the thickness of the film during processing. Pressures are applied from pressure chambers (elements P1 to P7) to that apply downward force on the wafer (element W1)).
Claim 28 are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura in view of Sung, and further in view of Deshpande.
Regarding Claim 28, modified Nakamura teaches all the limitations of claims 1 and 2 as outlined above.
Modified Nakamura fails to teach wherein a machine learning model is used to modify the one or more parameters of the planarization operation based on the change in the thickness of the layer as monitored during the planarization operation.
Deshpande teaches methods of polishing (Paragraph [0002]). Deshpande teaches that a machine learning AI model can be used to adjust control parameters of the process based on measurements gathered during processing (Paragraph [0088]).
It would have been obvious to one of ordinary skill in the art to have modified the method of modified Nakamura by implementing the machine learning AI model taught by Deshpande to assist in the adjustment of control parameters during the process.
One of ordinary skill in the art would have been motivated to make this modification because it would have allowed for improved planarization performance (Deshpande Paragraph [0031]). Further, this modification could have been considered the combination of prior art elements according to known methods to yield predictable results. This modification would have had the predictable result of allowing the machine learning AI model to make adjustments to the process parameters to improve the process results. See MPEP 2143(I)(A).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDREW KEELAN LAOBAK whose telephone number is (703)756-5447. The examiner can normally be reached Monday - Friday 8:00am - 5:30pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Allen can be reached at 571-270-3176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/A.K.L./Examiner, Art Unit 1713 /DUY VU N DEO/Primary Examiner, Art Unit 1713
Prosecution Insights