DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention II and species 2 in the reply filed on 9/2/25 is acknowledged.
Applicant has stated that claims 15-19 and newly added claims 21-35 read on the elected invention and species. Examiner respectfully disagrees with respect to claims 17, 25, and 35.
Applicant elected species 2, which corresponds to the method to form the device of Fig. 18A-B. As seen from Fig. 18A-B, the device contains a crystalline orientation switching layer (105), so the method to form that device cannot comprise replacing the crystalline orientation switching layer with an isolation layer or dielectric layer, as required by claims 17 and 25. Similarly, as seen from Fig. 18A-B, the device contains a metal oxide layer (105), so the method to form that device cannot comprise replacing the metal oxide layer with a dielectric layer, as required by claim 35.
Thus, claims 15-16, 18-19, 21-24, and 26-34 read on the elected invention (II) and species (2).
Information Disclosure Statement
The information disclosure statements (IDS) were submitted on 4/24/23, 2/14/25, and 7/31/25. The submissions are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements have been considered by the examiner.
Specification
The title of the invention is not descriptive as it is generic. A new title is required that is more clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 19 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 19 recites the term “about”. The term "about" is a relative term which renders the claim indefinite; it is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. “About” is defined as "almost or nearly—used to indicate that a number, amount, time, etc., is not exact or certain” (see Merriam Webster online dictionary). The term “about” modifies a target, and implicitly requires boundaries at some maximum value above the target and at some minimum value below the target beyond which one is not “about” the target any more. Neither the claims, nor the specification, defines these boundaries. Thus, it is unclear whether one must be within some small percentage of deviation of the target (such as 0.01 %, 0.1 %, 1 %, 2 %, 5 %, 10 %, or some other percentage) or within a certain number of units of the target and specifically which of these possible values defines the boundaries. If one were to poll 100 people having ordinary skill in the art, there would be many different responses for the boundaries. Thus, determining whether one is infringing the limitation is subjective, rather than objective, and thus the claim is unclear. Therefore, the claim is rejected as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant, regards as the invention.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 15, 21, and 26 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mannebach et al. (U.S. 2020/0295127 A1; “Mannebach”).
Regarding claim 15, Mannebach discloses a method, comprising:
Forming a first stack of alternating first semiconductor channel layers (106-1, Fig. 2A) and first sacrificial layers (104 within 130-1, Fig. 2A) over a first substrate (102, Fig. 2A), wherein the first semiconductor channel layers have a first crystalline orientation ([0020]);
Forming a second stack of alternating second semiconductor channel layers (106-2, Fig. 2A) and second sacrificial layers (104 within 106-2, Fig. 2A) over the first stack ([0020]), wherein the first semiconductor channel layers have a second crystalline orientation different from the first crystalline orientation ([0023]);
Forming first source/drain epitaxy structures (118-1, Fig. 8B) on opposite ends of each of the first semiconductor channel layers (106-1, Fig. 8B) ([0021]);
Forming second source/drain epitaxy structures (118-2, Fig. 8B) on opposite ends of each of the second semiconductor channel layers (106-2, Fig. 8B) ([0021]);
Replacing the first sacrificial layers with a first gate structure (122, 124-1, Fig. 11B), the first gate structure wrapping around each of the first semiconductor channel layers (106-1, Fig. 11A-B) ([0040]); and
Replacing the second sacrificial layers with a second gate structure (122, 124-2, Fig. 11B), the second gate structure wrapping around each of the second semiconductor channel layers (106-2, Fig. 11A-B) ([0040]).
Regarding claim 21, Mannebach discloses a method, comprising:
Depositing a first semiconductor channel layer (106-1, Fig. 2A) over a substrate (102, Fig. 2A), wherein the first semiconductor channel layer has a first crystalline orientation ([0020], [0023]);
Depositing a crystalline orientation switching layer (bottommost 106-2, Fig. 2A) over the first semiconductor channel layer, wherein the crystalline orientation switching layer has a second crystalline orientation that is different from the first crystalline orientation ([0020], [0023]);
Depositing a second semiconductor channel layer (uppermost 106-2, Fig. 2A) over the crystalline orientation switching layer (bottommost 106-2, Fig. 2A), such that the second semiconductor channel layer has the second crystalline orientation ([0020], [0023]);
Forming first source/drain structures (118-1, Fig. 8B) on opposite sides of the first semiconductor channel layer (106-1, Fig. 2A) ([0021]);
Forming second source/drain structures (118-2, Fig. 8B) on opposite sides of the second semiconductor channel layer (uppermost 106-2, Fig. 2A) ([0021]); and
Forming first (122, 124-1, Fig. 11B) and second gate (122, 124-2, Fig. 11B) structures over the first and second semiconductor channel layers, respectively ([0040]).
Regarding claim 26, Mannebach discloses forming an isolation structure over one of the first source/drain structures (118-1, Fig. 8B) prior to forming the second source/drain structures (118-2, Fig. 8B), wherein one of the second source/drain structures (118-2, Fig. 8B) is formed over the one of the first source/drain structures (118-1, Fig. 8B).
Claim(s) 15-16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mannebach et al. (U.S. 2020/0295127 A1; alternative interpretation “Mannebach 1”).
Regarding claim 15, Mannebach 1 discloses a method, comprising:
Forming a first stack of alternating first semiconductor channel layers (106-1, Fig. 2A) and first sacrificial layers (104 within 130-1, Fig. 2A) over a first substrate (102, Fig. 2A), wherein the first semiconductor channel layers have a first crystalline orientation ([0020]);
Forming a second stack of alternating second semiconductor channel layers (second from bottom 106-2 through uppermost 106-2, Fig. 2A) and second sacrificial layers (104 within 106-2, Fig. 2A) over the first stack ([0020]), wherein the first semiconductor channel layers have a second crystalline orientation different from the first crystalline orientation ([0023]);
Forming first source/drain epitaxy structures (118-1, Fig. 8B) on opposite ends of each of the first semiconductor channel layers ([0021]);
Forming second source/drain epitaxy structures (118-2, Fig. 8B) on opposite ends of each of the second semiconductor channel layers ([0021]);
Replacing the first sacrificial layers with a first gate structure (122, 124-1, Fig. 11B), the first gate structure wrapping around each of the first semiconductor channel layers (106-1, Fig. 11A-B) ([0040]); and
Replacing the second sacrificial layers with a second gate structure (122, 124-2, Fig. 11B), the second gate structure wrapping around each of the second semiconductor channel layers (106-2, Fig. 11A-B) ([0040]).
Regarding claim 16, Mannebach 1 discloses depositing a crystalline orientation switching layer (bottommost 106-2, Fig. 2A) over the first stack, wherein the second stack is formed over (on top of) the crystalline orientation switching layer, and wherein the crystalline orientation switching layer (bottommost 106-2, Fig. 2A) has a third crystalline orientation that is different from the first crystalline orientation and is the same as the second crystalline orientation ([0023]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 22-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mannebach et al. (U.S. 2020/0295127 A1; “Mannebach”) as applied to claim 21 above, and further in view of Cheng et al. (U.S. 2023/099156 A1; “Cheng”).
Regarding claims 22-23, Mannebach discloses the first semiconductor channel layers (106-1, Fig. 8B) correspond to either a PMOS transistor or NMOS transistor and the second semiconductor channel layers (106-2, Fig. 8B) correspond to a PMOS transistor, when the first semiconductor channel layers correspond to an NMOS transistor, or correspond to an NMOS transistor, when the first semiconductor channel layers correspond to a PMOS transistor ([0025]). Yet, Mannebach does not disclose the semiconductor channel layers corresponding to the PMOS have a (110) crystalline orientation and the semiconductor channel layers corresponding to the NMOS have a (100) crystalline orientation.
However, Cheng discloses semiconductor channel layers corresponding to a PMOS have a (110) crystalline orientation and semiconductor channel layers corresponding to an NMOS have a (100) crystalline orientation ([0062]). This advantageously improves device performance of the PMOS and NMOS transistors, respectively. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Mannebach with the semiconductor channel layers corresponding to the PMOS to have a (110) crystalline orientation and semiconductor channel layers corresponding to the NMOS have a (100) crystalline orientation, as taught by Cheng, so as to improve overall device performance.
Regarding claim 24, Mannebach discloses a substrate (102, Fig. 2B) but does not disclose it has a third crystalline orientation the same as the first crystalline orientation. However, Cheng discloses a substrate with a same crystalline orientation as that of first semiconductor channel layer ([0049]). This has the advantage of lattice matching between the substrate and the first semiconductor channel layer. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Mannebach with the substrate having the same crystalline orientation as that of first semiconductor channel layer, as taught by Cheng, so as to lattice match the first semiconductor channel layer.
Claim(s) 29 and 34 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dewey et al. (U.S. 2020/0105751 A1; “Dewey”) in view of Li et al. (U.S. 2020/0335581 A1; “Li”).
Regarding claims 29 and 34, Dewey discloses a method, comprising:
Depositing a first semiconductor channel layer (205, Fig. 2a) over a substrate (211, Fig. 2a) ([0027]);
Depositing an insulating layer (207, Fig. 2a) over the first semiconductor channel layer ([0027]-[0028]);
Depositing a second semiconductor channel layer (202, Fig. 2a) over the insulating layer ([0027]);
Forming first source/drain structures (222, Fig. 2a) on opposite sides of the first semiconductor channel layer ([0033]);
Forming second source/drain structures (220, Fig. 2a) on opposite sides of the second semiconductor channel layer ([0033]); and
Forming first (203, 206, Fig. 2a) and second (201, 204, Fig. 2a) gate structures over the first and second semiconductor channel layers, respectively ([0030]-[0031]).
Yet, Dewey does not disclose the insulating layer is a metal oxide layer. However, Li discloses an insulating layer (108, Fig. 1) between vertically stacked structures is a metal oxide layer such as yttrium oxide or cerium oxide ([0040]). A metal oxide layer such as yttrium oxide or cerium oxide has the advantage being able to be epitaxially grown while also providing sufficient electrical isolation between the vertically stacked structures. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Dewey with the insulating layer comprising a metal oxide layer, as taught by Li, so as to enable epitaxial growth while providing sufficient electrical isolation between vertically stacked structures.
Allowable Subject Matter
Claims 18, 27-28, and 30-33 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/REEMA PATEL/Primary Examiner, Art Unit 2812 12/11/2025