DETAILED ACTION
This Office action is in response to the amendment and election filed 27 February 2026. By this amendment, claims 1-15 and 18 are cancelled; claims 21-36 are new. Claims 16-17 and 19-36 are currently pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election without traverse of Invention II, Species III, claims 16-17, 19-20, and newly added claims 21-36 in the reply filed on 17 February 2026 is acknowledged.
Newly submitted claims 21-36 are directed to an invention that is independent or distinct from the invention originally claimed for the following reasons: the claims to the different species are shown/described separately in the specification and drawings, and have at least the following patentably distinct features: patterning the floating gate layer into a floating gate having a second width using a second etching process, and forming a third ILD surrounding the sidewalls of the blocking dielectric, wherein the sidewalls of the blocking dielectric are laterally spaced from the sidewalls of the tunnel dielectric.
Since applicant has received an action on the merits for the originally presented invention, this invention has been constructively elected by original presentation for prosecution on the merits. Accordingly, claims 21-36 are withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03.
To preserve a right to petition, the reply to this action must distinctly and specifically point out supposed errors in the restriction requirement. Otherwise, the election shall be treated as a final election without traverse. Traversal must be timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are subsequently added, applicant must indicate which of the subsequently added claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
Claims 21-36 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 17 February 2026.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 16 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2022/0285396 A1 to Huang et al. (hereinafter “Huang”)
Regarding independent claim 16, Huang (Fig. 10A) discloses a method of forming an integrated device, comprising:
forming an interlayer dielectric (ILD) layer over a substrate (dielectric layers present under 108, not illustrated in Fig. 10A, disclose the recited ILD and substrate; ¶ 0053 - “108 may be one of a stack of dielectric layers in a BEOL structure formed over a FEOL structure”);
forming a control gate 100 (¶ 0053) with a first length over the ILD layer (Fig. 10A - unpictured dielectric layer below 108);
forming a tunnel dielectric 110 (¶ 0055) over a top surface of the control gate 100 (Fig. 10A);
forming a floating gate 130 (¶ 0090) with a second length over the tunnel dielectric 110, the tunnel dielectric separating the floating gate 130 and the control gate 100, wherein the first length is less than the second length (Fig. 10A); and
forming a blocking dielectric 114/116 (¶ 0090) and a channel 102 (¶ 0090) over the tunnel dielectric 110, the blocking dielectric 114/116 separating the floating gate 130 and the channel 102 (Fig. 10A).
Claim 16 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 2024/0079495 A1 to Van Dal et al. (hereinafter “Van Dal”).
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Regarding independent claim 16, Van Dal (Fig. 1A) discloses a method of forming an integrated device, comprising:
forming an interlayer dielectric (ILD) layer over a substrate (dielectric layers present under 101, not shown in Fig. 1A, disclose the recited ILD and substrate; ¶ 0027 - “dielectric layer may include more than one dielectric layers”; ¶ 0029 - “101 is provided over a substrate”);
forming a control gate 102 (¶ 0028) with a first length over the ILD layer (Fig. 1A);
forming a tunnel dielectric 104 (¶ 0028) over a top surface of the control gate 102 (Fig. 1A);
forming a floating gate 106 (¶ 0028) with a second length over the tunnel dielectric 104, the tunnel dielectric separating the floating gate 106 and the control gate 102, wherein the first length is less than the second length (Fig. 1A); and
forming a blocking dielectric 108 (¶ 0038 - insulating layer/ferroelectric insulating layer) and a channel 110 (¶ 0038) over the tunnel dielectric 104, the blocking dielectric 108 separating the floating gate 106 and the channel 110 (Fig. 1A).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Huang.
Regarding claim 17, Huang (Fig. 10A) discloses the method of claim 16, wherein forming the floating gate 130, the blocking dielectric 114/116, and the channel 102 over the tunnel dielectric 110 further comprises: depositing a floating gate layer 130, a blocking layer 114/116, and a channel layer 102 over the substrate and the tunnel dielectric 110 (Fig. 10A).
In the instant embodiment, Huang does not expressly disclose: patterning the floating gate layer, the blocking layer, and the channel layer using one etching process to form the floating gate, the blocking dielectric, and the channel directly over the tunnel dielectric. In a different embodiment, Huang discloses patterning the floating gate layer, the blocking layer, and the channel layer using one etching process to form the floating gate, the blocking dielectric, and the channel directly over the tunnel dielectric (¶ 0100). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Huang to include patterning and etching as recited above, for the purpose of forming stacked memory structures (¶ 0097).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Huang as applied to claim 16 above, and further in view of US 5,661,056 to Takeuchi (hereinafter “Takeuchi”).
Regarding claim 19, Huang discloses the method of claim 16, however fails to expressly disclose: wherein forming the control gate and the tunnel dielectric over the substrate further comprises: forming a silicon layer over the ILD layer; and performing an anneal to form a silicon dioxide layer on the silicon layer. Examiner notes that the claim does not recite a relationship between the control gate and the silicon layer formed, or the tunnel dielectric and silicon dioxide layer formed.
In the same field of endeavor, Takeuchi discloses the use of silicon layers in forming gates, and performing an anneal to form a silicon dioxide layer on the silicon layer (col. 4, ll. 47-67). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Huang to include the steps of Takeuchi for the purpose of forming the control gate utilizing an art-recognized alternative material known to be suitable for use in gates, and to improve efficiency of the manufacturing process (col. 4, ll. 47-67).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Huang as applied to claim 16 above, and further in view of US 2019/0326252 to Mandalapu et al. (hereinafter “Mandalapu”).
Regarding claim 20, Huang discloses the method of claim 16, however fails to expressly disclose: wherein forming the control gate and the tunnel dielectric over the substrate further comprises: forming the tunnel dielectric and the control gate on a separate wafer; bonding the separate wafer to the integrated device; and removing the separate wafer, leaving the tunnel dielectric and control gate on the integrated device.
Huang does disclose globally forming layers over control gate 100 then patterning (¶ 0100), however does not disclose forming the tunnel dielectric and control gate on a separate wafer and transferring them. In the same field of endeavor, Mandalapu (Fig. 1) discloses forming layers on a separate wafer 102 (¶ 0030; Fig. 1A); bonding the separate wafer to a device substrate 114 (¶ 0037; Fig. 1B); and removing the separate wafer, leaving the layers (Fig. 1C). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Huang to use the technique of Manalapu for the purpose of increase flexibility and efficiency in the manufacturing method, e.g., the ability to use pre-formed layers on separate wafers, which reduces the number of layers to be formed or deposited individually.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Van Dal.
Regarding claim 17, Van Dal (Fig. 1A) discloses the method of claim 16, wherein forming the floating gate 106, the blocking dielectric 108, and the channel 110 over the tunnel dielectric 104 further comprises: depositing a floating gate layer 106, a blocking layer 108, and a channel layer 110 over the substrate and the tunnel dielectric 104 (Fig. 1A).
In the instant embodiment, Van Dal does not expressly disclose: patterning the floating gate layer, the blocking layer, and the channel layer using one etching process to form the floating gate, the blocking dielectric, and the channel directly over the tunnel dielectric. In a different embodiment, Van Dal discloses patterning the multiple device layers 905-907 (¶ 0070) using one etching process to form the device structures (Figs. 9K-9O; ¶ 0070). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Van Dal to include patterning and etching as recited above, for the purpose of forming the structure in an art-recognized alternative way (i.e., instead of patterning a dielectric layer and depositing the layers within the patterned area as described in ¶¶ 0032-33, depositing the layers and then subsequently patterning as described in ¶ 0070).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Van Dal as applied to claim 16 above, and further in view of Takeuchi.
Regarding claim 19, Van Dal discloses the method of claim 16, however fails to expressly disclose: wherein forming the control gate and the tunnel dielectric over the substrate further comprises: forming a silicon layer over the ILD layer; and performing an anneal to form a silicon dioxide layer on the silicon layer. Examiner notes that the claim does not recite a relationship between the control gate and the silicon layer formed, or the tunnel dielectric and silicon dioxide layer formed.
In the same field of endeavor, Takeuchi discloses the use of silicon layers in forming gates, and performing an anneal to form a silicon dioxide layer on the silicon layer (col. 4, ll. 47-67). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Van Dal to include the steps of Takeuchi for the purpose of forming the control gate utilizing an art-recognized alternative material known to be suitable for use in gates, and to improve efficiency of the manufacturing process (col. 4, ll. 47-67).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Van Dal as applied to claim 16 above, and further in view of Mandalapu.
Regarding claim 20, Van Dal discloses the method of claim 16, however fails to expressly disclose: wherein forming the control gate and the tunnel dielectric over the substrate further comprises: forming the tunnel dielectric and the control gate on a separate wafer; bonding the separate wafer to the integrated device; and removing the separate wafer, leaving the tunnel dielectric and control gate on the integrated device.
Van Dal does disclose forming layers then patterning (see Figs. 9K-9O), however does not disclose forming the tunnel dielectric and control gate on a separate wafer. In the same field of endeavor, Mandalapu (Fig. 1) discloses forming layers on a separate wafer 102 (¶ 0030; Fig. 1A); bonding the separate wafer to a device substrate 114 (¶ 0037; Fig. 1B); and removing the separate wafer, leaving the layers (Fig. 1C). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Van Dal to use the technique of Manalapu for the purpose of increase flexibility and efficiency in the manufacturing method, e.g., the ability to use pre-formed layers on separate wafers, which reduces the number of layers to be formed or deposited individually.
Conclusion
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CANDICE Y. CHAN
Examiner
Art Unit 2813
3 April 2026
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813