DETAILED ACTION
This action is responsive to the amendments filed August 2, 2025. Prior to entry, claims 1-20 were pending. Claims 2 and 14 have been cancelled. Claims 1, 3, and 13 have been amended. Thus, claims 1, 3-13, and 15-20 are currently pending. Claims 1 and 13 are independent.
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The disclosure is objected to because of the following informalities: The Specification is objected to under 37 CFR 1.71 and MPEP § 608.01 for failing to maintain a clear and concise description of the invention due to insertion of duplicate generic paragraphs 35, 41 and 43. This duplication introduces unnecessary redundancy into the record and detracts from clarity of the disclosure. Applicant is requested to cancel the duplicate text in the next response to this Office action.
Response to Amendment
Applicant's amendments to claim 3 addressing the indefiniteness rejection are acknowledged and accepted. The rejection for claim 3 under 35 USC § 112(b) is withdrawn.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1, 3-5, 10-11, 13, 15-16, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Mehta et al. (US 20180166129 – of record; "Mehta") in view of Houston (US 20060274587).
Regarding independent claim 1, Mehta discloses a circuit comprising:
a memory cell; a pair of bit lines, coupled to the memory cell (Fig. 3; memory cell 214, and bit lines 222 and 224);
a precharge circuit, coupled between the pair of bit lines, wherein the precharge circuit is configured to precharge each of the bit lines to approximately a first supply voltage to begin a write operation (Fig. 4; pre-charge circuit 460. It is noted that the PMOS transistors of the pre-charge circuit, when turned on, would necessarily pull up the bit lines to the (first) supply voltage.);
a multiplexer, configured to select which one of the pair of bit lines is a zero bit driven to a low logic level during the write operation and after the precharge circuit is turned off (Fig. 8; multiplexor 208' which includes transistors Write Mux 802 and 804 which select a bit line.);
and a pull-up circuit, coupled to the pair of bit lines, wherein after the write operation begins, the pull-up circuit is configured to select which one of the pair of bit lines is a non-zero bit line driven to a high logic level (Fig. 8; pull -ups of 814)
Mehta is silent with respect to a dual-rail power supply for memory cell and pre-charge/write driver circuitry.
However, Houston teaches, wherein the memory cell is supplied with a second supply voltage; wherein the second supply voltage exceeds the first supply voltage (Fig. 2C where it illustrates the precharge circuit powered by VddPCHG which is shown in Fig. 3 to be Vdd-Vtn. See also Abstr; "a bit line precharge circuit coupled to bit lines of the SRAM array and configured to precharge the bit lines to a precharge voltage substantially lower than the word line driver voltage.).
Mehta and Houston are from the same field of endeavor as Applicant's invention directed to SRAM design and operation, specifically write circuitry, pre-charge techniques, and power optimization of the memory device. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the single-rail SRAM write driver scheme of Mehta (which uses a common Vdd domain for both the memory cell and the bit line pre-charge) to implement a dual-rail power supply configuration as taught by Houston in which the bit lines are precharged to a firs supply voltages that is substantially lower than the second supply voltage supplied to the memory cell. Doing so would reduce dynamic power consumption associated with pre-charging bit lines, which is a well-recognized design goal in SRAMs, particularly at advanced process nodes. This combination is merely the use of a known technique (dual-rail supply with lower periphery voltage) to improve a similar device (Mehta's SRAM write circuit) in the same way.
Regarding claim 3, Mehta and Houston combined disclose the limitations of claim 1.
As applied, Metha further discloses wherein the pull-up circuit charges (Fig. 8: 806 and 808) the non-zero bit to approximately the first supply voltage according to the input data (Fig. 1: 102 and 112).
Regarding claim 4, Mehta and Houston combined disclose the limitations of claim 1.
As applied, Mehta further discloses wherein the multiplexer (Fig. 8: 802 and 804) further comprises:
a pair of pass transistors (Fig. 8: Write Mux 208’, but also see Fig. 1-7), wherein each of the pair of pass transistors is coupled to different one of the pair of bit lines (Fig. 8: 802 and 804) wherein the pair of pass transistors select which one of the pair of bit lines is the zero bit during the write operation by coupling the zero bit to a ground according to input data.
Regarding claim 5, Mehta and Houston combined disclose the limitations of claim 4.
As applied, Mehta further discloses wherein the pull-up circuit further comprises:
a first stack of pull-up transistors (Fig. 8: 806 and 810, but also see Fig. 1-7); and
a second stack of pull-up transistors (Fig. 8: 808 and 812, but also see Fig. 1-7);
wherein each of the first stack of pull-up transistors and the second stack of pull- up transistors is coupled (Fig. 8: 208’ and 210’) to different one of the pair of bit lines;
wherein after the write operation begins, the first stack of pull-up transistors and the second stack of pull-up transistors select (Fig. 8: 208’ and 210’) which one of the pair of bit lines is the non-zero bit line by charging the non-zero bit to approximately the first supply voltage according to the input data.
Regarding claim 10, Mehta and Houston combined disclose the limitations of claim 1.
As applied, Mehta further discloses comprising:
a write driver (Fig. 2: 210, but also see Fig. 8: 810 and 812), coupled to the pair of bit lines through the multiplexer and configured to drive the zero bit to the low logic level and to drive the non-zero bit to the high logic level.
Regarding claim 11, Mehta and Houston combined disclose the limitations of claim 10.
As applied, Mehta further discloses wherein the multiplexer further comprises:
a pair of pass transistors (Fig. 8: 802 and 804), wherein each of the pair of pass transistors is coupled to different one of the pair of bit lines;
wherein when the memory cell is selected, the pair of pass transistors are turned on so that the write driver (Fig. 8: 210’, 810 and 812) is coupled to the pair of bit lines.
Regarding independent claim 13, Mehta discloses a method for performing a write operation on a memory cell, comprising:
precharging a pair of bit lines coupled to the memory cell to approximately a first supply voltage to begin the write operation (Fig. 3; memory cell 214, and bit lines 222 and 224. Also Fig. 4; pre-charge circuit 460. It is noted that the PMOS transistors of the pre-charge circuit, when turned on, would necessarily pull up the bit lines to the (first) supply voltage);
after turning off precharging of the pair of bit lines, selecting which one of the pair of bit lines (Fig. 8 multiplexor 208’) is a zero bit driven to a low logic level; and
after the write operation begins, selecting which one of the pair of bit lines is a non-zero bit line driven to a high logic level (Fig. 8, where it illustrates transistors 802 and 804 which select the bit line).
Mehta is silent with respect to a dual-rail power supply for memory cell and pre-charge/write driver circuitry.
However, Houston teaches, wherein the memory cell is supplied with a second supply voltage; wherein the second supply voltage exceeds the first supply voltage (Fig. 2C where it illustrates the precharge circuit powered by VddPCHG which is shown in Fig. 3 to be Vdd-Vtn. See also Abstr; "a bit line precharge circuit coupled to bit lines of the SRAM array and configured to precharge the bit lines to a precharge voltage substantially lower than the word line driver voltage.).
Mehta and Houston are from the same field of endeavor as Applicant's invention directed to SRAM design and operation, specifically write circuitry, pre-charge techniques, and power optimization of the memory device. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the single-rail SRAM write driver scheme of Mehta (which uses a common Vdd domain for both the memory cell and the bit line pre-charge) to implement a dual-rail power supply configuration as taught by Houston in which the bit lines are precharged to a firs supply voltages that is substantially lower than the second supply
Regarding claim 15, Mehta and Houston combined disclose the limitations of claim 13, wherein the step of selecting which one of the pair of bit lines (Fig. 8: Write Mux 208’, but also see Fig. 1-7) is the zero bit driven to the low logic level further comprises:
selecting which one of the pair of bit lines (Fig. 8: 802 and 804) is the zero bit by coupling the zero bit to a ground according to input data.
Regarding claim 16, Mehta and Houston combined disclose the limitations of claim 15.
As applied, Mehta further discloses wherein the step of selecting (Fig. 8: 802 and 804) which one of the pair of bit lines is the non-zero bit line driven to the high logic level further comprises:
selecting which one of the pair of bit lines is the non-zero bit line by charging the non-zero bit (Fig. 8: 810 and 812) to approximately the first supply voltage according to the input data.
Regarding claim 19, Mehta and Houston combined disclose the limitations of claim 13.
As applied, Mehta further discloses wherein the step of selecting which one of the pair of bit lines is the zero bit driven to the low logic level further comprises:
generating a zero-bit signal based on input data by a write driver (Fig. 8: 210); and
providing the zero-bit signal to the zero bit (Fig. 8: 810 and 812) to drive the zero bit to the low logic level.
Claims 6-8, 12, 17-18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Mehta et al. (U.S. 2018/0166129 – of record; “Mehta”), in view of Houston (US 20060274587), and further in view of Yu et al. (U.S. 2020/0020386 – of record; “Yu”).
Regarding claim 6, Mehta and Houston combined disclose the limitations of claim 5,
As applied, Mehta further discloses further comprising:
a write driver (Fig. 2: 210, but also see Fig. 8).
Mehta shows their write driver (Fig. 2: 210 Write Driver) as a box with two inputs (Fig. 2: 108 and 210 Write Data and Write Clock) and one output connected to the multiplexer that leads to the bit lines. Mehta, however, does not illustrate in Figure 2 the specific circuitry of their write driver.
In this regard, Mehta and Houston are silent to the details of their write driver including, as claimed, a first logic gate, performing a first logic operation on the input data and a select signal to generate a zero-bit signal so as to turn on the corresponding one of the pair of pass transistors for coupling the zero bit to the ground; and a second logic gate, performing a second logic operation on the input data and the select signal to generate an non-zero-bit signal so as to turn on the corresponding first or second stack of pull-up transistors for charging the non-zero bit to approximately the first supply voltage; wherein the zero-bit signal is an inverse of the non-zero-bit signal.
The absence of the illustrating circuitry for the write driver in Figure 2 would motivate one skilled in the art to find suitable write driver circuitry to utilize Mehta’s invention.
Yu teaches a related SRAM memory having a write driver, that notably receives as input a clock and data, compatible with Mehta’s write driver. Additionally, Yu teaches their write driver includes a first and a second NOR logic gate (Fig. 5: 502 and 504) with two inputs (Fig. 5: CLK and Din_C) and one output connected to bit lines for SRAM. When Yu’s write driver is implemented as the circuitry for Mehta’s write driver, Yu’s NOR gate (e.g., Fig. 5: 502) would perform a first logic operation (i.e., logic NOR) on the input data (e.g., Fig. 5: Din_C) and a select signal (Fig. 5: CLK) to generate a zero-bit signal (e.g., signal controlling gate of 503) so as to turn on the corresponding one of the pair of pass transistors for coupling the zero bit to the ground (e.g., Fig. 5: 503 couples to ground on that signal); and a second logic gate (e.g., Fig. 5: 504), performing a second logic operation (i.e., logic NOR) on the input data (e.g., Fig. 5: Din_T) and the select signal (Fig. 5: CLK) to generate an non-zero-bit signal (e.g., output that controls gate of 505) so as to turn on the corresponding first or second stack of pull-up transistors for charging the non-zero bit to approximately the first supply voltage (see e.g.,. Fig. 5: 422, which pulls up when transistor 505 is pulled-down); wherein the zero-bit signal is an inverse of the non-zero-bit signal (note the outputs when CLK = “0” will result in the NORs’ output to be dependent upon Din_C/Din_T, which are complementary, meaning signals generated by the NORs are complementary, or “inverse” as claimed).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the SRAM write circuit of Mehta as improved by Houston's dual-rail voltage configuration to include a write driver comprising first and second logic gates that generate complementary zero-bit and non-zero-bit signals as taught by Yu. Doing so would provide a simple, reliable and area-efficient means of generating the complementary control signals needed to coordinate the multiplexer which is a well-known and predictable design choice in SRAM write circuitry to ensure proper timing and avoid contention.
Regarding claim 7: Mehta, Houston and Yu combine to disclose the limitations with of claim 6.
As applied, Yu further discloses wherein the first stack of pull-up transistors comprises:
a first transistor, coupled to the first supply voltage and controlled by the non- zero-bit signal (Fig 5: 502 and 506); and
a second transistor (Fig 5: 502 and 506), coupled between the first transistor and the non-zero bit and controlled by the zero bit;
wherein the second stack of pull-up transistors comprises:
a third transistor, coupled to the first supply voltage and controlled by the zero-bit signal (Fig 5: 502 and 506); and
a fourth transistor, coupled between the third transistor and the zero bit and controlled by the non-zero bit (Fig 5: 502 and 506);
wherein the first transistor and the second transistor are turned on to drive the non-zero bit to the high logic level;
wherein the third transistor is turned off based on the zero-bit signal.
It is noted that the circuit described in claim 7 is well known in the art as being equivalent to a NOR logic gate (Fig. 5: 502 and 504).
Regarding claim 8, Mehta, Houston and Yu combine to disclose the limitations with of claim 6.
As applied, Yu further discloses wherein the pair of pass transistors (Fig. 5: 503 and 505) select the zero bit coupled to the ground based on the zero-bit signal.
Regarding claim 12, Mehta and Houston disclose the limitations of claim 11.
As applied, Mehta further discloses wherein the pull-up circuit (Fig. 8: 814) further comprises:
a pair of pull-up transistors (Fig. 8: 806 and 808), wherein each of the pair of pull-up transistors is coupled to different one of the pair of bit lines; and
wherein one of the pair of pull-up transistors is configured to charge the non- zero bit to approximately the first supply voltage (Fig. 806 and 808) based on a zero-bit signal and the other of the pair of pull-up transistors is turned off;
wherein the write driver configured to drive the zero bit to the low logic level based on the zero-bit signal (Fig 8: 810 and 812).
Mehta is silent with respect to a pair of cross-pullup transistors, wherein each of the pair of cross-pullup transistors is coupled to different one of the pair of bit lines;
wherein one of the pair of cross-pullup transistors is configured to charge the non-zero bit to approximately the first supply voltage based on the zero bit and the other of the pair of cross-pullup transistors is turned off;
However, Yu teaches a pair of cross-pullup transistors (Fig. 422 and 424), wherein each of the pair of cross-pullup transistors is coupled to different one of the pair of bit lines;
wherein one of the pair of cross-pullup transistors is configured to charge the non-zero bit to approximately the first supply voltage based on the zero bit and the other of the pair of cross-pullup transistors is turned off (Fig. 422 and 424);
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to modify the SRAM write circuit resulting in the combination of Mehta and Houston to further include the specific pull-up circuit structure having both signal-controlled pull-up transistors and cross-pullup transistors as suggested by the circuit techniques disclosed by Yu. Doing so would improve the speed and robustness of charging the non-zero bit line during a differential write.
Regarding claim 17, Mehta and Houston combined disclose the limitations of claim 16.
As applied, Mehta further discloses coupling the zero bit to the ground according to the zero-bit signal (Fig. 8: 810 and 812);
charging the non-zero bit with the first supply voltage according to the nonzero-bit signal (Fig. 8: 806 and 808); wherein the zero-bit signal is an inverse of the non-zero-bit signal.
wherein the zero-bit signal is an inverse of the non-zero-bit signal (Fig. 8: 222 and 224).
Mehta (Fig. 2: 210 Write Driver) provides a description of a write driver with two inputs (Fig. 2: 108 and 210 Write Data and Write Clock) and one output connected to the multiplexer that leads to the bit lines. Mehta does not provide a detailed description of the implementation of the write driver in Figure 2. The absence of the detailed description of the write driver in Mehta would motivate one skilled in the art to find a circuit to utilize the invention.
Mehta shows their write driver (Fig. 2: 210 Write Driver) as a box with two inputs (Fig. 2: 108 and 210 Write Data and Write Clock) and one output connected to the multiplexer that leads to the bit lines. Mehta, however, does not illustrate in Figure 2 the specific circuitry of their write driver.
In this regard, Mehta is silent to the details of their write driver including, as claimed, performing (by an unclaimed first logic gate) a first logic operation on the input data and a select signal to generate a zero-bit signal; coupling the zero bit to ground according to the zero-bit signal; and performing (by an unclaimed a second logic gate) a second logic operation on the input data and the select signal to generate an non-zero-bit signal; charging (by unclaimed first or second stack of pull-up transistors) the non-zero bit to approximately the first supply voltage; wherein the zero-bit signal is an inverse of the non-zero-bit signal.
The absence of the illustrating circuitry for the write driver in Figure 2 would motivate one skilled in the art to find suitable write driver circuitry to utilize Mehta’s invention.
Yu teaches a related SRAM memory having a write driver, that notably receives as input a clock and data, compatible with Mehta’s write driver. Additionally, Yu teaches their write driver includes a first and a second NOR logic gate (Fig. 5: 502 and 504) with two inputs (Fig. 5: CLK and Din_C) and one output connected to bit lines for SRAM. When Yu’s write driver is implemented as the circuitry for Mehta’s write driver, Yu’s NOR gate (e.g., Fig. 5: 502) would perform a first logic operation (i.e., logic NOR) on the input data (e.g., Fig. 5: Din_C) and a select signal (Fig. 5: CLK) to generate a zero-bit signal (e.g., signal controlling gate of 503) so as to turn on the corresponding one of the pair of pass transistors for coupling the zero bit to the ground (e.g., Fig. 5: 503 couples to ground on that signal); and a second logic gate (e.g., Fig. 5: 504), performing a second logic operation (i.e., logic NOR) on the input data (e.g., Fig. 5: Din_T) and the select signal (Fig. 5: CLK) to generate an non-zero-bit signal (e.g., output that controls gate of 505) so as to turn on the corresponding first or second stack of pull-up transistors for charging the non-zero bit to approximately the first supply voltage (see e.g.,. Fig. 5: 422, which pulls up when transistor 505 is pulled-down); wherein the zero-bit signal is an inverse of the non-zero-bit signal (note the outputs when CLK = “0” will result in the NORs’ output to be dependent upon Din_C/Din_T, which are complementary, meaning signals generated by the NORs are complementary, or “inverse” as claimed).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the SRAM write circuit of Mehta as improved by Houston's dual-rail voltage configuration to include a write driver comprising first and second logic gates that generate complementary zero-bit and non-zero-bit signals as taught by Yu. Doing so would provide a simple, reliable and area-efficient means of generating the complementary control signals needed to coordinate the multiplexer which is a well-known and predictable design choice in SRAM write circuitry to ensure proper timing and avoid contention.
Regarding claim 18, Mehta, Houston and Yu combined disclose the limitations of claim 17.
As applied, Yu further discloses wherein the non-zero bit is driven to the high logic level by a stack of pull-up transistors (Fig. 5: 422 and 503), wherein the step of selecting which one of the pair of bit lines is the non-zero bit line driven to the high logic level further comprises: turning on the stack of pull-up transistors based on the zero bit and the non- zero-bit signal(Fig. 5: 502); and
charging the non-zero bit to approximately the first supply voltage due to the stack of pull-up transistors being turned on (Fig 5: 502, 503 and 422).
Regarding claim 20, Mehta, Houston and Yu combined disclose the limitations of claim 19.
As applied, Mehta further discloses wherein the step of selecting (Fig. 1, but also see Fig. 8) which one of the pair of bit lines is the non-zero bit line driven to the high logic level further comprises:
generating a non-zero-bit signal based on the input data (Fig. 8: 210) by using the write driver, wherein the non-zero-bit signal is an inverse of the zero-bit signal;
providing the non-zero-bit signal to the non-zero bit (Fig. 8: 810 and 812) to drive the non-zero bit to the high logic level;
charging the non-zero bit to approximately the first supply voltage by using a pull-up transistor (Fig. 8: 806 and 808) according to the zero-bit signal;
Mehta is silent on charging the non-zero bit to approximately the first supply voltage by a cross-pullup transistor according to the zero bit.
Yu teaches charging the non-zero bit to approximately the first supply voltage by a cross-pullup transistor (Fig. 5: 422 and 424, but also see Spec. para. [0036 and 0037]) according to the zero bit.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Yu to modify the method of performing a write operation as taught by Mehta and Houston such that charging the non-zero bit by a cross-pullup transistor reinforces the logic high voltage on the non-zero bit. Doing so would be a predictable variation for enhancing write performance and robustness while retaining the power benefits and amounts to using well-known techniques (cross-controlled pull-up assist) in a predictable manner to improve the write method.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Mehta et al. (U.S. 2018/0166129 – of record; “Mehta”), in view of Houston (US 20060274587), and further in view of Lee et al. (U.S. 2021/0134354 – of record; “Lee”).
Regarding claim 9, Mehta and Houston combined discloses the limitations of claim 1.
Mehta and Houston are silent with respect to the negative boost circuit.
However, Lee teaches further comprising a negative boost circuit, coupled between the multiplexer and the ground (Fig. 3: 330 but also see Fig. 4);
wherein when the negative boost circuit is turned on, the negative boost circuit couples the multiplexer to the ground (Fig. 3: 330 but also see Fig. 4);
wherein when the negative boost circuit is turned off, the negative boost circuit provides a negative voltage to the multiplexer (Fig. 3: 330 but also see Fig. 4).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to modify the SRAM write circuit resulting from the combination of Mehta and Houston to further include a negative boost circuit coupled between the multiplexer and ground that provides a negative voltage to the multiplexer when it is turned off as taught by Lee. Doing so would improve write margin and reliability, particularly when operating at reduced supply voltages.
Response to Arguments
Applicant's arguments have been fully considered but they are not persuasive.
Claims 1 and 13 were amended to include the limitation that the memory cell is supplied with a second voltage that exceeds the first supply voltage used to precharge the bit lines. This limitation was not present in the claims previously rejected. Mehta does not disclose or suggest distinct supply voltages. Accordingly, the previous anticipation rejection has been withdrawn.
The amended claims are now rejected under 35 U.S.C. § 103 over Mehta in view of Houston. This constitutes a new ground of rejection necessitated by Applicant's amendment. Houston teaches precharging bit lines to a voltage substantially lower than the word line driver and memory array voltage.
Rejection of all remaining dependent claims are maintained.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to James S. Wells whose telephone number is (703)756-1413. The examiner can normally be reached M-F 8:30-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander Sofocleous can be reached at (571)272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/James S. Wells/Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825
Prosecution Insights