DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 21-23 and 25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (PG Pub. No. US 2020/0020768 A1).
Regarding claim 21, Lee teaches a method of manufacturing a semiconductor device (fig. 13 among others), comprising:
forming a stack of semiconductor layers (¶ 0023: 14L) and sacrificial layers (12L) alternately arranged over a substrate along a vertical direction (fig. 1: 14L/12L alternately arranged over substrate 10/11 along a vertical direction);
patterning the stack to form a stacking structure on the substrate (¶ 0028: patterning process provides patterned stack S1 formed on 10/11), the stacking structure extending along a first horizontal direction (fig. 2: S1 extends at least in the horizontal direction);
disposing a sacrificial gate structure (¶ 0032: 16) on the substrate (fig. 2: 16 disposed on 10), wherein the sacrificial gate structure is extending along a second horizontal direction intersected with the first horizontal direction and covers a portion of the stacking structure (¶ 0032 & figs. 2-3: each sacrificial gate structure 16 formed on first and second sides of stack S1, such that 16 extend in second horizontal direction);
removing portions of the stacking structure not overlapped with the sacrificial gate structure (¶ 0040 & fig. 3: portions of S1 not overlapped with 16 are removed);
disposing source/drain regions (¶ 0047: 22) at opposite sides of the sacrificial gate structure (figs. 5, 7: 22 disposed at opposite sides of 16), the semiconductor layers in the remained stacking structure connecting between the source/drain regions (figs. 5, 7: portions 14P of layers 14L connected between source/drain regions 22);
removing the sacrificial gate structure and rest of the sacrificial layers (¶ 0057: 16 and remaining portions 12P of layers 12L removed) to form a cavity (removal of 16/12R forms gate cavity GC) accessibly revealing the semiconductor layers in the remained stacking structure (fig. 8: GC accessibly reveals 14P);
forming a semiconductor material (¶ 0058: Ge-containing layer 28) to cover the semiconductor layers in the remained stacking structure being accessibly revealed by the cavity (fig. 9: 28 covers 14P revealed by GC);
performing a thermal process to completely transform the semiconductor material into a Si-containing layer and a Ge-containing layer (¶¶ 0060-0061: condensation anneal transforms entire material 14P into Si-containing layer 30 and Ge-containing layer 14P’/14E), wherein the Si-containing layer is disposed over the semiconductor layers being accessibly revealed by the cavity (fig. 10: 30 disposed over 14P’ revealed by GC), and the Ge-containing layer is interposed between the Si-containing layer and the semiconductor layers in the remained stacking structure (fig. 10: 14P’ interposed between 30 and non-converted portions 14E);
removing the Si-containing layer (¶ 0065: SiO2 layer 30 removed); and
forming a gate structure (¶ 0065: 32/34) in the cavity and over the remained stacking structure (fig. 12: 32/34 formed in GC and over 14P’/14E).
Regarding claim 22, Lee teaches the method of claim 21, wherein the cavity further accessibly reveals the substrate overlapped with the remained stacking structure (Lee, fig. 8: top surface of 10/11 revealed by cavity GC), wherein:
forming the semiconductor material to cover the semiconductor layers in the remained stacking structure being accessibly revealed by the cavity further comprises forming the semiconductor material to cover the substrate overlapped with the remained stacking structure being accessibly revealed by the cavity (Lee, fig. 9: Ge-containing layer 28 covers exposed portion of 10/11 overlapped with NS1 and exposed by GC), and
the Si-containing layer is further disposed over the substrate overlapped with the remained stacking structure being accessibly revealed by the cavity (Lee, fig. 10: 30 disposed over exposed surface of 10/11), and the Ge-containing layer is further interposed between the Si-containing layer and the substrate overlapped with the remained stacking structure being accessibly revealed by the cavity (Lee, fig. 10: 14P’ interposed between at least a portion of 30 and 10/11 exposed by GC).
Regarding claim 23, Lee teaches the method of claim 21, further comprising:
globally disposing a dielectric layer (Lee, ¶ 0038: dielectric spacer material) over the substrate to cover the sacrificial gate structure and the stacking structure (Lee, ¶ 0038 & fig. 2: 18 disposed over 10/11 to cover at least side surfaces of 16 and S1); and
patterning the dielectric layer to form a pair of gate spacers at the two opposite sides of the sacrificial gate structure (Lee, ¶¶ 0038-0039 & fig. 2: 18 formed by pattern etching dielectric spacer material),
wherein:
removing portions of the stacking structure not overlapped with the sacrificial gate structure comprises removing portions of the stacking structure not overlapped with the sacrificial gate structure and the pair of gate spacers (Lee, fig. 3: portions of S1 not covered by 16 and 18 removed).
Regarding claim 25, Lee teaches the method of claim 21, prior to disposing the source/drain regions and after removing the portions of the stacking structure not overlapped with the sacrificial gate structure, further comprising:
laterally recessing the sacrificial layers included in the remained stacking structure to form a plurality of first recesses (Lee, ¶ 0040: each sacrificial SiGe nanosheet 12L laterally recessed to provide a recessed sacrificial SiGe nanosheet 12R); and
forming inner spacers (Lee, ¶ 0040: 20) in the plurality of first recesses (Lee, fig. 3: 20 formed in recessed adjacent to 12R).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3, 5 and 8-13 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Cheng et al. (US 2017/0365662 A1).
Regarding claim 1, Lee teaches a method of manufacturing a semiconductor device (fig. 13 among others), comprising:
forming a stack of semiconductor layers (¶ 0023: 14L) and sacrificial layers (12L) alternately arranged over a substrate along a vertical direction (fig. 1: 14L/12L alternately arranged over substrate 10/11 along a vertical direction);
patterning the stack to form a stacking structure on the substrate (¶ 0028: patterning process provides patterned stack S1 formed on 10/11), the stacking structure extending along a first horizontal direction (fig. 2: S1 extends at least in the horizontal direction);
disposing a sacrificial gate structure (¶ 0032: 16) on the substrate (fig. 2: 16 disposed on 10), wherein the sacrificial gate structure is extending along a second horizontal direction intersected with the first horizontal direction and covers a portion of the stacking structure (¶ 0032 & figs. 2-3: each sacrificial gate structure 16 formed on first and second sides of stack S1, such that 16 extend in second horizontal direction);
removing portions of the stacking structure not overlapped with the sacrificial gate structure (¶ 0040 & fig. 3: portions of S1 not overlapped with 16 are removed);
disposing source/drain regions (¶ 0047: 22) at opposite sides of the sacrificial gate structure (figs. 5, 7: 22 disposed at opposite sides of 16), the semiconductor layers in the remained stacking structure connecting between the source/drain regions (figs. 5, 7: portions 14P of layers 14L connected between source/drain regions 22);
removing the sacrificial gate structure and rest of the sacrificial layers (¶ 0057: 16 and remaining portions 12P of layers 12L removed) to form a cavity (removal of 16/12R forms gate cavity GC) accessibly revealing the semiconductor layers in the remained stacking structure (fig. 8: GC accessibly reveals 14P);
forming a semiconductor material (¶ 0058: Ge-containing layer 28) to cover the semiconductor layers in the remained stacking structure being accessibly revealed by the cavity (fig. 9: 28 covers 14P revealed by GC);
performing a thermal process to transform the semiconductor material into a Si-containing layer and a Ge-containing layer (¶¶ 0060-0061: condensation anneal transfers Ge from 28 into 14P’, and forms SiO2 layer 30), wherein the Si-containing layer is disposed over the semiconductor layers being accessibly revealed by the cavity (fig. 10: 30 disposed over 14P’ revealed by GC), and the Ge-containing layer is interposed between the Si-containing layer and the semiconductor layers in the remained stacking structure (fig. 10: 14P’ interposed between 30 and non-converted portions 14E);
removing the Si-containing layer (¶ 0065: SiO2 layer 30 removed); and
forming a gate structure (¶ 0065: 32/34) in the cavity and over the remained stacking structure (fig. 12: 32/34 formed in GC and over 14P’/14E).
Lee does not teach the Ge-containing layer is interposed between the Si-containing layer and the semiconductor layers in the remained stacking structure along the vertical direction.
Cheng teaches a method of forming a semiconductor device, including a Ge-containing layer (¶ 0046: 16) interposed between an Si-containing layer (¶ 0046: 30) and a semiconductor layer along a vertical direction (fig. 6: 16 vertically interposed between portion of 30 and Si layer 14 or 18).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the method of Lee with the vertical stacking of Cheng, as a means to provide a space efficient and high performing transistor device (Cheng, ¶ 0030).
Regarding claim 2, Lee in view of Cheng teaches the method of claim 1, wherein the cavity further accessibly reveals the substrate overlapped with the remained stacking structure (Lee, fig. 8: top surface of 10/11 revealed by cavity GC), wherein:
forming the semiconductor material to cover the semiconductor layers in the remained stacking structure being accessibly revealed by the cavity further comprises forming the semiconductor material to cover the substrate overlapped with the remained stacking structure being accessibly revealed by the cavity (Lee, fig. 9: Ge-containing layer 28 covers exposed portion of 10/11 overlapped with NS1 and exposed by GC), and
the Si-containing layer is further disposed over the substrate overlapped with the remained stacking structure being accessibly revealed by the cavity (Lee, fig. 10: 30 disposed over exposed surface of 10/11), and the Ge-containing layer is further interposed between the Si-containing layer and the substrate overlapped with the remained stacking structure being accessibly revealed by the cavity (Lee, fig. 10: 14P’ interposed between at least a portion of 30 and 10/11 exposed by GC).
Regarding claim 3, Lee in view of Cheng teaches the method of claim 1, further comprising:
globally disposing a dielectric layer (Lee, ¶ 0038: dielectric spacer material) over the substrate to cover the sacrificial gate structure and the stacking structure (Lee, ¶ 0038 & fig. 2: 18 disposed over 10/11 to cover at least side surfaces of 16 and S1); and
patterning the dielectric layer to form a pair of gate spacers at the two opposite sides of the sacrificial gate structure (Lee, ¶¶ 0038-0039 & fig. 2: 18 formed by pattern etching dielectric spacer material),
wherein:
removing portions of the stacking structure not overlapped with the sacrificial gate structure comprises removing portions of the stacking structure not overlapped with the sacrificial gate structure and the pair of gate spacers (Lee, fig. 3: portions of S1 not covered by 16 and 18 removed).
Regarding claim 5, Lee in view of Cheng teaches the method of claim 1, prior to disposing the source/drain regions and after removing the portions of the stacking structure not overlapped with the sacrificial gate structure, further comprising:
laterally recessing the sacrificial layers included in the remained stacking structure to form a plurality of first recesses (Lee, ¶ 0040: each sacrificial SiGe nanosheet 12L laterally recessed to provide a recessed sacrificial SiGe nanosheet 12R); and
forming inner spacers (Lee, ¶ 0040: 20) in the plurality of first recesses (Lee, fig. 3: 20 formed in recessed adjacent to 12R).
Regarding claim 8, Lee in view of Cheng teaches the method of claim 1, prior to forming the semiconductor material to cover the semiconductor layers and after removing the sacrificial gate structure and the rest of the sacrificial layers, further comprising:
trimming the semiconductor layers (Lee, ¶ 0066: 14P exposed to etchant, equivalent to trimming process disclosed in ¶ 0066 of the instant specification).
Regarding claim 9, Lee teaches a method of manufacturing a semiconductor device (fig. 13), comprising:
forming a plurality of transistors (fig. 13: at least two nFET and/or two pFET), comprising:
forming a stack of first semiconductor layers (¶ 0023: 12L) and second semiconductor layers (14L) alternately arranged along a vertical direction (fig. 1: 12L/14L alternately arranged in a vertical direction);
patterning the stack (¶ 0028) to form a plurality of stacking structures (plurality of S1 and/or S2), the plurality of stacking structures extending along a first horizontal direction (fig. 2: S1 and/or S2 extend along a horizontal direction);
disposing a plurality of dummy gate structures (¶ 9932: 16) on the plurality of stacking structures (fig. 2: 16 disposed on S1 and/or S2 patterns), wherein the plurality of dummy gate structures extend along a second horizontal direction intersected with the first horizontal direction and cover portions of the plurality of stacking structures (¶ 0032: 16 formed on sides and top of S1 and S2; not illustrated);
removing portions of the plurality of stacking structures not overlapped with the plurality of dummy gate structures (¶ 0040 & fig. 3: portions of S1 and S2 not overlapped with 16 are removed to form respective nanosheet stacks NS1 and NS2);
laterally recessing the first semiconductor layers to form a plurality of first recesses (¶ 0040: 12L recessed to form gaps);
forming inner spacers (¶ 0040: 20) in the plurality of first recesses, the inner spacers respectively connecting two adjacent second semiconductor layers in the vertical direction (fig. 3: 20 formed in gaps to connect 14L/14P in vertical direction);
disposing source/drain regions (¶ 0047: 22) at opposite sides of the plurality of the dummy gate structures (fig. 4: 22 disposed at opposite sides of 16), the second semiconductor layers connecting between the source/drain regions in the first horizontal direction (fig. 4: 14P connect between 22);
removing the plurality of dummy gate structures and rest of the first semiconductor layers (¶ 0057: 16 and 12R removed) to form a plurality of cavities (GC) exposing the second semiconductor layers (fig. 8: GC exposes remaining portions 14P of semiconductor layers 14L);
selectively forming a layer of Ge material (¶ 0058: Ge-containing layer 28) to cover the second semiconductor layers exposed by the plurality of cavities (fig. 9: 28 covers 14P exposed by GC);
treating the layer of Ge material (¶ 0060: 28 exposed to thermal treatment process) to form a Si-containing layer (30) and a Ge-containing layer (14P’) over the second semiconductor layers (fig. 10: 30/14P’ disposed over at least non-converted portions 14E), wherein the Ge-containing layer is interposed between the Si-containing layer and the second semiconductor layers (fig. 10: at least a portion of 14P’ diagonally interposed between 30 and 14E);
removing the Si-containing layer (¶ 0065: 30 removed); and
forming a plurality of gate structures (¶ 0066: 32/34) in the cavities and over the plurality of stacking structures (fig. 12: 32/34 formed in GC and over 14P’/14E); and
forming an interconnection structure (¶ 0075: 36, 38 and/or 40) over the plurality of transistors (fig. 13: 36/38/40 formed over nFET and/or pFET), wherein the plurality of transistors are electrically coupled through the interconnection structure (at least one nFET transistor and one pFET transistor electrically coupled through 36, 38 and/or 40).
Lee does not teach the Ge-containing layer is interposed between the Si-containing layer and the semiconductor layers in the remained stacking structure along the vertical direction, the Ge-containing layer comprises SiGe, or the thermal treatment process includes oxidation.
Cheng teaches a method of forming a semiconductor device, including a Ge-containing layer (¶ 0046: 16 and/or 33) interposed between an Si-containing layer (¶ 0046: 30) and a semiconductor layer along a vertical direction (fig. 6: 16/33 vertically interposed between a portion of 30 and Si layer 14 or 18), the Ge-containing layer comprises SiGe (¶ 0051: at least portion 33 includes SiGe), and the thermal treatment process includes oxidation (¶ 0051: condensation includes an oxidizing process).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the method of Lee with the vertical stacking of Cheng, as a means to provide a space efficient and high performing transistor device (Cheng, ¶ 0030).
Regarding claim 10, Lee in view of Cheng teaches the method of claim 9, wherein oxidizing the layer of SiGe material to form the Si-containing layer and the Ge-containing layer over the second semiconductor layers comprises oxidizing the layer of SiGe material to form a SiO2 layer (Lee, ¶ 0061: 30 and/or Shah, ¶ 0061: 136) and a Ge layer (Lee, ¶ 0061: 14P’ and/or Shah, ¶ 0045: 134) over the second semiconductor layers (Lee, fig. 10: at least portions of 30/14P’ formed over non-converted portions 14E), wherein the Ge layer is interposed between the SiO2 layer and the second semiconductor layers (Lee, fig. 10: 14P’ at least diagonally interposed between 30 and 14E).
Regarding claim 11, Lee in view of Cheng teaches the method of claim 9, wherein:
selectively forming the layer of SiGe material to cover the second semiconductor layers exposed by the plurality of cavities (Lee, fig. 9: 28, as modified to include SiGe of Shah, covers 14P exposed by GC) comprises forming a Si1-WGeW layer by selective epitaxial growth (Cheng, ¶ 0046: 16 comprises SiGe with 5-80* Ge, and formed by epitaxial growth) to cover the second semiconductor layers (Lee, fig. 9: 28 covers 14P), and w is in a range of about 0.1 to about 0.5 (Cheng, ¶ 0046: 20% germanium content), and
the Ge-containing layer is formed to have a composition of Si1-vGev (Cheng, ¶ 0051: 33 comprises SiGe).
Lee in view of Cheng as applied to claim 9 above does not explicitly teach v is about twice of w.
However, Cheng does teach the composition of Ge is a results-effective variable (¶ 0051: The size of the dot 32 can be controlled by the concentration of Ge in the layer 16; Portions 33 of layers 14 and 18 may include SiGe with the concentration depending on the condensation process).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to adjust the germanium content in the Ge-containing layer of Lee in view of Cheng, as a means to optimize the size and/or concentration of condensed germanium (Cheng, ¶ 0051: Ge content in 16 and/or 33, similar to 14P of Lee), optimizing electrical properties of the device channel (16 of Cheng, 14P of Lee).
Regarding claim 12, Lee in view of Cheng teaches the method of claim 9, prior to selectively forming the layer of SiGe material to cover the second semiconductor layers exposed by the plurality of cavities and after removing the plurality of dummy gate structures and rest of the first semiconductor layers, further comprising:
trimming the second semiconductor layers (Lee, ¶ 0066: 14P exposed to etchant, equivalent to trimming process disclosed in ¶ 0066 of the instant specification), wherein a thickness of a central portion of each of the second semiconductor layers is less than a thickness of ends portions thereof (Lee, fig. 12: resulting thickness of 14P’ less than thickness of 14E).
Regarding claim 13, Lee in view of Cheng teaches the method of claim 9, wherein removing the Si-containing layer comprising performing a selective etching process to removing only the Si-containing layer (Lee, ¶ 0066: 30 removed by a process selective to silicon dioxide).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Cheng as applied to claim 1 above, and further in view of Kao et al. (PG Pub. No. US 2022/0328659 A1).
Regarding claim 4, Lee in view of Cheng teaches the method of claim 1, prior to removing the sacrificial gate structure and the rest of the sacrificial layers, further comprising:
conformally forming an etching stop layer (Lee, ¶ 0052: 24) over the source/drain regions (Lee, fig. 6: 24 formed over 22).
Lee in view of Cheng fails to teach the method further comprising:
forming the etching stop layer over the sacrificial gate structure;
forming an isolation structure over the substrate to cover the etching stop layer, the source/drain regions, and the sacrificial gate structure; and
performing a planarization process to accessibly reveal the sacrificial gate structure.
Kao teaches a method comprising:
forming an etching stop layer (¶ 0044: 190) over a source/drain region and a sacrificial gate structure (figs. 9A-9C: 190 formed over source/drain 180 and sacrificial gate 162/164);
forming an isolation structure (¶ 0044: 195) over the substrate to cover the etching stop layer, the source/drain regions, and the sacrificial gate structure (figs. 9A-9C: 195 covers 190, 180 and 162/164); and
performing a planarization process (¶ 0045: CMP) to accessibly reveal the sacrificial gate structure (fig. 9C: planarization reveals 162/164).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the method of Lee in view of Cheng with that of Kao, as a means to facilitate formation of source/drain contact structures (Koa, ¶ 0050: 240) without damaging the source/drain regions, and/or form low-resistance metal alloy layers (Kao, ¶ 0050).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Cheng as applied to claim 1 above, and further in view of Shah et al. (PG Pub. No. US 2011/0147697 A1).
Regarding claim 6, Lee in view of Cheng teaches the method of claim 1, wherein forming the semiconductor material to cover the semiconductor layers in the remained stacking structure being accessibly revealed by the cavity comprises forming a Ge-containing layer (Lee, ¶ 0058: 28 comprises germanium) by selective epitaxial growth (Lee, ¶ 0059: 28 formed by an epitaxial process such as ALD) to cover the semiconductor layers in the remained stacking structure being accessibly revealed by the cavity (Lee, fig. 9: 28 formed to cover remaining semiconductor layer portions 14P revied by cavity GC).
Lee in view of Cheng fails to teach the Ge-containing layer comprises Si1-WGeW layer, and w is in a range of about 0.1 to about 0.5.
Shah teaches a method including forming a Si1-WGeW layer by selective epitaxial grown to cover exposed semiconductor structures (¶ 0036 & fig. 8: silicon germanium alloy 132 epitaxially grown selectively on 112), and w is in a range of about 0.05 to about 0.35 (¶ 0036: 132 may have a chemical formula of Si1-xGex, where 0.05 < x <0.35).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the Ge-containing layer of Lee in view of Cheng with the material of Shah, as a means to optimize the germanium content in the resulting nanowire/channel structure (Shah, ¶ 0044: Ge content in nanowire 134, similar to 14P of Lee).
Furthermore, it has been held that where the claimed ranges overlap or lie inside ranges disclosed by the prior art, a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). In the instant case, the claimed range of “about 0.1 to about 0.5” overlaps the range disclosed by Shah (0.05 < x <0.35).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Cheng as applied to claim 1 above, and further in view of Chao et al. (PG Pub. No. US 2019/0267463 A1).
Regarding claim 7, Lee in view of Cheng teaches the method of claim 1, wherein performing the thermal process comprises performing a treatment under a temperature being less than or substantially equal to 600°C (Lee, ¶ 0061: thermal process includes temperature of 350° C).
Lee in view of Cheng does not teach the thermal process comprises an oxidation treatment.
Chao teaches a performing a treatment process on a semiconductor layer (¶ 0030: germanium condensation, similar to that of Lee), the treatment including a thermal oxidation under a temperature being less than or substantially equal to 600° C (¶ 0030: condensation includes an oxidation process between about 400° C and 600° C).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the thermal treatment of Lee in view of Cheng with an oxidation at a temperature of less than or substantially equal to 600° C, as a means to avoid oxidation of the semiconductor layers (Chao, ¶ 0030: low temperature minimized oxidation of channel layers 104, similar to 14L/14P of Lee).
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Lee as applied to claim 21 above, and further in view of Kao.
Regarding claim 4, Lee teaches the method of claim 1, prior to removing the sacrificial gate structure and the rest of the sacrificial layers, further comprising:
conformally forming an etching stop layer (¶ 0052: 24) over the source/drain regions (fig. 6: 24 formed over 22).
Lee fails to teach the method further comprising:
forming the etching stop layer over the sacrificial gate structure;
forming an isolation structure over the substrate to cover the etching stop layer, the source/drain regions, and the sacrificial gate structure; and
performing a planarization process to accessibly reveal the sacrificial gate structure.
Kao teaches a method comprising:
forming an etching stop layer (¶ 0044: 190) over a source/drain region and a sacrificial gate structure (figs. 9A-9C: 190 formed over source/drain 180 and sacrificial gate 162/164);
forming an isolation structure (¶ 0044: 195) over the substrate to cover the etching stop layer, the source/drain regions, and the sacrificial gate structure (figs. 9A-9C: 195 covers 190, 180 and 162/164); and
performing a planarization process (¶ 0045: CMP) to accessibly reveal the sacrificial gate structure (fig. 9C: planarization reveals 162/164).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the method of Lee with that of Kao, as a means to facilitate formation of source/drain contact structures (Koa, ¶ 0050: 240) without damaging the source/drain regions, and/or form low-resistance metal alloy layers (Kao, ¶ 0050).
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Lee as applied to claim 21 above, and further in view of Shah.
Regarding claim 6, Lee teaches the method of claim 21, wherein forming the semiconductor material to cover the semiconductor layers in the remained stacking structure being accessibly revealed by the cavity comprises forming a Ge-containing layer (¶ 0058: 28 comprises germanium) by selective epitaxial growth (¶ 0059: 28 formed by an epitaxial process such as ALD) to cover the semiconductor layers in the remained stacking structure being accessibly revealed by the cavity (fig. 9: 28 formed to cover remaining semiconductor layer portions 14P revied by cavity GC).
Lee fails to teach the Ge-containing layer comprises Si1-WGeW layer, and w is in a range of about 0.1 to about 0.5.
Shah teaches a method including forming a Si1-WGeW layer by selective epitaxial grown to cover exposed semiconductor structures (¶ 0036 & fig. 8: silicon germanium alloy 132 epitaxially grown selectively on 112), and w is in a range of about 0.05 to about 0.35 (¶ 0036: 132 may have a chemical formula of Si1-xGex, where 0.05 < x <0.35).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the Ge-containing layer of Lee with the material of Shah, as a means to optimize the germanium content in the resulting nanowire/channel structure (Shah, ¶ 0044: Ge content in nanowire 134, similar to 14P of Lee).
Furthermore, it has been held that where the claimed ranges overlap or lie inside ranges disclosed by the prior art, a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). In the instant case, the claimed range of “about 0.1 to about 0.5” overlaps the range disclosed by Shah (0.05 < x <0.35).
Allowable Subject Matter
Claim 27 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art fails to teach or clearly suggest the limitations
“prior to forming the semiconductor material to cover the semiconductor layers and after removing the sacrificial gate structure and the rest of the sacrificial layers, further comprising:
trimming the semiconductor layers” as recited in claim 27.
Lee teaches removing a sacrificial gate structure and remaining sacrificial layers, and forming the semiconductor material to cover the semiconductor layers, but fails to teach trimming the semiconductor layers as required by claim 27.
Response to Arguments
Applicant’s arguments, see page 14 of the reply filed on 12/29/2025, with respect to the formal objections to the specification and claims, have been fully considered and are persuasive. Accordingly, these objections have been withdrawn.
Applicant’s arguments with respect to the 35 USC § 102 and § 103 rejections of claims 1-13 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/BRIAN TURNER/Examiner, Art Unit 2818