DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I and Species III in the reply filed on 10/6/2025 is acknowledged. Claims 1-15, 17 and 21-24 are being examined in this office action.
Drawings
The drawings are objected to because:
In Figs. 6B, 7B, 8B and 9B, the horizontal axis direction should be “Y-axis” and not “X-axis”.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 5-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lai et al. (US 2023/0040387 A1).
Re Claim 1, Lai teaches a semiconductor structure (Fig. 1), comprising:
a substrate having a circuit region (200, Fig. 1, para [0018]) and a seal ring region (300, Fig. 1, para [0018]) around the circuit region (200);
first active regions (220, Fig. 2, para [0020]) of a first width (width of 220, Fig. 2) disposed in the circuit region (200);
second active regions (320+360+362+324, see Figs. 3 and 17, para [0021]) of a second width (w1, Fig. 3, para [0021]) disposed in the seal ring region (300), wherein the second width is greater than the first width (widths of the components like fins in the seal region 300 are wider than the widths of their counterparts in the circuit region 200, para [0049]);
first gate structures (240, Fig. 2, para [0020]) disposed on the first active regions (220), wherein the first gate structures (240) are longitudinally oriented to be orthogonal (see Fig. 2) with the first active regions (220); and
second gate structures (340, see Figs. 3 and 17, para [0020]) disposed on longitudinal edges of the second active regions (340 is disposed on the longitudinal inner edges of 360 and 362, Fig. 17), wherein the second gate structures (340) are longitudinally oriented to be in parallel (see Fig. 3) with the second active regions (320+360+362+324).
Re Claim 5, Lai teaches the semiconductor structure of claim 1, wherein the first active regions (220) occupy a first percentile of a first area (marked “1st area”, in annotated Fig. 2 below) in the circuit region (200), the second active regions (320+360+362+324) occupy a second percentile of a second area (marked “2nd area”, in annotated Fig. 3 below) in the seal ring region (300), and a difference between the first percentile and the second percentile is within 10% (Examiner notes that the extent of the areas that can be chosen for the calculation are not defined. Hence, one can arbitrarily define “a first area” in the circuit region (marked “a 1st area”, in annotated Fig. 2 below) and “a second area” in the seal region (marked “a 2nd area”, in annotated Fig. 3 below), such that a difference between the first percentile and the second percentile is within 10%. The claim language does not preclude this treatment).
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Re Claim 6, Lai teaches the semiconductor structure of claim 1, wherein the first gate structures (240, Fig. 2) occupy a first percentile of a first area (marked “1st gate area”, in annotated Fig. 2 below) in the circuit region (200), the second gate structures (340, Fig. 3) occupy a second percentile of a second area (marked “1st gate area”, in annotated Fig. 2 below) in the seal ring region (300), and a difference between the first percentile and the second percentile is within 10% (Examiner notes that the extent of the areas that can be chosen for the calculation are not defined. Hence, one can arbitrarily define “a first area” in the circuit region (marked “a 1st gate area”, in annotated Fig. 2 below) and “a second area” in the seal region (marked “a 2nd gate area”, in annotated Fig. 3 below), such that a difference between the first percentile and the second percentile is within 10%. The claim language does not preclude this treatment).
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Re Claim 7, Lai teaches the semiconductor structure of claim 1, further comprising:
contact structures (380, Figs. 3 and 17, para [0021]) disposed on the second active regions (320+360+362+324, Fig. 17) and completely landing on the second active regions (see Fig. 17).
Re Claim 8, Lai teaches the semiconductor structure of claim 7, wherein the contact structures (380, Figs. 3 and 17) are landing on the second active regions (320+360+362+324, Fig. 17) with margins such that longitudinal edges of each of the contact structures are within the longitudinal edges of a respective one of the second active regions (see Fig. 17).
Re Claim 9, Lai teaches the semiconductor structure of claim 1, wherein each of the second active regions (320+360+362+324, Figs. 3 and 17) is a continuous ring shape (Fig. 1) to enclose the circuit region (200), and each of the second gate structures (340, Fig. 3) is a continuous ring shape to enclose the circuit region (Fig. 1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Lai et al. (US 2023/0040387 A1).
Re Claim 4, Lai teaches the semiconductor structure of claim 1, wherein each of the second gate structures (340, Fig. 17) overlaps with a respective one of the second active regions (320+360+362+324, Fig. 17) for a width (marked “overlap-width” in annotated Fig. 17 below) measured from a respective one of the longitudinal edges (inner longitudinal edges of 360 and 362, Fig. 17) towards a centerline of the respective one of the second active regions (center of 320, Fig. 17).
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Lai does not disclose that the overlap width is between 5 nm and 15 nm.
However, Lai discloses that the widths of the gate in the seal region can be 50 nm (para [0021]), and hence the overlap width will be 50/2 = 25 nm, close to the claimed range.
It would have been obvious to one of ordinary skill in the art, at the time of invention, to optimize the overlap width and arrive at the claimed range. With respect to the limitations of the claim, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955). The optimization of the claimed width would have been obvious to one of ordinary skill in the art.
Claim 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Lai et al. (US 2023/0040387 A1), and further in view of Lai et al. (US 2023/0040287 A1, hereinafter Lai-2).
Re Claim 2, Lai teaches the semiconductor structure of claim 1, but does not explicitly disclose that a ratio of the second width over the first width ranges between 1.1 and 5.
Related art Lai-2 teaches a similar seal ring region enclosing a circuit region where the width of the active region in the seal region can be 250 nm (w1, Fig. 3, para [0029]), while the width of the active region in the circuit region can be 60 nm (2*wD + wG = 2*20 + 20 = 60 nm, Fig. 2, para [0027]), which gives a ratio of 250/60 = 4.2, within the claimed range.
It would have been obvious to one of ordinary skill in the art, at the time of invention, to optimize the ratio of the widths of the active regions in the seal region and the circuit region and arrive at the claimed range. With respect to the limitations of the claim, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955). The optimization of the claimed ratio would have been obvious to one of ordinary skill in the art.
Re Claim 3, Lai teaches the semiconductor structure of claim 1, but does not disclose that the first gate structures have a third width, and the second gate structures have a fourth width that is substantially equal to the third width.
Related art Lai-2 teaches a similar seal ring region enclosing a circuit region wherein the ratio of the width of the gate structure in the seal region (w4, Fig. 4, para [0036]) to the width of the gate structure in the circuit region (wG, Fig. 2, para [0027]) can be between 1 and 2.5 (para [0036]), satisfying the claim limitation.
It would have been obvious to one of ordinary skill in the art, at the time of invention, to optimize the ratio of the widths of the active regions in the seal region and the circuit region and arrive at the claimed limitation. With respect to the limitations of the claim, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955). The optimization of the claimed ratio would have been obvious to one of ordinary skill in the art.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Song et al. (US 2019/0385916 A1), and further in view of Knoblinger et al. (US 2007/0181942 A1).
Re Claim 11, Song teaches a semiconductor structure (Fig. 1D), comprising:
an active region (140, Fig. 1D, para [0033]) extending lengthwise in a first direction (y-axis, Fig. 1D) in a region of the semiconductor structure (see Fig. 1D);
a first gate structure (G3, Fig. 1D, para [0033]) disposed on a first edge of the active region (140, Figs. 1A and 1D), the first gate structure extending lengthwise in the first direction (y-axis, Fig. 1D) in the region of the semiconductor structure (see Fig. 1D);
a second gate structure (G1, Fig. 1D, para [0033]) disposed on a second edge of the active region (140, Figs. 1A and 1D), the second edge opposing the first edge (see Figs. 1A and 1D), the second gate structure (G1) extending lengthwise in the first direction (y-axis, Fig. 1D) in the region of the semiconductor structure (see Fig. 1D); and
Song does not disclose a contact structure completely landing on the active region, the contact structure extending lengthwise in the first direction in the region of the semiconductor structure.
However, related art, Knoblinger teaches a semiconductor structure (Fig. 2), where a contact structure (SL, Fig. 2, paras [0038] – [0039]) completely lands (contacts K, Fig. 2, para [0039]) on the active region (S12+S22+S11+S21, Fig. 2, para [0027]), and extends lengthwise in the same direction as the active region (see Fig. 2).
It would have been obvious to one of ordinary skill in the art, at the time of invention, to dispose the contact structure of Knoblinger on to the source/drain device of Song, as the contact structure will supply the necessary current to drive the transistor device of Song, resulting in a functional transistor device.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Song et al. (US 2019/0385916 A1) and Knoblinger et al. (US 2007/0181942 A1), and further in view of Yang et al. (US 2021/0280722 A1).
Re Claim 15, Song modified by Knoblinger teaches the semiconductor structure of claim 11, but does not disclose that the active region includes multiple channel members vertically stacked.
Related art, Yang teaches a FinFET transistor with multiple channels vertically stacked (145, Fig. 3, para [0026]). The gate-all-around (GAA) multi-channel FinFET provides a distinct advantage over regular FinFET devices, as GAA provides improved short channel effect, channel length reduction, gate pitch reduction, and also increase drive current with larger effective device widths (para [0003]).
It would have been obvious to one of ordinary skill in the art, at the time of invention, to modify the device of Song to implement the gate-all-around (GAA) multi-channel FinFET as taught by Yang, as GAA provides improved short channel effect, channel length reduction, gate pitch reduction, and also increase drive current with larger effective device widths (para [0003], Yang).
Allowable Subject Matter
Claims 21-24 are allowed.
Claims 10, 12-14 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 21 is allowable for at least the following reasons. Most of the limitations of claim 21 are taught by Lai et al. (US 2023/0040387 A1) as stated earlier in claims 1 and 7-8. However, Lai does not teach the limitation, wherein “a third gate structure disposed on a second edge of the active region, the second edge opposing the first edge”. Yu et al. (US 2015/0255593 A1) teaches multiple piece-wise dummy gate structures (210, Fig. 2A, para [0025]), which are disposed on either edges of fin-like structures (208, Fig. 2A, para [0025], also see Fig. 4D) in the seal ring region, but does not show contact structures over the fin-like structures. It would not have been obvious to a person of ordinary skill in the art to combine the above teachings to either form the piece-wise dummy gate structures in the device of Lai or dispose contact structures on the fin-like structures in the seal ring region of the device of Yu, to reach the combined limitation recited in claim 21. Claims 22-24 depend from 21 and are allowable for at least the reasons above.
Claim 10 is allowable for at least the following reasons. Lai et al. (US 2023/0040387 A1) teaches a third active region disposed on the corner regions of the seal ring region (see Fig. 1), while Lai et al. (US 2023/0040287 A1, hereinafter Lai-2) teaches that the active regions in the corner can be segmented (see Figs. 1 and 3), but they do not teach the limitation that states, “third gate structures disposed on edges of the third active regions, wherein each of the third gate structures fully surrounds a respective one of the third active regions.” This limitation is neither anticipated nor made obvious by the prior art of record in the Examiner’s opinion.
Claim 12 is allowable for at least the reasons of, “wherein each of the active region, the first gate structure, the second gate structure, and the contact structure is a ring shape.” Other prior arts like Lai et al. (US 2023/0040387 A1) teaches this limitation, where the individual structures are formed in the seal ring region. However, the primary reference for claim 11, Song et al. (US 2019/0385916 A1), from which claim 12 depends on, teaches the limitations of claim 11 within a circuit region of a substrate. Hence, in the examiner’s opinion, it would not have been obvious to a person of ordinary skill in the art to combine the above teachings, to reach the limitation of claim 12. Claim 13 depends from claim 12 and is allowable for at least the reasons above.
Claim 14 is allowable for at least the reasons of, “wherein the region is an edge region of the semiconductor structure, the active region extends lengthwise in a second direction in a corner region of the semiconductor structure, and the second direction is about 45 degrees tilted with respect to the first direction.” Other prior art like Lai et al. (US 2023/0040287 A1, hereinafter Lai-2) teaches this limitation, where the active region is tilted 45 degrees in the corners of the seal ring region (see Figs. 1, 3 and 4). However, the primary reference for claim 11, Song et al. (US 2019/0385916 A1), from which claim 14 depends on, teaches the limitations of claim 11 within a circuit region of a substrate. Hence, in the examiner’s opinion, it would not have been obvious to a person of ordinary skill in the art to combine the above teachings, to reach the limitation of claim 14.
Claim 17 is allowable for at least the following reasons. Song et al. (US 2019/0385916 A1) teaches an isolation feature (120, Figs. 2A-2B, para [0033]) surrounding the active fins but does not teach the limitation, wherein “a second contact structure disposed completely on the isolation feature, the second contact structure extending lengthwise in the first direction in the region of the semiconductor structure, the first and second contact structures sandwiching the second gate structure.” This limitation is neither anticipated nor made obvious by the prior art of record in the Examiner’s opinion.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
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/P.D./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898