DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
Prior objection to drawing is withdrawn in view of corrected drawings.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 5-6 and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by You et al. (US 2022/0037521 A1, newly cited).
Re Claim 1, You teaches a semiconductor structure, comprising:
a substrate (“SUB”, Figs. 1-2B, para [0035]) having a circuit region (“IC” region, Fig. 1, para [0035]) and a seal ring region (“GR” region, Fig. 1, para [0038]) around the circuit region (“IC” region);
first active regions (15L, Fig. 2B, paras [0043] – [0045]) of a first width (width of 15L in Fig. 2B) disposed in the circuit region;
second active regions (115L, Fig. 5B, para [0079]) of a second width (width of 115L, Fig. 5B) disposed in the seal ring region (“GR” region, Fig. 5A), wherein the second width is greater than the first width (width of 115L in “GR” region can be wider than width of 15L in “IC” region, para [0079]);
first gate structures (30, Fig. 2B, para [0052]) disposed on the first active regions (15L, Fig. 2B), wherein the first gate structures are longitudinally oriented to be orthogonal with the first active regions (see Figs. 2A-2B); and
second gate structures (130a, Figs. 5A-5B, para [0124] – [0125]) disposed on longitudinal edges of the second active regions (“GR” region, see Fig. 5A) and overlapping with the longitudinal edges of the second active regions when viewed from top (see Fig. 5A, para [0124]), wherein the second gate structures are longitudinally oriented to be in parallel with the second active regions (see Fig. 5A).
Re Claim 5, You teaches the semiconductor structure of claim 1, wherein the first active regions (15L, Figs. 2A-2B) occupy a first percentile of a first area (marked “1st area”, in annotated Fig. 2A below) in the circuit region (“IC” region), the second active regions (115L, Figs. 5A-5B) occupy a second percentile of a second area (marked “2nd area”, in annotated Fig. 5A below) in the seal ring region (“GR” region), and a difference between the first percentile and the second percentile is within 10% (Examiner notes that the extent of the areas that can be chosen for the calculation are not defined. Hence, one can arbitrarily define “a first area” in the circuit region (marked “a 1st area”, in annotated Fig. 2A below) and “a second area” in the seal region (marked “a 2nd area”, in annotated Fig. 5A below), such that a difference between the first percentile and the second percentile is within 10%. The claim language does not preclude this treatment).
PNG
media_image1.png
439
816
media_image1.png
Greyscale
Re Claim 6, You teaches the semiconductor structure of claim 1, wherein the first gate structures (30, Fig. 2A) occupy a first percentile of a first area (marked “1st gate area”, in annotated Fig. 2A below) in the circuit region (“IC” region), the second gate structures (130a, Figs. 5A) occupy a second percentile of a second area (marked “a 2nd gate area”, in annotated Fig. 5A below) in the seal ring region (“GR” region), and a difference between the first percentile and the second percentile is within 10% (Examiner notes that the extent of the areas that can be chosen for the calculation are not defined. Hence, one can arbitrarily define “a first area” in the circuit region (marked “a 1st gate area”, in annotated Fig. 2A below) and “a second area” in the seal region (marked “a 2nd gate area”, in annotated Fig. 5A below), such that a difference between the first percentile and the second percentile is within 10%. The claim language does not preclude this treatment).
PNG
media_image2.png
429
782
media_image2.png
Greyscale
Re Claim 9, You teaches the semiconductor structure of claim 1, wherein each of the second active regions (115L, Figs. 5A-B) is a continuous ring shape (see Fig. 1) to enclose the circuit region (“IC region”), and each of the second gate structures (130a, Figs. 5A-5B) is a continuous ring shape (see Fig. 1) to enclose the circuit region (“IC region”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2-4 are rejected under 35 U.S.C. 103 as being unpatentable over You et al. (US 2022/0037521 A1, newly cited), and further in view of Lai et al. (US 2023/0040287 A1, hereinafter Lai-2, of record).
Re Claim 2, You teaches the semiconductor structure of claim 1, but does not explicitly disclose that a ratio of the second width over the first width ranges between 1.1 and 5.
Related art Lai-2 teaches a similar seal ring region enclosing a circuit region where the width of the active region in the seal region can be 250 nm (w1, Fig. 3, para [0029]), while the width of the active region in the circuit region can be 60 nm (2*wD + wG = 2*20 + 20 = 60 nm, Fig. 2, para [0027]), which gives a ratio of 250/60 = 4.2, within the claimed range.
It would have been obvious to one of ordinary skill in the art, at the time of invention, to optimize the ratio of the widths of the active regions in the seal region and the circuit region and arrive at the claimed range. With respect to the limitations of the claim, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955). The optimization of the claimed ratio would have been obvious to one of ordinary skill in the art.
Re Claim 3, You teaches the semiconductor structure of claim 1, but does not disclose that the first gate structures have a third width, and the second gate structures have a fourth width that is substantially equal to the third width.
Related art Lai-2 teaches a similar seal ring region enclosing a circuit region wherein the ratio of the width of the gate structure in the seal region (w4, Fig. 4, para [0036]) to the width of the gate structure in the circuit region (wG, Fig. 2, para [0027]) can be between 1 and 2.5 (para [0036]), satisfying the claim limitation.
It would have been obvious to one of ordinary skill in the art, at the time of invention, to optimize the ratio of the widths of the active regions in the seal region and the circuit region and arrive at the claimed limitation. With respect to the limitations of the claim, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955). The optimization of the claimed ratio would have been obvious to one of ordinary skill in the art.
Re Claim 4, You teaches the semiconductor structure of claim 1, wherein each of the second gate structures (130a, Fig. 5B) overlaps with a respective one of the second active regions (115L, Fig. 5B).
You does not explicitly disclose that the overlap width is between 5 nm and 15 nm measured from a respective one of the longitudinal edges towards a centerline of the respective one of the second active regions. However, from Fig. 5B, one of ordinary skill would realize that the overlap width is approximately one-half the width of the gate structure.
Related art Lai-2 teaches a similar seal ring region enclosing a circuit region wherein the width of the gate structure in the seal region (w4, Fig. 4, para [0036]) can be between 18 nm and 27 nm (para [0036]).
Comparing You and Lai-2, where the width of the gate structure can be between 18 nm and 27 nm (para [0036], Lai-2), the overlap region can thus be one-half the width of the gate structure (as stated above) and therefore can be between 9 nm and 13 nm, within the claimed limitation.
Additionally, it would have been obvious to one of ordinary skill in the art, at the time of invention, to optimize the overlap width and arrive at the claimed range. With respect to the limitations of the claim, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955). The optimization of the claimed width would have been obvious to one of ordinary skill in the art.
Allowable Subject Matter
Claims 11, 13-15, 17 and 21-25 are allowed.
Claims 7-8 and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 11 is allowable for at least the following reasons. Most of the limitation of claim 11 are taught by Song et al. (US 2019/0385916 A1, of record), and further in view of Knoblinger et al. (US 2007/0181942 A1, of record), as explained in the last Office Action dated 1/23/2026. However, the newly amended claim includes an additional limitation wherein, “wherein each of the active region, the first gate structure, the second gate structure, and the contact structure is a ring shape”. Song in view of Knoblinger fails to teach the above limitation. Other prior arts like Lai et al. (US 2023/0040387 A1, of record) teaches this limitation, where the individual structures are formed in the seal ring region. However, the primary reference Song et al. (US 2019/0385916 A1, of record) teaches the limitations of claim 11 within a circuit region of a substrate. Hence, in the examiner’s opinion, it would not have been obvious to a person of ordinary skill in the art to combine the above teachings, to reach the combined limitation of claim 11, as was also stated in the objection of claim 12 in the last office action dated 1/23/2026. Claim 13-15, 17 and 25 depend from claim 11 and are allowable for at least the reasons above.
Claims 21-24 were allowed in the last office action dated 1/23/2026.
Claim 7 is allowable for at least the reasons of, “wherein the semiconductor structure of claim 1, further comprising: contact structures disposed on the second active regions and completely landing on the second active regions”. In the embodiment of Figs. 5A-5B, as was used in the rejection of claim 1 above, You et al. (US 2022/0037521 A1), does not teach any additional contact structures “disposed on the second active regions and completely landing on the second active regions”. Prior art, Lai et al. (US 2023/0040387 A1, of record), shows a seal region where both a contact structure (380, Figs. 3 and 17, para [0021]) and a gate structure (380, Figs. 3 and 17) are disposed on the second active regions (320+360+362+324, Fig. 17), but the gate structure does not overlap with the longitudinal edges of the second active regions, as required in the independent claim 1, from which claim 7 depends on. Additionally, in Examiner’s opinion, it would not be obvious to one of ordinary skill in the art to combine the above prior arts to reach the whole limitation of claim 7, when viewed in context of the independent claim 1, as a whole. Claim 8 depends from claim 7 and is allowable for at least the reasons above.
Claim 10 is allowable for at least the following reasons. You et al. (US 2022/0037521 A1, newly cited), used in the rejection of claim 1 above, fails to teach the limitations of claim 10. Prior art, Lai et al. (US 2023/0040387 A1, of record) teaches a third active region disposed on the corner regions of the seal ring region (see Fig. 1), while Lai et al. (US 2023/0040287 A1, hereinafter Lai-2, of record) teaches that the active regions in the corner can be segmented (see Figs. 1 and 3), but they do not teach the limitation that states, “third gate structures disposed on edges of the third active regions, wherein each of the third gate structures fully surrounds a respective one of the third active regions.” This limitation is neither anticipated nor made obvious by the prior art of record in the Examiner’s opinion, when taken in context of the entire claim 10 and in view of the independent claim 1 and intervening dependent claim 9, as a whole.
Response to Arguments
Applicant’s arguments with respect to claim 1 has been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PINAKI DAS whose telephone number is (703)756-5641. The examiner can normally be reached M-F 8-5 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JULIO MALDONADO can be reached at (571)272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/P.D./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
Prosecution Insights