Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election of claims 13 – 20 without traverse, in the reply filed on 1/12/2026 is acknowledged. Applicant newly added claims 21 – 32.
Newly submitted claims 21 – 32 directed to an invention that is independent or distinct from the invention originally claimed for the following reasons:
I. Claim 13 – 20, drawn to a method, classified in H10D64/017.
II. Claim 21 – 32, drawn to a method of forming a semiconductor device, classified in H10D62/116.
Inventions I and II are directed to related method. The related inventions are distinct if: (1) the inventions as claimed are either not capable of use together or can have a materially different design, mode of operation, function, or effect; (2) the inventions do not overlap in scope, i.e., are mutually exclusive; and (3) the inventions as claimed are not obvious variants. See MPEP § 806.05(j). In the instant case, the inventions have a materially different design. Inventions I requires a dummy gate structure; a first plurality of lateral cavities; a dummy inner spacer layer including a first portion and a second portion; a plurality of dummy lateral spacers; a first dummy fill material; a second dummy fill material; removing a portion of a dummy sidewall spacer layer to form a vertical cavity above the second plurality of lateral cavities; while invention II requires a dielectric gas; a first dielectric gas; a second dielectric gas; the second dielectric region is between a contact structure and the first portion of the gate structure; a plurality of curved regions penetrating into the second portion of the gate structure; a top nanostructure channel of the plurality of nanostructure channels is between the first dielectric region and the second dielectric region; the filler structure is configured to seal the second dielectric gas within the second dielectric region; forming a tunnel region that connects the first dielectric region and the second dielectric region.
Since applicant has received an action on the merits for the originally presented invention, this invention has been constructively elected by original presentation for prosecution on the merits. Accordingly, claims 21 – 32 withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03.
To preserve a right to petition, the reply to this action must distinctly and specifically point out supposed errors in the restriction requirement. Otherwise, the election shall be treated as a final election without traverse. Traversal must be timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are subsequently added, applicant must indicate which of the subsequently added claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 13 – 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ando ( Pub. No. US 20190157414 A1 ), hereinafter Ando.
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Regarding Independent Claim 13 (Original), Ando teaches a method, comprising:
forming, over a semiconductor substrate ( Ando, FIG. 1, 102; [0023], semiconductor substrate 102 ), a plurality of nanostructure layers ( Ando, FIG. 1, 108, 104, 106; [0024], A stack of alternating semiconductor layers 108. Layers of a sacrificial material 104 alternate with layers of a channel material 106 ) in a direction that is perpendicular to the semiconductor substrate ( Ando, FIG. 1, 102 ),
wherein the plurality of nanostructure layers ( Ando, FIG. 1, 108, 104, 106 ) comprises a plurality of sacrificial layers ( Ando, FIG. 1, 104, [0024], Layers of a sacrificial material 104 ) alternating with a plurality of channel layers( Ando, FIG. 1, 106, [0024], layers of a channel material 106 ) ;
forming, over the plurality of nanostructure layers ( Ando, FIG. 1, 108, 104, 106 ), a dummy gate structure ( Ando, FIG. 2, 205; [0027], Dummy gates 205 );
forming, in each of the plurality of sacrificial layers ( Ando, FIG. 1, 104 ), a first plurality of lateral cavities ( Ando, FIG. 3, 302; [0033], etched sacrificial layers 302 ) that penetrate laterally into respective sacrificial layers of the plurality of sacrificial layers ( Ando, [0033], The etch selectively removes material from the layers of sacrificial material 104 and leaves the layers of channel material in place 106, creating etched sacrificial layers 302 );
forming a dummy inner spacer layer ( Ando, FIG. 4, 402; FIG. 5, 502; FIG. 7, 702; [0034], A first inner spacer layer 402; [0036], A second inner spacer layer 502; [0039], expanded second inner spacer layers 702 ) including a first portion ( Ando, FIG. 4, 402; or FIG. 5, 502, FIG. 7, 702 ) and a second portion ( Ando, FIG. 5, 502, FIG. 7, 702; or FIG. 4, 402 ),
wherein the first portion ( Ando, FIG. 4, 402; or FIG. 5, 502, FIG. 7, 702 ) of the dummy inner spacer layer ( Ando, FIG. 4, 402; FIG. 5, 502; FIG. 7, 702 ) fills the first plurality of lateral cavities ( Ando, FIG. 3, 302 );
removing the second portion ( Ando, [0036], As with the first inner spacer layer 402, additional deposited material may be removed from exposed surfaces using, e.g., an anisotropic etch; [0038], An etch is performed to recess the first inner spacer layer 402, producing recessed first inner spacers 602; [0048], the expanded second inner spacer layer 702 is etched away ) of the dummy inner spacer layer ( Ando, FIG. 4, 402; FIG. 5, 502; FIG. 7, 702 ),
wherein the first portion ( Ando, FIG. 6, 502, 602; FIG. 7, 702 ) that fills the first plurality of lateral cavities (Ando, FIG. 3, 302) remains in the first plurality of lateral cavities (Ando, FIG. 3, 302), and
wherein the first portion ( Ando, FIG. 6, 502, 602; FIG. 7, 702 ) that fills the first plurality of lateral cavities ( Ando, FIG. 3, 302 ) corresponds to a plurality of dummy lateral spacers ( FIG. 7, 702, 602 ) within the first plurality of lateral cavities ( Ando, FIG. 3, 302 );
removing the dummy gate structure ( Ando, FIG. 2, 205; [0044], The dummy gate stack is removed by an appropriate etch );
removing the plurality of sacrificial layers ( Ando, FIG. 9, 302; [0044], the recessed sacrificial layers 302 are etched away as well );
forming a metal gate structure ( Ando, FIG. 9, 904; [0044], a gate conductor 904 ),
wherein forming the metal gate structure ( Ando, FIG. 9, 904 ) comprises forming a portion that wraps around ( Ando, [0044], It is specifically contemplated that the gate dielectric layer 902 and the gate conductor 904 will form a “gate-all-around” structure, completely encircling the exposed portions of the channel layers 106 ) a plurality of nanostructure channels ( Ando, FIG. 9, 106 ) formed from the plurality of channel layers; and
removing the plurality of dummy lateral spacers ( Ando, FIG. 11, [0048], the expanded second inner spacer layer 702 is etched away ) to form a dielectric region ( Ando, FIG. 11, etched 702; FIG. 12, 1204; [0049], inner air gaps 1204 ) including a second plurality of lateral cavities ( Ando, FIG. 11, etched 702 ) between the portion of the metal gate structure ( Ando, FIG. 9, 904 ) that wraps around the plurality of nanostructure channels ( Ando, FIG. 9, 106 ) and a source/drain region ( Ando, FIG. 9, 802; [0041], Source/drain regions 802 ).
Regarding Claim 14 (Original), Ando teaches the method of claim 13, on which this claim is dependent, Ando further teaches: further comprising:
forming a helmet structure ( Ando, FIG. 8, FIG. 9, FIG. 10, 806; [0043], An encapsulating layer 806 is then deposited to protect the source/drain regions 802 and inner spacer layers ) over a dielectric layer ( Ando, FIG. 8, 804; [0043], A liner layer 804 of, e.g., silicon nitride, is conformally deposited over the source/drain regions 802 ) that is over the source/drain region (Ando, FIG. 8, FIG. 9, 802) subsequent to forming the metal gate structure ( Ando, FIG. 9, 904 ) and prior to removing the plurality of dummy lateral spacers ( Ando, FIG. 11, [0048], the expanded second inner spacer layer 702 is etched away ) .
Regarding Claim 15 (Original), Ando teaches the method of claim 13, on which this claim is dependent, Ando further teaches:
wherein forming the dummy inner spacer layer ( Ando, FIG. 4, 402; FIG. 5, 502; FIG. 7, 702 ) comprises:
using a first deposition operation ( Ando, FIG. 4, 402, [0034], The first inner spacer layer 402 may be formed from, e.g., silicon nitride, by some conformal deposition process such as, e.g., CVD. ) to deposit a first layer of a first dummy fill material corresponding to the first portion ( Ando, FIG. 4, 402 ) that fills the first plurality of lateral cavities ( Ando, FIG. 3, 302 );
and
using a second deposition operation ( Ando, FIG. 5, 502, [0036], A second inner spacer layer 502 is conformally deposited to fill the remaining space and may be formed from, e.g., silicon dioxide. ) that deposits a second layer of a second dummy fill material corresponding to the second portion ( Ando, FIG. 5, 502, FIG. 7, 702 ) adjacent to the dummy gate structure ( Ando, FIG. 2, 205 ),
wherein the second dummy fill material ( Ando, FIG. 5, 502, [0036], silicon dioxide ) is other than the first dummy fill material ( Ando, FIG. 4, 402, [0034], silicon nitride ).
Regarding Claim 16 (Original), Ando teaches the method of claim 13, on which this claim is dependent, Ando further teaches:
wherein forming the dummy inner spacer layer ( Ando, FIG. 4, 402; FIG. 5, 502; FIG. 7, 702 ) comprises:
using a single deposition operation ( Ando, FIG. 4, 402, [0034], The first inner spacer layer 402 may be formed from, e.g., silicon nitride, by some conformal deposition process such as, e.g., CVD. ) to deposit a single dielectric material ( Ando, FIG. 4, 402, [0034], silicon nitride ).
Regarding Claim 17 (Original), Ando teaches the method of claim 16, on which this claim is dependent, Ando further teaches:
wherein using the single deposition operation ( Ando, FIG. 4, 402, [0034], The first inner spacer layer 402 may be formed from, e.g., silicon nitride, by some conformal deposition process such as, e.g., CVD. ) to deposit the single dielectric material ( Ando, FIG. 4, 402, [0034], silicon nitride ) comprises:
using the single deposition operation ( Ando, FIG. 4, 402, [0034], CVD ) to deposit a silicon oxycarbonnitride material ( Ando, FIG. 4, 402, [0034], silicon nitride; FIG. 5, 502, [0036], silicon dioxide; [0049], A new dielectric layer is deposited from a material that will pinch off (e.g., silicoboron carbonitride) and leave air gaps to form outer air-gap spacers 1202. ).
Regarding Claim 18 (Original), Ando teaches the method of claim 13, on which this claim is dependent, Ando further teaches:
wherein the dielectric region ( Ando, FIG. 11, etched 702; FIG. 12, 1204 ) corresponds to a first dielectric region, the portion of the metal gate structure ( Ando, FIG. 9, 904 ) corresponds to a first portion ( Ando, FIG. 9, 904 around 106 ) of the metal gate structure ( Ando, FIG. 9, 904 ), and further comprising:
removing a portion of a dummy sidewall spacer layer ( Ando, FIG. 10, 806; [0043], An encapsulating layer 806 ) to form a vertical cavity ( Ando, FIG. 11, etched 806; FIG. 12, 1202; [0049], outer air-gap spacers 1202 ) above the second plurality of lateral cavities ( Ando, FIG. 11, etched 702 ),
wherein the vertical cavity ( Ando, FIG. 12, 1202 ) is between a second portion ( Ando, FIG. 9, 904 above 106 ) of the metal gate structure ( Ando, FIG. 9, 904 ) above the plurality of nanostructure channels ( Ando, FIG. 12, 106 ) and a dielectric layer ( Ando, FIG. 12, 1202 ) adjacent to the second portion ( Ando, FIG. 9, 904 above 106 ) of the metal gate structure ( Ando, FIG. 9, 904 ).
Regarding Claim 19 (Original), Ando teaches the method of claim 18, on which this claim is dependent, Ando further teaches:
wherein removing the portion of the dummy sidewall spacer layer ( Ando, FIG. 10, 806; [0043], An encapsulating layer 806 ) to form the vertical cavity ( Ando, FIG. 11, etched 806; FIG. 12, 1202; [0049], outer air-gap spacers 1202 ) above the second plurality of lateral cavities ( Ando, FIG. 11, etched 702 ) comprises:
removing the portion of the dummy sidewall spacer layer ( Ando, FIG. 10, 806; [0043], An encapsulating layer 806 ) using a removal operation that is concurrent ( Ando, [0048], In an embodiment where both the encapsulating layer 806 and the second inner spacer layer 702 are formed from the same material (e.g., silicon dioxide), these structures can be removed with a single wet or dry chemical etch ) with removing the dummy inner spacer layer ( Ando, FIG. 4, 402; FIG. 5, 502; FIG. 7, 702 ).
Regarding Claim 20 (Original), Ando teaches the method of claim 18, on which this claim is dependent, Ando further teaches:
wherein removing portion of the dummy sidewall spacer layer ( Ando, FIG. 10, 806; [0043], An encapsulating layer 806 ) to form the vertical cavity ( Ando, FIG. 11, etched 806; FIG. 12, 1202; [0049], outer air-gap spacers 1202 ) above the second plurality of lateral cavities ( Ando, FIG. 11, etched 702 ) comprises:
removing the portion of the dummy sidewall spacer layer ( Ando, FIG. 10, 806; [0043], An encapsulating layer 806 ) using a removal operation that is separate from ( Ando, [0022], Embodiments of the present invention use dual-layer spacers during fabrication and exploit etch selectivity between the two layers to create consistent, uniform inner and outer air-gap spacers; [0031], In one specific embodiment, multiple different etches may be used, with a first etch anisotropically removing material to remove material around the thicker gate pattern hardmask and vertical spacer, followed by a second etch that is selective to the materials of the stack 108 without affecting the remaining hardmask materials ) another removal operation that removes the dummy inner spacer layer ( Ando, FIG. 4, 402; FIG. 5, 502; FIG. 7, 702 ).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Da-Wei Lee whose telephone number is 703-756-1792. The examiner can normally be reached M -̶ F 8:00 am -̶ 6:00 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached on 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DA-WEI LEE/Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817