Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Amendment filed on 5/15/2026 has been entered. Claims 1 – 12 were previously canceled. Claims 13, 18 are amended. Claims 21 – 32 are canceled. Claims 33 – 44 are newly added. Claims 13 – 20, 33 – 44 are pending in the present application.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 13 – 20, 33 – 44 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ando ( Pub. No. US 20190157414 A1 ), hereinafter Ando.
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Regarding Independent Claim 13 (Currently Amended), Ando teaches a method, comprising:
forming, over a semiconductor substrate ( Ando, FIG. 1, 102; [0023], semiconductor substrate 102 ), a plurality of nanostructure layers ( Ando, FIG. 1, 108, 104, 106; [0024], A stack of alternating semiconductor layers 108. Layers of a sacrificial material 104 alternate with layers of a channel material 106 ) in a direction that is perpendicular to the semiconductor substrate ( Ando, FIG. 1, 102 ),
wherein the plurality of nanostructure layers ( Ando, FIG. 1, 108, 104, 106 ) comprises a plurality of sacrificial layers ( Ando, FIG. 1, 104, [0024], Layers of a sacrificial material 104 ) alternating with a plurality of channel layers ( Ando, FIG. 1, 106, [0024], layers of a channel material 106 ) ;
forming, over the plurality of nanostructure layers ( Ando, FIG. 1, 108, 104, 106 ), a dummy gate structure ( Ando, FIG. 2, 205; [0027], Dummy gates 205 );
forming, in each of the plurality of sacrificial layers ( Ando, FIG. 1, 104 ), a first plurality of lateral cavities ( Ando, FIG. 3, 302; [0033], etched sacrificial layers 302 ) that penetrate laterally into respective sacrificial layers of the plurality of sacrificial layers ( Ando, [0033], The etch selectively removes material from the layers of sacrificial material 104 and leaves the layers of channel material in place 106, creating etched sacrificial layers 302 );
forming a dummy inner spacer layer ( Ando, FIG. 4, 402; FIG. 5, 502; FIG. 7, 702; [0034], A first inner spacer layer 402; [0036], A second inner spacer layer 502; [0039], expanded second inner spacer layers 702 ) including a first portion ( Ando, FIG. 4, 402; or FIG. 5, 502, FIG. 7, 702 ) and a second portion ( Ando, FIG. 5, 502, FIG. 7, 702; or FIG. 4, 402 ),
wherein the first portion ( Ando, FIG. 4, 402; or FIG. 5, 502, FIG. 7, 702 ) of the dummy inner spacer layer ( Ando, FIG. 4, 402; FIG. 5, 502; FIG. 7, 702 ) fills the first plurality of lateral cavities ( Ando, FIG. 3, 302 );
removing the second portion ( Ando, [0036], As with the first inner spacer layer 402, additional deposited material may be removed from exposed surfaces using, e.g., an anisotropic etch; [0038], An etch is performed to recess the first inner spacer layer 402, producing recessed first inner spacers 602; [0048], the expanded second inner spacer layer 702 is etched away ) of the dummy inner spacer layer ( Ando, FIG. 4, 402; FIG. 5, 502; FIG. 7, 702 ),
wherein the first portion ( Ando, FIG. 4, 402; or FIG. 5, 502, FIG. 7, 702 ) that fills the first plurality of lateral cavities (Ando, FIG. 3, 302) remains in the first plurality of lateral cavities (Ando, FIG. 3, 302), and
wherein the first portion ( Ando, FIG. 4, 402; or FIG. 5, 502, FIG. 7, 702 ) that fills the first plurality of lateral cavities ( Ando, FIG. 3, 302 ) corresponds to a plurality of dummy lateral spacers ( FIG. 7, 702, 602 ) within the first plurality of lateral cavities ( Ando, FIG. 3, 302 );
removing the dummy gate structure ( Ando, FIG. 2, 205; [0044], The dummy gate stack is removed by an appropriate etch );
removing the plurality of sacrificial layers ( Ando, FIG. 9, 302; [0044], the recessed sacrificial layers 302 are etched away as well );
forming a metal gate structure ( Ando, FIG. 9, 904; [0044], a gate conductor 904 ),
wherein forming the metal gate structure ( Ando, FIG. 9, 904 ) comprises forming a portion that wraps around ( Ando, [0044], It is specifically contemplated that the gate dielectric layer 902 and the gate conductor 904 will form a “gate-all-around” structure, completely encircling the exposed portions of the channel layers 106 ) a plurality of nanostructure channels ( Ando, FIG. 9, 106 ) formed from the plurality of channel layers; and
removing the plurality of dummy lateral spacers ( Ando, FIG. 11, [0048], the expanded second inner spacer layer 702 is etched away ) to form a dielectric region ( Ando, FIG. 11, etched 702; FIG. 12, 1204; [0049], inner air gaps 1204 ) including a second plurality of lateral cavities ( Ando, FIG. 11, etched 702 ),
wherein the second plurality of lateral cavities ( Ando, FIG. 11, etched 702 ) penetrate laterally into ( Ando, FIG. 3, 302; [0033], The etch selectively removes material from the layers of sacrificial material 104 and leaves the layers of channel material in place 106, creating etched sacrificial layers 302 ) the portion of the metal gate structure ( Ando, FIG. 3, 205; [0027], Dummy gates 205; FIG. 9, 904, [0044], recessed sacrificial layers 302 are etched away as well, exposing the surfaces of the channel layers 106. A new gate stack is then deposited including, e.g., a gate dielectric layer 902 and a gate conductor 904. It is specifically contemplated that the gate dielectric layer 902 and the gate conductor 904 will form a “gate-all-around” structure ), and
wherein the second plurality of lateral cavities ( Ando, FIG. 11, etched 702 ) are between the portion of the metal gate structure ( Ando, FIG. 9, 904 ) and a source/drain region ( Ando, FIG. 9, 802; [0041], Source/drain regions 802 ).
Regarding Claim 14 (Original), Ando teaches the method of claim 13, on which this claim is dependent, Ando further teaches: further comprising:
forming a helmet structure ( Ando, FIG. 8, FIG. 9, FIG. 10, 806; [0043], An encapsulating layer 806 is then deposited to protect the source/drain regions 802 and inner spacer layers ) over a dielectric layer ( Ando, FIG. 8, 804; [0043], A liner layer 804 of, e.g., silicon nitride, is conformally deposited over the source/drain regions 802 ) that is over the source/drain region (Ando, FIG. 8, FIG. 9, 802) subsequent to forming the metal gate structure ( Ando, FIG. 9, 904 ) and prior to removing the plurality of dummy lateral spacers ( Ando, FIG. 11, [0048], the expanded second inner spacer layer 702 is etched away ) .
Regarding Claim 15 (Original), Ando teaches the method of claim 13, on which this claim is dependent, Ando further teaches:
wherein forming the dummy inner spacer layer ( Ando, FIG. 4, 402; FIG. 5, 502; FIG. 7, 702 ) comprises:
using a first deposition operation ( Ando, FIG. 4, 402, [0034], The first inner spacer layer 402 may be formed from, e.g., silicon nitride, by some conformal deposition process such as, e.g., CVD. ) to deposit a first layer of a first dummy fill material corresponding to the first portion ( Ando, FIG. 4, 402 ) that fills the first plurality of lateral cavities ( Ando, FIG. 3, 302 );
and
using a second deposition operation ( Ando, FIG. 5, 502, [0036], A second inner spacer layer 502 is conformally deposited to fill the remaining space and may be formed from, e.g., silicon dioxide. ) that deposits a second layer of a second dummy fill material corresponding to the second portion ( Ando, FIG. 5, 502, FIG. 7, 702 ) adjacent to the dummy gate structure ( Ando, FIG. 2, 205 ),
wherein the second dummy fill material ( Ando, FIG. 5, 502, [0036], silicon dioxide ) is other than the first dummy fill material ( Ando, FIG. 4, 402, [0034], silicon nitride ).
Regarding Claim 16 (Original), Ando teaches the method of claim 13, on which this claim is dependent, Ando further teaches:
wherein forming the dummy inner spacer layer ( Ando, FIG. 4, 402; FIG. 5, 502; FIG. 7, 702 ) comprises:
using a single deposition operation ( Ando, FIG. 4, 402, [0034], The first inner spacer layer 402 may be formed from, e.g., silicon nitride, by some conformal deposition process such as, e.g., CVD. ) to deposit a single dielectric material ( Ando, FIG. 4, 402, [0034], silicon nitride ).
Regarding Claim 17 (Original), Ando teaches the method of claim 16, on which this claim is dependent, Ando further teaches:
wherein using the single deposition operation ( Ando, FIG. 4, 402, [0034], The first inner spacer layer 402 may be formed from, e.g., silicon nitride, by some conformal deposition process such as, e.g., CVD. ) to deposit the single dielectric material ( Ando, FIG. 4, 402, [0034], silicon nitride ) comprises:
using the single deposition operation ( Ando, FIG. 4, 402, [0034], CVD ) to deposit a silicon oxycarbonnitride material ( Ando, FIG. 4, 402, [0034], silicon nitride; FIG. 5, 502, [0036], silicon dioxide; [0049], A new dielectric layer is deposited from a material that will pinch off (e.g., silicoboron carbonitride) and leave air gaps to form outer air-gap spacers 1202. ).
Regarding Claim 18 (Currently Amended), Ando teaches the method of claim 13, on which this claim is dependent, Ando further teaches:
wherein the dielectric region ( Ando, FIG. 11, etched 702; FIG. 12, 1204 ) corresponds to a first dielectric region,
wherein the portion of the metal gate structure ( Ando, FIG. 9, 904 ) corresponds to a first portion ( Ando, FIG. 9, 904 around 106 ) of the metal gate structure ( Ando, FIG. 9, 904 ), and
wherein the method further comprises:
removing a portion of a dummy sidewall spacer layer ( Ando, FIG. 10, 806; [0043], An encapsulating layer 806 ) to form a vertical cavity ( Ando, FIG. 11, etched 806; FIG. 12, 1202; [0049], outer air-gap spacers 1202 ) above the second plurality of lateral cavities ( Ando, FIG. 11, etched 702 ),
wherein the vertical cavity ( Ando, FIG. 12, 1202 ) is between a second portion ( Ando, FIG. 9, 904 above 106 ) of the metal gate structure ( Ando, FIG. 9, 904 ) above the plurality of nanostructure channels ( Ando, FIG. 12, 106 ) and a dielectric layer ( Ando, FIG. 12, 1202 ) adjacent to the second portion ( Ando, FIG. 9, 904 above 106 ) of the metal gate structure ( Ando, FIG. 9, 904 ).
Regarding Claim 19 (Original), Ando teaches the method of claim 18, on which this claim is dependent, Ando further teaches:
wherein removing the portion of the dummy sidewall spacer layer ( Ando, FIG. 10, 806; [0043], An encapsulating layer 806 ) to form the vertical cavity ( Ando, FIG. 11, etched 806; FIG. 12, 1202; [0049], outer air-gap spacers 1202 ) above the second plurality of lateral cavities ( Ando, FIG. 11, etched 702 ) comprises:
removing the portion of the dummy sidewall spacer layer ( Ando, FIG. 10, 806; [0043], An encapsulating layer 806 ) using a removal operation that is concurrent ( Ando, [0048], In an embodiment where both the encapsulating layer 806 and the second inner spacer layer 702 are formed from the same material (e.g., silicon dioxide), these structures can be removed with a single wet or dry chemical etch ) with removing the dummy inner spacer layer ( Ando, FIG. 4, 402; FIG. 5, 502; FIG. 7, 702 ).
Regarding Claim 20 (Original), Ando teaches the method of claim 18, on which this claim is dependent, Ando further teaches:
wherein removing portion of the dummy sidewall spacer layer ( Ando, FIG. 10, 806; [0043], An encapsulating layer 806 ) to form the vertical cavity ( Ando, FIG. 11, etched 806; FIG. 12, 1202; [0049], outer air-gap spacers 1202 ) above the second plurality of lateral cavities ( Ando, FIG. 11, etched 702 ) comprises:
removing the portion of the dummy sidewall spacer layer ( Ando, FIG. 10, 806; [0043], An encapsulating layer 806 ) using a removal operation that is separate from ( Ando, [0022], Embodiments of the present invention use dual-layer spacers during fabrication and exploit etch selectivity between the two layers to create consistent, uniform inner and outer air-gap spacers; [0031], In one specific embodiment, multiple different etches may be used, with a first etch anisotropically removing material to remove material around the thicker gate pattern hardmask and vertical spacer, followed by a second etch that is selective to the materials of the stack 108 without affecting the remaining hardmask materials ) another removal operation that removes the dummy inner spacer layer ( Ando, FIG. 4, 402; FIG. 5, 502; FIG. 7, 702 ).
Regarding Independent Claim 33 (New), Ando teaches a method, comprising:
forming, over a semiconductor substrate ( Ando, FIG. 1, 102; [0023], semiconductor substrate 102 ), a plurality of nanostructure layers ( Ando, FIG. 1, 108, 104, 106; [0024], A stack of alternating semiconductor layers 108. Layers of a sacrificial material 104 alternate with layers of a channel material 106 ) in a direction that is perpendicular to the semiconductor substrate ( Ando, FIG. 1, 102 );
forming, over the plurality of nanostructure layers ( Ando, FIG. 1, 108, 104, 106 ), a dummy gate structure ( Ando, FIG. 2, 205; [0027], Dummy gates 205 );
forming a first plurality of lateral cavities ( Ando, FIG. 3, 302; [0033], etched sacrificial layers 302 ) that penetrate laterally into respective layers of the plurality of nanostructure layers ( Ando, [0033], The etch selectively removes material from the layers of sacrificial material 104 and leaves the layers of channel material in place 106, creating etched sacrificial layers 302 );
forming a dummy inner spacer layer ( Ando, FIG. 4, 402; FIG. 5, 502; FIG. 7, 702; [0034], A first inner spacer layer 402; [0036], A second inner spacer layer 502; [0039], expanded second inner spacer layers 702 ) including a first portion ( Ando, FIG. 4, 402; or FIG. 5, 502, FIG. 7, 702 ) and a second portion ( Ando, FIG. 5, 502, FIG. 7, 702; or FIG. 4, 402 ),
wherein the first portion ( Ando, FIG. 4, 402; or FIG. 5, 502, FIG. 7, 702 ) of the dummy inner spacer layer ( Ando, FIG. 4, 402; FIG. 5, 502; FIG. 7, 702 ) fills the first plurality of lateral cavities ( Ando, FIG. 3, 302 );
removing the second portion ( Ando, [0036], As with the first inner spacer layer 402, additional deposited material may be removed from exposed surfaces using, e.g., an anisotropic etch; [0038], An etch is performed to recess the first inner spacer layer 402, producing recessed first inner spacers 602; [0048], the expanded second inner spacer layer 702 is etched away ) of the dummy inner spacer layer ( Ando, FIG. 4, 402; FIG. 5, 502; FIG. 7, 702 ),
wherein the first portion ( Ando, FIG. 4, 402; or FIG. 5, 502, FIG. 7, 702 ) that fills the first plurality of lateral cavities (Ando, FIG. 3, 302) remains in the first plurality of lateral cavities (Ando, FIG. 3, 302), and
wherein the first portion ( Ando, FIG. 4, 402; or FIG. 5, 502, FIG. 7, 702 ) that fills the first plurality of lateral cavities ( Ando, FIG. 3, 302 ) corresponds to a plurality of dummy lateral spacers ( FIG. 7, 702, 602 ) within the first plurality of lateral cavities ( Ando, FIG. 3, 302 );
removing the dummy gate structure ( Ando, FIG. 2, 205; [0044], The dummy gate stack is removed by an appropriate etch );
forming a metal gate structure ( Ando, FIG. 9, 904; [0044], a gate conductor 904 ),
wherein forming the metal gate structure ( Ando, FIG. 9, 904 ) comprises forming a portion that wraps around ( Ando, [0044], It is specifically contemplated that the gate dielectric layer 902 and the gate conductor 904 will form a “gate-all-around” structure, completely encircling the exposed portions of the channel layers 106 ) a plurality of nanostructure channels ( Ando, FIG. 9, 106 ) formed from the plurality of nanostructure layers; and
removing the plurality of dummy lateral spacers ( Ando, FIG. 11, [0048], the expanded second inner spacer layer 702 is etched away ) to form a dielectric region ( Ando, FIG. 11, etched 702; FIG. 12, 1204; [0049], inner air gaps 1204 ) including a second plurality of lateral cavities ( Ando, FIG. 11, etched 702 ),
wherein the second plurality of lateral cavities ( Ando, FIG. 11, etched 702 ) penetrate laterally into ( Ando, FIG. 3, 302; [0033], The etch selectively removes material from the layers of sacrificial material 104 and leaves the layers of channel material in place 106, creating etched sacrificial layers 302 ) the portion of the metal gate structure ( Ando, FIG. 3, 205; [0027], Dummy gates 205; FIG. 9, 904, [0044], recessed sacrificial layers 302 are etched away as well, exposing the surfaces of the channel layers 106. A new gate stack is then deposited including, e.g., a gate dielectric layer 902 and a gate conductor 904. It is specifically contemplated that the gate dielectric layer 902 and the gate conductor 904 will form a “gate-all-around” structure ), and
wherein the second plurality of lateral cavities ( Ando, FIG. 11, etched 702 ) are between the portion of the metal gate structure ( Ando, FIG. 9, 904 ) and a source/drain region ( Ando, FIG. 9, 802; [0041], Source/drain regions 802 ).
Regarding Claim 34 (New), Ando teaches the method of claim 33, on which this claim is dependent, Ando further teaches:
wherein the plurality of nanostructure layers comprises a plurality of sacrificial layers ( Ando, FIG. 1, 104, [0024], Layers of a sacrificial material 104 ) alternating with a plurality of channel layers ( Ando, FIG. 1, 106, [0024], layers of a channel material 106 ), the method further comprising:
removing the plurality of sacrificial layers ( Ando, FIG. 9, 302; [0044], the recessed sacrificial layers 302 are etched away as well ) after removing the dummy gate structure ( Ando, FIG. 2, 205; [0044], The dummy gate stack is removed by an appropriate etch ).
Regarding Claim 35 (New), Ando teaches the method of claim 33, on which this claim is dependent, Ando further teaches: further comprising:
forming a helmet structure ( Ando, FIG. 8, FIG. 9, FIG. 10, 806; [0043], An encapsulating layer 806 is then deposited to protect the source/drain regions 802 and inner spacer layers ) over a dielectric layer ( Ando, FIG. 8, 804; [0043], A liner layer 804 of, e.g., silicon nitride, is conformally deposited over the source/drain regions 802 ) that is over the source/drain region (Ando, FIG. 8, FIG. 9, 802) subsequent to forming the metal gate structure ( Ando, FIG. 9, 904 ) and prior to removing the plurality of dummy lateral spacers ( Ando, FIG. 11, [0048], the expanded second inner spacer layer 702 is etched away ).
Regarding Claim 36 (New), Ando teaches the method of claim 33, on which this claim is dependent, Ando further teaches:
wherein forming the dummy inner spacer layer ( Ando, FIG. 4, 402; FIG. 5, 502; FIG. 7, 702 ) comprises:
using a first deposition operation ( Ando, FIG. 4, 402, [0034], The first inner spacer layer 402 may be formed from, e.g., silicon nitride, by some conformal deposition process such as, e.g., CVD. ) to deposit a first layer of a first dummy fill material corresponding to the first portion ( Ando, FIG. 4, 402 ) that fills the first plurality of lateral cavities ( Ando, FIG. 3, 302 ); and
using a second deposition operation ( Ando, FIG. 5, 502, [0036], A second inner spacer layer 502 is conformally deposited to fill the remaining space and may be formed from, e.g., silicon dioxide. ) that deposits a second layer of a second dummy fill material corresponding to the second portion ( Ando, FIG. 5, 502, FIG. 7, 702 ) adjacent to the dummy gate structure ( Ando, FIG. 2, 205 ),
wherein the second dummy fill material ( Ando, FIG. 5, 502, [0036], silicon dioxide ) is other than the first dummy fill material ( Ando, FIG. 4, 402, [0034], silicon nitride ).
Regarding Claim 37 (New), Ando teaches the method of claim 33, on which this claim is dependent, Ando further teaches:
wherein forming the dummy inner spacer layer ( Ando, FIG. 4, 402; FIG. 5, 502; FIG. 7, 702 ) comprises:
using a single deposition operation ( Ando, FIG. 4, 402, [0034], The first inner spacer layer 402 may be formed from, e.g., silicon nitride, by some conformal deposition process such as, e.g., CVD. ) to deposit a single dielectric material ( Ando, FIG. 4, 402, [0034], silicon nitride ).
Regarding Claim 38 (New), Ando teaches the method of claim 37, on which this claim is dependent, Ando further teaches:
wherein using the single deposition operation ( Ando, FIG. 4, 402, [0034], The first inner spacer layer 402 may be formed from, e.g., silicon nitride, by some conformal deposition process such as, e.g., CVD. ) to deposit the single dielectric material ( Ando, FIG. 4, 402, [0034], silicon nitride ) comprises:
using the single deposition operation ( Ando, FIG. 4, 402, [0034], CVD ) to deposit a silicon oxycarbonnitride material ( Ando, FIG. 4, 402, [0034], silicon nitride; FIG. 5, 502, [0036], silicon dioxide; [0049], A new dielectric layer is deposited from a material that will pinch off (e.g., silicoboron carbonitride) and leave air gaps to form outer air-gap spacers 1202. ).
Regarding Independent Claim 39 (New), Ando teaches a method, comprising:
forming, over a semiconductor substrate ( Ando, FIG. 1, 102; [0023], semiconductor substrate 102 ), a plurality of nanostructure layers ( Ando, FIG. 1, 108, 104, 106; [0024], A stack of alternating semiconductor layers 108. Layers of a sacrificial material 104 alternate with layers of a channel material 106 ) in a direction that is perpendicular to the semiconductor substrate ( Ando, FIG. 1, 102 ),
wherein the plurality of nanostructure layers ( Ando, FIG. 1, 108, 104, 106 ) comprises a plurality of sacrificial layers ( Ando, FIG. 1, 104, [0024], Layers of a sacrificial material 104 ) alternating with a plurality of channel layers ( Ando, FIG. 1, 106, [0024], layers of a channel material 106 );
removing the plurality of sacrificial layers ( Ando, FIG. 1, 104 );
forming a metal gate structure ( Ando, FIG. 9, 904; [0044], a gate conductor 904 ),
wherein forming the metal gate structure ( Ando, FIG. 9, 904 ) comprises forming a portion that wraps around ( Ando, [0044], It is specifically contemplated that the gate dielectric layer 902 and the gate conductor 904 will form a “gate-all-around” structure, completely encircling the exposed portions of the channel layers 106 ) a plurality of nanostructure channels ( Ando, FIG. 1, 106 ) formed from the plurality of channel layers; and
forming a dielectric region ( Ando, FIG. 11, etched 702; FIG. 12, 1204; [0049], inner air gaps 1204 ) including a plurality of lateral cavities ( Ando, FIG. 3, 302; [0033], etched sacrificial layers 302; FIG. 11, etched 702; FIG. 12, 1204; [0049], inner air gaps 1204 ),
wherein the plurality of lateral cavities ( Ando, FIG. 11, etched 702 ) penetrate laterally into ( Ando, FIG. 3, 302; [0033], The etch selectively removes material from the layers of sacrificial material 104 and leaves the layers of channel material in place 106, creating etched sacrificial layers 302 ) the portion of the metal gate structure ( Ando, FIG. 3, 205; [0027], Dummy gates 205; FIG. 9, 904, [0044], recessed sacrificial layers 302 are etched away as well, exposing the surfaces of the channel layers 106. A new gate stack is then deposited including, e.g., a gate dielectric layer 902 and a gate conductor 904. It is specifically contemplated that the gate dielectric layer 902 and the gate conductor 904 will form a “gate-all-around” structure ), and
wherein the plurality of lateral cavities ( Ando, FIG. 11, etched 702 ) are between the portion of the metal gate structure ( Ando, FIG. 9, 904 ) and a source/drain region ( Ando, FIG. 11, etched 702 ).
Regarding Claim 40 (New), Ando teaches the method of claim 39, on which this claim is dependent, Ando further teaches:
wherein the plurality of lateral cavities ( Ando, FIG. 11, etched 702 ) is a second plurality of lateral cavities ( Ando, FIG. 11, etched 702 ), the method further comprising:
forming, over the plurality of nanostructure layers ( Ando, FIG. 1, 108, 104, 106 ), a dummy gate structure ( Ando, FIG. 2, 205; [0027], Dummy gates 205 );
forming, in each of the plurality of sacrificial layers ( Ando, FIG. 1, 104 ), a first plurality of lateral cavities ( Ando, FIG. 3, 302; [0033], etched sacrificial layers 302 ) that penetrate laterally into respective sacrificial layers ( Ando, FIG. 1, 104 ) of the plurality of sacrificial layers ( Ando, FIG. 1, 104 );
forming a dummy inner spacer layer ( Ando, FIG. 4, 402; FIG. 5, 502; FIG. 7, 702; [0034], A first inner spacer layer 402; [0036], A second inner spacer layer 502; [0039], expanded second inner spacer layers 702 ) including a first portion ( Ando, FIG. 4, 402; or FIG. 5, 502, FIG. 7, 702 ) and a second portion ( Ando, FIG. 5, 502, FIG. 7, 702; or FIG. 4, 402 ),
wherein the first portion ( Ando, FIG. 4, 402; or FIG. 5, 502, FIG. 7, 702 ) of the dummy inner spacer layer ( Ando, FIG. 4, 402; FIG. 5, 502; FIG. 7, 702 ) fills the first plurality of lateral cavities ( Ando, FIG. 3, 302 );
removing the second portion ( Ando, [0036], As with the first inner spacer layer 402, additional deposited material may be removed from exposed surfaces using, e.g., an anisotropic etch; [0038], An etch is performed to recess the first inner spacer layer 402, producing recessed first inner spacers 602; [0048], the expanded second inner spacer layer 702 is etched away ) of the dummy inner spacer layer ( Ando, FIG. 4, 402; FIG. 5, 502; FIG. 7, 702 ),
wherein the first portion ( Ando, FIG. 4, 402; or FIG. 5, 502, FIG. 7, 702 ) that fills the first plurality of lateral cavities ( Ando, FIG. 3, 302 ) remains in the first plurality of lateral cavities ( Ando, FIG. 3, 302 ), and
wherein the first portion ( Ando, FIG. 4, 402; or FIG. 5, 502, FIG. 7, 702 ) that fills the first plurality of lateral cavities ( Ando, FIG. 3, 302 ) corresponds to a plurality of dummy lateral spacers ( FIG. 7, 702, 602 ) within the first plurality of lateral cavities ( Ando, FIG. 3, 302 ); and
removing the dummy gate structure ( Ando, FIG. 2, 205; [0044], The dummy gate stack is removed by an appropriate etch ) before removing the plurality of sacrificial layers ( Ando, FIG. 9, 302; [0044], the recessed sacrificial layers 302 are etched away as well ).
Regarding Claim 41 (New), Ando teaches the method of claim 40, on which this claim is dependent, Ando further teaches:
wherein forming the dielectric region ( Ando, FIG. 11, etched 702; FIG. 12, 1204 ) comprises:
removing the plurality of dummy lateral spacers ( Ando, FIG. 11, [0048], the expanded second inner spacer layer 702 is etched away ) to form the dielectric region ( Ando, FIG. 11, etched 702; FIG. 12, 1204; [0049], inner air gaps 1204 ) including the second plurality of lateral cavities ( Ando, FIG. 11, etched 702 ).
Regarding Claim 42 (New), Ando teaches the method of claim 40, on which this claim is dependent, Ando further teaches:
wherein the dielectric region ( Ando, FIG. 11, etched 702; FIG. 12, 1204 ) corresponds to a first dielectric region,
wherein the portion of the metal gate structure ( Ando, FIG. 9, 904 ) corresponds to a first portion ( Ando, FIG. 9, 904 around 106 ) of the metal gate structure ( Ando, FIG. 9, 904 ), and
wherein the method further comprises:
removing a portion of a dummy sidewall spacer layer ( Ando, FIG. 10, 806; [0043], An encapsulating layer 806 ) to form a vertical cavity ( Ando, FIG. 11, etched 806; FIG. 12, 1202; [0049], outer air-gap spacers 1202 ) above the plurality of lateral cavities ( Ando, FIG. 11, etched 702 ),
wherein the vertical cavity ( Ando, FIG. 12, 1202 ) is between a second portion ( Ando, FIG. 9, 904 above 106 ) of the metal gate structure ( Ando, FIG. 9, 904 ) above the plurality of nanostructure channels ( Ando, FIG. 1, 106 ) and a dielectric layer ( Ando, FIG. 12, 1202 ) adjacent to the second portion ( Ando, FIG. 9, 904 above 106 ) of the metal gate structure ( Ando, FIG. 9, 904 ).
Regarding Claim 43 (New), Ando teaches the method of claim 42, on which this claim is dependent, Ando further teaches:
wherein removing the portion of the dummy sidewall spacer layer ( Ando, FIG. 10, 806; [0043], An encapsulating layer 806 ) to form the vertical cavity ( Ando, FIG. 11, etched 806; FIG. 12, 1202; [0049], outer air-gap spacers 1202 ) above the plurality of lateral cavities ( Ando, FIG. 11, etched 702 ) comprises:
removing the portion of the dummy sidewall spacer layer ( Ando, FIG. 10, 806; [0043], An encapsulating layer 806 ) using a removal operation that is concurrent ( Ando, [0048], In an embodiment where both the encapsulating layer 806 and the second inner spacer layer 702 are formed from the same material (e.g., silicon dioxide), these structures can be removed with a single wet or dry chemical etch ) with removing the dummy inner spacer layer ( Ando, FIG. 4, 402; FIG. 5, 502; FIG. 7, 702 ).
Regarding Claim 44 (New), Ando teaches the method of claim 42, on which this claim is dependent, Ando further teaches:
wherein removing portion of the dummy sidewall spacer layer ( Ando, FIG. 10, 806; [0043], An encapsulating layer 806 ) to form the vertical cavity ( Ando, FIG. 11, etched 806; FIG. 12, 1202; [0049], outer air-gap spacers 1202 ) above the plurality of lateral cavities ( Ando, FIG. 11, etched 702 ) comprises:
removing the portion of the dummy sidewall spacer layer ( Ando, FIG. 10, 806; [0043], An encapsulating layer 806 ) using a removal operation that is separate from ( Ando, [0022], Embodiments of the present invention use dual-layer spacers during fabrication and exploit etch selectivity between the two layers to create consistent, uniform inner and outer air-gap spacers; [0031], In one specific embodiment, multiple different etches may be used, with a first etch anisotropically removing material to remove material around the thicker gate pattern hardmask and vertical spacer, followed by a second etch that is selective to the materials of the stack 108 without affecting the remaining hardmask materials ) another removal operation that removes the dummy inner spacer layer ( Ando, FIG. 4, 402; FIG. 5, 502; FIG. 7, 702 ).
Response to Arguments
Applicant’s argument for claim 13 ( Currently Amended ): page 12, line 7, cited “
However, as discussed during the interview, Neither the description nor the figures of ANDO can be relied upon to disclose "removing the plurality of dummy lateral spacers to form a dielectric region including a second plurality of lateral cavities, wherein the second plurality of lateral cavities penetrate laterally into the portion of the metal gate structure," as recited in amended claim 1 ( ps. this should be claim 13 ) (emphasis added).
Therefore, independent claim 13, and the claims that depend thereon, are patentable over the cited sections of ANDO. ”.
Examiner’s response:
First, please refer to the interview summary mailed 05/08/2026, cited “ (2) Examiners received and understood the amendments, and explained: the proposed amendments appear to read on prior art Ando in last non-final rejection, i.e. etched 702 in FIG. 11. ”.
Second, please refer to the Claim Rejections - 35 USC § 102 for claim 13 (Currently Amended) in this office action, cited “
removing the plurality of dummy lateral spacers ( Ando, FIG. 11, [0048], the expanded second inner spacer layer 702 is etched away ) to form a dielectric region ( Ando, FIG. 11, etched 702; FIG. 12, 1204; [0049], inner air gaps 1204 ) including a second plurality of lateral cavities ( Ando, FIG. 11, etched 702 ),
wherein the second plurality of lateral cavities ( Ando, FIG. 11, etched 702 ) penetrate laterally into ( Ando, FIG. 3, 302; [0033], The etch selectively removes material from the layers of sacrificial material 104 and leaves the layers of channel material in place 106, creating etched sacrificial layers 302 ) the portion of the metal gate structure ( Ando, FIG. 3, 205; [0027], Dummy gates 205; FIG. 9, 904, [0044], recessed sacrificial layers 302 are etched away as well, exposing the surfaces of the channel layers 106. A new gate stack is then deposited including, e.g., a gate dielectric layer 902 and a gate conductor 904. It is specifically contemplated that the gate dielectric layer 902 and the gate conductor 904 will form a “gate-all-around” structure ), ”. Therefore, each and every feature in amended claim 13 are disclosed by Ando.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Da-Wei Lee whose telephone number is 703-756-1792. The examiner can normally be reached M -̶ F 8:00 am -̶ 6:00 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DA-WEI LEE/Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
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