DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-12, 17-24 in the reply filed on 07/22/26 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-12, 17-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over deVilliers(USPGPUB DOCUMENT: 2017/0092506, hereinafter deVilliers) in view of Lin (USPGPUB DOCUMENT: 2019/0157094, hereinafter Lin).
Re claim 1 deVilliers discloses in Fig 11-14 a method for metal patterning, comprising steps of: forming a plurality of mandrel recesses(recesses of 111) in a mandrel layer(111) over a semiconductor substrate(substrate)[0030,0050];forming a plurality of spacers(left112/right112) respectively in the mandrel recesses(recesses of 111), each of the spacers(left112/right112) being connected to a sidewall of the corresponding one of the mandrel recesses(recesses of 111) and having a spacer recess(left/right recess of left112/right112) formed therein; forming a plurality of filling features(124) respectively in the spacer recesses(left/right recess of left112/right112) of the spacers(left112/right112); performing a second patterning process[0043] to pattern the filling features(124) to form a second line pattern(114)[0046]; forming, in the semiconductor substrate(substrate)[0030,0050],
deVilliers does not disclose first patterning process to pattern the mandrel layer(111) to form a first line pattern; metal lines that are arranged in a pattern which is a combination of the first line pattern and the second line pattern(114)[0046].
Lin disclose first patterning process[0026 of Lin] to pattern the mandrel layer(124) to form a first line pattern(line pattern)[0029 of Lin];
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Lin to the teachings of deVilliers in order to improve processing performance (e.g., photolithographic resolution) may be prevented from achieving continuing improvement due to limitations of available fabrication technologies and equipment [0002, Lin]. In doing so, metal lines[0020 of Lin] that are arranged in a pattern which is a combination of the first line pattern(line pattern)[0029 of Lin] and the second line pattern(114)[0046].
Re claim 2 deVilliers and Lin disclose the method according to claim 1, wherein the step of forming the plurality of the filling features(124) includes:depositing a reverse material[0010 of Lin] layer on the mandrel layer(111) and the spacers(left112/right112) and in the spacer recess(left/right recess of left112/right112)es(recesses of 112); andperforming a planarization process on the reverse material layer to reveal the mandrel layer(111) and the spacers(left112/right112), so as to form the filling features(124) that are formed by a portion of the reverse material layer filled in the spacer recess(left/right recess of left112/right112)es(recesses of 112).
Re claim 3 deVilliers and Lin disclose the method according to claim 2, wherein the reverse material[0010 of Lin] layer includes one of a silicon-containing oxide, a silicon-containing nitride, a metal oxide, a metal nitride, a metal carbide, and a combination thereof.
Re claim 4 deVilliers and Lin disclose the method according to claim 1, wherein the first patterning process includes:forming a first patterning layer over the mandrel layer(111), the spacers(left112/right112) and the filling features(124), where the first patterning layer covers each of the filling features(124) and is formed with multiple openings that correspond to the first line pattern and that expose parts of the mandrel layer(111); andetching the parts of the mandrel layer(111) with the first patterning layer serving as a mask to form the first line pattern in the mandrel layer(111).
Re claim 5 deVilliers and Lin disclose the method according to claim 4, wherein the first line pattern includes a first line segment and a second line segment that extend in a first direction, that are aligned in the first direction, and that are spaced apart from each other in the first direction by a first line-end distance ranging from 2 nm to 50 nm;wherein the first line pattern includes a third line segment and a fourth line segment that extend in the first direction, that are aligned in the first direction, and that are spaced apart from each other in the first direction by a second line-end distance ranging from 2 nm to 50 nm;wherein, in the first line pattern, the third line segment and the fourth line segment are adjacent to the first line segment and the second line segment in a second direction perpendicular to the first direction; andwherein the first line-end distance is different from the second line-end distance.
Re claim 6 deVilliers and Lin disclose the method according to claim 4, wherein the second patterning process[0043] includes:forming a second patterning layer over the mandrel layer(111), the spacers(left112/right112) and the filling features(124), where the second patterning layer covers the mandrel layer(111) and is formed with multiple openings that correspond to the second line pattern(114)[0046] and that expose parts of the filling features(124);and etching the parts of the filling features(124) with the second patterning layer serving as a mask to form the second line pattern(114)[0046] in the filling features(124).
Re claim 7 deVilliers and Lin disclose the method according to claim 6, wherein the second line pattern(114)[0046] includes a first line segment and a second line segment that extend in a first direction, that are aligned in the first direction, and that are spaced apart from each other in the first direction by a first line-end distance ranging from 2 nm to 50 nm;wherein the second line pattern(114)[0046] includes a third line segment and a fourth line segment that extend in the first direction, that are aligned in the first direction, and that are spaced apart from each other in the first direction by a second line-end distance ranging from 2 nm to 50 nm;wherein, in the second line pattern(114)[0046], the third line segment and the fourth line segment are adjacent to the first line segment and the second line segment in a second direction perpendicular to the first direction; andwherein the first line-end distance is different from the second line-end distance.
Re claim 8 deVilliers and Lin disclose the method according to claim 6, wherein the metal lines correspond in position to the openings formed in the first patterning layer and the second patterning layer.
Re claim 9 deVilliers and Lin disclose the method according to claim 1, wherein one of the filling features(124) extends in a first direction, and has a uniform width in a second direction perpendicular to the first direction;wherein the first line pattern includes a first line segment that extends in the first direction;wherein the second line pattern(114)[0046] includes a second line segment that extends in the first direction, that corresponds in position to said one of the filling features(124);wherein the second line segment is adjacent to the first line segment in the second direction, and is spaced apart from the first line segment in the second direction by a distance ranging from 5 nm to 50 nm;wherein a length of the first line segment in the first direction is shorter than a length of the second line segment in the first direction, and the first line segment overlaps a portion of the second line segment when viewed in the second direction; andwherein the second line segment has a uniform width in the second direction.
Re claim 10 deVilliers and Lin disclose the method according to claim 1, wherein the metal lines extend in a first direction, and are arranged in a second direction perpendicular to the first direction;wherein the metal lines include a plurality of first metal lines that are arranged in the first line pattern, and a plurality of second metal lines that are arranged in the second line pattern(114)[0046]; andwherein two of the second metal lines are adjacent to each other in the second line pattern(114)[0046], and each of the first metal lines is disposed outside of a space between the two of the second metal lines.
Re claim 11 deVilliers and Lin disclose the method according to claim 1, wherein the semiconductor substrate(substrate)[0030,0050] includes a dielectric layer, and a masking layer disposed on the dielectric layer, the mandrel layer(111) being formed over the masking layer;wherein, in the first patterning process, the mandrel layer(111) is patterned to include a plurality of first openings that expose the masking layer;wherein, in the second patterning process[0043], the filling features(124) are patterned to include a plurality of second openings that expose the masking layer; andwherein the step of forming the metal lines includes:etching the masking layer with the mandrel layer(111), the spacers(left112/right112) and the filling features(124) thus patterned serving as a mask to form the first line pattern and the second line pattern(114)[0046] in the masking layer;etching the dielectric layer with the masking layer thus etched serving as a mask to form the first line pattern and the second line pattern(114)[0046] in the dielectric layer; anddepositing a metal material onto the dielectric layer thus etched to form the metal lines.
Re claim 12 deVilliers and Lin disclose the method according to claim 1, wherein the first patterning process and the second patterning process[0043] are performed separately.
Re claim 17 deVilliers discloses in Fig 11-14 a method for metal patterning, comprising steps of:forming a mandrel layer(111) onto a semiconductor substrate(substrate)[0030,0050], wherein the mandrel layer(111) is formed with a first mandrel opening(left/right opening of 111) and a second mandrel opening(left/right opening of 111) that extend in a first direction, that are adjacent to each other in a second direction perpendicular to the first direction, and that expose the semiconductor substrate(substrate)[0030,0050];forming a first spacer feature(left112/right112) onto a sidewall of the first mandrel opening(left/right opening of 111), and a second spacer feature(left112/right112) onto a sidewall of the second mandrel opening(left/right opening of 111), wherein the first spacer feature(left112/right112) is formed with a first spacer opening(left/right opening of left112/right112) that extends in the first direction and that exposes the semiconductor substrate(substrate)[0030,0050], and the second spacer feature(left112/right112) is formed with a second spacer opening(left/right opening of left112/right112) that extends in the first direction and that exposes the semiconductor substrate(substrate)[0030,0050];filling the first spacer opening(left/right opening of left112/right112) and the second spacer opening(left/right opening of left112/right112) in the first spacer opening(left/right opening of left112/right112) and the second spacer opening(left/right opening of left112/right112); patterning the first filling feature and the second filling feature to form a second line pattern(114)[0046]; andforming, in the semiconductor substrate(substrate)[0030,0050], metal lines that are arranged in the first line pattern and the second line pattern(114)[0046].
deVilliers does not disclose filling the first spacer opening(left/right opening of left112/right112) and the second spacer opening(left/right opening of left112/right112) with a reverse material to form a first filling feature and a second filling feature respectively in the first spacer opening(left/right opening of left112/right112) and the second spacer opening(left/right opening of left112/right112); patterning the mandrel layer(111) at a position between the first mandrel opening(left/right opening of 111) and the second mandrel opening(left/right opening of 111) to form a first line pattern;patterning the first filling feature and the second filling feature to form a second line pattern(114)[0046]; andforming, in the semiconductor substrate(substrate)[0030,0050], metal lines that are arranged in the first line pattern and the second line pattern(114)[0046].
Lin disclose a reverse material[0010 of Lin]; patterning the mandrel layer(124 of LIn) at a position between the first mandrel opening(left/right opening of 124 of LIn) and the second mandrel opening to form a first line pattern(line pattern)[0029 of Lin]; patterning the first filling feature(line pattern)[0029 of Lin] and the second filling feature to form a second line pattern(114)[0046]; and forming, in the semiconductor substrate(substrate)[0030,0050], metal lines[0020 of Lin] that are arranged in the first line pattern(line pattern)[0029 of Lin] and the second line pattern(114)[0046].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Lin to the teachings of deVilliers in order to improve processing performance (e.g., photolithographic resolution) may be prevented from achieving continuing improvement due to limitations of available fabrication technologies and equipment [0002, Lin]. In doing so, filling the first spacer opening(left/right opening of left112/right112) and the second spacer opening(left/right opening of left112/right112) with a reverse material[0010 of Lin] to form a first filling feature and a second filling feature respectively in the first spacer opening(left/right opening of left112/right112) and the second spacer opening(left/right opening of left112/right112); patterning the mandrel layer(124 of LIn) at a position between the first mandrel opening(left/right opening of 124 of LIn) and the second mandrel opening(left/right opening of 111) to form a first line pattern(line pattern)[0029 of Lin]; patterning the first filling feature(line pattern)[0029 of Lin] and the second filling feature to form a second line pattern(114)[0046]; andforming, in the semiconductor substrate(substrate)[0030,0050], metal lines[0020 of Lin] that are arranged in the first line pattern(line pattern)[0029 of Lin] and the second line pattern(114)[0046].
Re claim 18 deVilliers and Lin disclose the method according to claim 17, wherein the first spacer opening(left/right opening of left112/right112) has a uniform width in the second direction;wherein the metal lines include a first metal line that corresponds in position to a portion of the mandrel layer(111) disposed at the position between the first mandrel opening(left/right opening of 111) and the second mandrel opening(left/right opening of 111), and a second metal line that corresponds in position to the first filling feature;and wherein the first metal line is shorter than the second metal line, and the second metal line has a uniform width in the second direction.
Re claim 19 deVilliers and Lin disclose the method according to claim 17, wherein the second line pattern(114)[0046] includes a first line segment and a second line segment that correspond in position to the first filling feature, and a third line segment and a fourth line segment that correspond in position to the second filling feature;wherein the first line segment and the second line segment are aligned with and spaced apart from each other in the first direction, and the third line segment and the fourth line segment are aligned with and spaced apart from each other in the first direction; andwherein a line-end distance between the first line segment and the second line segment is different from a line-end distance between the third line segment and the fourth line segment.
Re claim 20 deVilliers and Lin disclose the method according to claim 17, wherein, in the step of patterning the mandrel layer(111), the first filling feature and the second filling feature are masked; andwherein, in the step of patterning the first filling feature and the second filling feature, a portion of the mandrel layer(111) that is disposed at the position between the first mandrel opening(left/right opening of 111) and the second mandrel opening(left/right opening of 111) is masked.
Re claim 21 deVilliers and Lin disclose the method according to claim 1, wherein the semiconductor substrate(substrate)[0030,0050] includes a masking layer, and the step of forming a plurality of spacers(left112/right112) includes:forming a spacer layer(122) conformally onto the mandrel layer(111) and in the mandrel recesses(recesses of 111);and etching the spacer layer(122) to reveal a top surface of the mandrel layer(111) and to form the spacers(left112/right112) in the spacer layer(122) and in the mandrel recesses(recesses of 111), wherein the spacer recess(left/right recess of left112/right112)es(recesses of 112) of the spacers(left112/right112) expose the masking layer.
Re claim 22 deVilliers and Lin disclose the method according to claim 17, wherein the semiconductor substrate(substrate)[0030,0050] includes a masking layer, and the step of forming the first spacer feature(left112/right112) and the second spacer feature(left112/right112) includes:depositing a conformal spacer layer(122) onto the mandrel layer(111) and in the first mandrel opening(left/right opening of 111) and the second mandrel opening(left/right opening of 111); andetching the conformal spacer layer(122) to reveal a top surface of the mandrel layer(111) and to form the first spacer opening(left/right opening of left112/right112) and the second spacer opening(left/right opening of left112/right112) in the spacer layer(122) and in the first mandrel opening(left/right opening of 111) and the second mandrel opening(left/right opening of 111), wherein the first spacer opening(left/right opening of left112/right112) and the second spacer opening(left/right opening of left112/right112) expose the masking layer.
Re claim 23 deVilliers discloses in Fig 11-14 a method for metal patterning, comprising steps of:forming a mandrel layer(111) over a semiconductor substrate(substrate)[0030,0050];patterning the mandrel layer(111) to form mandrel recesses(recesses of 111) in the mandrel layer(111);conformally depositing a spacer layer(122) over the mandrel layer(111) and in the mandrel recesses(recesses of 111);forming spacer feature(left112/right112)s(112) respectively in the mandrel recesses(recesses of 111), wherein the spacer feature(left112/right112)s(112) have spacer recess(left/right recess of left112/right112)es(recesses of 112) that expose the semiconductor substrate(substrate)[0030,0050];forming filling features(124) to fill the spacer recess(left/right recess of left112/right112)es(recesses of 112); patterning the filling features(124) to form a second line pattern(114)[0046]; and forming the second line pattern(114)[0046] in the semiconductor substrate(substrate)[0030,0050];
deVilliers does not disclose patterning the mandrel layer(111) to form a first line pattern; andforming the first line pattern and the second line pattern(114)[0046] in the semiconductor substrate(substrate)[0030,0050];and depositing a metal layer on the semiconductor substrate(substrate)[0030,0050] having the first line pattern and the second line pattern(114)[0046].
Lin disclose patterning the mandrel layer(124 of LIn) to form a first line pattern(line pattern)[0029 of Lin];
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Lin to the teachings of deVilliers in order to improve processing performance (e.g., photolithographic resolution) may be prevented from achieving continuing improvement due to limitations of available fabrication technologies and equipment [0002, Lin]. In doing so, andforming the first line pattern(line pattern)[0029 of Lin] and the second line pattern(114)[0046] in the semiconductor substrate(substrate)[0030,0050];and depositing a metal layer[0020 of Lin] on the semiconductor substrate(substrate)[0030,0050] having the first line pattern(line pattern)[0029 of Lin] and the second line pattern(114)[0046].
Re claim 24 deVilliers and Lin disclose the method according to claim 23, wherein the semiconductor substrate(substrate)[0030,0050] includes a masking layer, and the step of forming the spacer feature(left112/right112)s(112) includes:anisotropically etching the spacer layer(122) to remove portions of the spacer layer(122) that are over the mandrel layer(111) and portions of the spacer layer(122) that are disposed at a bottom of the mandrel recesses(recesses of 111), wherein remained portions of the spacer layer(122) that are formed on sidewalls of the mandrel recesses(recesses of 111) serve as the spacer feature(left112/right112)s(112),wherein the step of forming the filling features(124) includes:depositing a filling layer on the mandrel layer(111) and the spacer feature(left112/right112)s(112) and in the spacer recess(left/right recess of left112/right112)es(recesses of 112), wherein a material used in the filling layer is different from a material used in the spacer layer(122); andperforming a planarization process on the filling layer to reveal the mandrel layer(111) and the spacer feature(left112/right112)s(112),wherein the step of patterning the mandrel layer(111) includes:forming a first patterning layer over the mandrel layer(111), the spacer feature(left112/right112)s(112) and the filling features(124), wherein the first patterning layer covers the filling features(124), and has first openings that correspond to the first line pattern and that expose parts of the mandrel layer(111); andetching the parts of the mandrel layer(111) with the first patterning layer serving as an etching mask,wherein the step of patterning the filling features(124) includes forming a second patterning layer over the mandrel layer(111), the spacer feature(left112/right112)s(112) and the filling features(124), wherein the second patterning layer covers the mandrel layer(111), and has second openings that correspond to the second line pattern(114)[0046] and that expose parts of the filling features(124);and etching the parts of the filling features(124) with the second patterning layer serving as an etching mask, andwherein the step of forming the first line pattern and the second line pattern(114)[0046] in the semiconductor substrate(substrate)[0030,0050] includes:etching the semiconductor substrate(substrate)[0030,0050] with the mandrel layer(111), the spacer feature(left112/right112)s(112) and the filling features(124) serving as an etching mask, thereby forming substrate openings arranged in a pattern that is a combination of the first line pattern and the second line pattern(114)[0046].
Conclusion
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/PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812
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