DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election without traverse of Group II (method), Species B of Figs. 36A-36B, claims 14-20, new claims 21-25 and 27-32 in the reply filed on October 27, 2025 is acknowledged. Therefore, claims 14-25 and 27-32 are presented for examination.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 22 and 24 are rejected under 35 U.S.C. 102(a)(1) or (a)(2) as being anticipated by Sung et al. (US 2014/0252458, hereinafter Sung).
Regarding claim 22, Sung discloses for a method comprising that
forming a sidewall recess in a nanostructure (sidewall recess of channel region 31, Fig. 3I) by recessing a sidewall of the nanostructure (Fig. 3I);
forming a gate structure (gate dielectric 36/gate electrode 103, Fig. 3I) in the sidewall recess (sidewall recess of 31, Fig. 3I) and on the sidewall of the nanostructure (Fig. 3I);
depositing an inter-layer dielectric (first interlayer dielectric layer 38, Fig. 3I) around the gate structure (36/103, Fig. 3I);
forming a gate contact (gate contact 105, Fig. 3I) through the inter-layer dielectric (38, Fig. 3I) to contact a sidewall of the gate structure (sidewall of 103, Fig. 3I); and
forming a contact mask (hard mask layer 35, Fig. 3I) on the gate contact (105, Fig. 3I), because the hard mask layer 35 by Sung is formed indirectly on a sidewall of the gate contact 105 (Fig. 3I). Examiner notes that Applicants do not specifically claim a contact mask is formed directly on a top surface of the gate contact;
a top surface of the contact mask (top surface of hard mask layer 35, Fig. 3I) being coplanar with a top surface of the inter-layer dielectric (top surface of first interlayer dielectric layer 38, Fig. 3I).
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Regarding claim 24, Sung further discloses that forming the gate structure (36/103, Fig. 3I) comprises: depositing a gate dielectric layer (36, Fig. 3I) in the sidewall recess (sidewall recess of 31, Fig. 3I); depositing a gate electrode layer (103, Fig. 3I) on the gate dielectric layer (36, Fig. 3I) and in the sidewall recess (sidewall recess of 31, Fig. 3I); and removing a portion of the gate electrode layer outside of the sidewall recess, because Sung further discloses that “the gate electrode 103 is formed by depositing a first conductive layer over the substrate 101 and the pillar structure 102, and performing an etch-back process until the gate dielectric 36 over the substrate 101, between the pillar structure 102, is exposed” (emphasis added, [0045]), therefore, a portion of the gate electrode 103 is removed by the etch-back process by Sung.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 27 is rejected under 35 U.S.C. 103 as being unpatentable over by Sung et al. (US 2014/0252458, hereinafter Sung) in view of Dewey et al. (US 2020/0411692, hereinafter Dewey).
Regarding claim 27, Sung further discloses that after forming the contact mask (35, Fig. 3I), forming a front-side interconnect structure (word line 106, Fig. 3I) over the nanostructure (31, Fig. 3I) and the gate contact (105, Fig. 3I), because the word line 106 by Sung is positioned over the channel region 31 and gate contact 105 (Fig. 3I) and includes the barrier layer 41 and metal layer 42, and therefore it can correspond to the front-side interconnect structure in the claimed invention.
Sung does not explicitly disclose that forming a back-side interconnect structure below the nanostructure, the back-side interconnect structure comprising power rails.
However, Dewey discloses for transistor structures that the transistor device includes a vertical channel transistor (Fig. 14B) having the gate dielectric 315 and gate electrode 220 on a sidewall of the channel material 210, and the source/drain metallizations 250 are positioned above and below the channel material 210 (Fig. 14B). Dewey further discloses that the transistor device includes an back-end of line (BEOL) interconnection (1550, metallization levels M4/M5/M6, Fig. 15) over the transistor structure and a front-end of line (FEOL) interconnection and circuitry (metallization levels M1/M2/M3, 1581, Fig. 15) below the transistor structure, therefore, BEOL and FEOL by Dewey may correspond to the front-side interconnect structure and the back-side interconnect structure in the claimed invention, respectively; it is obvious to one of ordinary skill in the semiconductor art that the front-end of line structure to form active devices and back-end of line structure to form interconnects in a semiconductor memory device is widely used.
Since both Sung and Dewey teach a semiconductor device structure, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the semiconductor device would include the front-end of line structure to form active devices and back-end of line structure to form interconnects, as disclosed by Sung and Dewey.
Claims 14-15 and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over by Lin (US 2011/0079836) in view of Sung et al. (US 2014/0252458, hereinafter Sung).
Regarding claim 14, Lin discloses for a method comprising that
forming a nanostructure (top silicon island 10a/fin channel 10b, Fig. 7) between a first gate spacer (left spacer 24, Fig. 7) and a second gate spacer (right spacer 24, Fig. 7), because Applicants do not specifically claim what dimensions the nanostructure have and/or what material’s composition the nanostructure has, the top silicon island 10a and fin channel 10b by Lin are formed between the left and right spacers 24 (Fig. 7);
forming a sidewall recess (recess of fin channel 10b, Fig. 7) by recessing a sidewall of the nanostructure (sidewall of 10b, Fig. 7) from a sidewall of the first gate spacer (sidewall of left 24, Fig. 7) and from a sidewall of the second gate spacer (sidewall of right 24, Fig. 7);
forming a gate structure (gate dielectric layer 30/buried word line 40, Fig. 8) in the sidewall recess (recess of 10b, Fig. 8) and on the sidewall of the nanostructure (sidewall of 10b, Fig. 8);
depositing an inter-layer dielectric (trench fill dielectric 52, Fig. 9) around the gate structure (30/40, Fig. 9).
Lin does not explicitly disclose that forming a gate contact through the inter-layer dielectric to contact a sidewall of the gate structure.
However, Sung discloses for a semiconductor device having a vertical channel transistor that the vertical transistor includes a channel region 31 with a recessed sidewall (Fig. 3I), the gate electrode 103/gate dielectric 36 are formed in the recess of the channel region 31, and the first interlayer dielectric (ILD) layer 38 surrounds the gate structure 103/36. Sung further discloses that the gate contact 105 is formed through the first interlayer dielectric layer 38 so as to contact a sidewall of the gate electrode 103 (Fig. 3I), therefore, it would have been obvious to one of ordinary skill in the semiconductor art before the effective filing date of the claimed invention that a conductive contact, such as via or interconnect, would be formed through an interlayer dielectric layer (ILD) in the vertical transistor device of Lin to electrically contact the gate structure, as taught by Sung, in order to electrically connect the gate electrode to external circuitry and render the device operational.
Since both Lin and Sung teach a semiconductor device, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form a conductive contact in the vertical transistor device, as disclosed by Sung, in order to electrically connect the gate electrode to external circuitry and render the device operational.
Regarding claim 15, Sung further discloses that patterning a contact opening (contact hole 40, Fig. 3B) in the inter-layer dielectric (38, Fig. 3B), the contact opening (40, Fig. 3B) exposing the sidewall of the gate structure (sidewall of gate electrode 103, Fig. 3B), the gate contact being formed in the contact opening (Fig. 3C).
Regarding claim 17, Sung further discloses that forming an upper source/drain region (source region 32, Fig. 3I) above the nanostructure (above channel region 31, Fig. 3I); and forming a lower source/drain region (drain region between 101 and 102, Fig. 3I) below the nanostructure (below channel region 31, Fig. 3I), because Sung further discloses that “impurity ions, e.g., phosphor (P) and arsenic (As), are implanted into the substrate 101 between the pillar structures 102 to form an impurity region serving as a drain region of a vertical channel transistor” (emphasis added, [0046]), therefore, the drain region by Sung is formed in the substrate 101 below the channel region 31 (Fig. 3I), which corresponds to the lower source/drain region in the claimed invention.
Regarding claim 18, Lin further discloses that forming the gate structure (gate dielectric layer 30/buried word line 40, Fig. 8) comprises: depositing a gate dielectric layer (30, Fig. 8) in the sidewall recess (sidewall recess of 10a/10b, Fig. 8); depositing a gate electrode layer (40, Fig. 8) on the gate dielectric layer (30, Fig. 8) and in the sidewall recess (sidewall recess of 10a/10b, Fig. 8).
Lin does not explicitly disclose that removing a portion of the gate electrode layer outside of the sidewall recess with an etch-back process.
However, Sung further discloses “the gate electrode 103 is formed by depositing a first conductive layer over the substrate 101 and the pillar structure 102, and performing an etch-back process until the gate dielectric 36 over the substrate 101, between the pillar structure 102, is exposed” (emphasis added, [0045]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to perform an etch-back process to expose sidewall surface of gate dielectric layer and gate electrode, as disclosed by Sung.
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over by Lin (US 2011/0079836) in view of Sung et al. (US 2014/0252458, hereinafter Sung) as applied to claim 14 above, and further in view of Seo et al. (KR 100660891, hereinafter Seo).
Regarding claim 19, Lin in view of Sung does not explicitly disclose that the etch-back process selectively etches a material of the gate electrode layer at a faster rate than a material of the gate dielectric layer.
However, Seo discloses for a semiconductor memory device having a vertical channel that the memory device (Fig. 3w) includes that the gate insulating layer 222 and gate electrode 225 are formed in a recess of a sidewall of an upper channel portion 112. Seo further discloses that “the upper gate electrode layer is etched back using the upper gate insulating layer 212 as an etch stop layer” (page 5, lines 14-15, see attached machine-translated copy), therefore, one of ordinary skill in the semiconductor art would readily acknowledge that the etch-back process etches gate electrode layer at a faster rate the gate dielectric layer since the etch-back process would stop by the gate dielectric layer. Furthermore, selective etching process between gate electrode and gate dielectric is routine in the semiconductor manufacturing, and it is well-known that gate electrode materials are typically etched at a higher rate than gate dielectric material to protect the gate dielectric layer.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that gate electrode materials are etched at a faster rate than gate dielectric material to expose a sidewall of the gate electrode and gate dielectric layers, as disclosed by Seo, and this selective etching technique is widely used in semiconductor manufacturing.
Regarding claim 20, Lin in view of Sung and further in view of Seo does not explicitly disclose that the etch-back process comprises a dry etch performed using chlorine as an etchant.
However, chlorine-based etch chemistries were well known in the semiconductor manufacturing for use in dry etch processes to etch gate electrode materials. In particular, chlorine-based dry etch chemistries were commonly employed to selectively etch conductive gate materials in the presence of gate dielectric materials during gate patterning operations.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ a chlorine-based dry etch chemistry in the etch-back process of Lin, Sung, or Seo, in order to etch the gate electrode material with appropriate selectivity to the gate dielectric, as well known in the semiconductor device fabrication.
Allowable Subject Matter
Claims 16, 21, 23 and 25 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, because the prior arts cited in this Office Action do not teach the claimed limitations, “recessing a top surface of the gate contact” of claim 16, “an upper lightly doped source/drain region” and “a lower lightly doped source/drain region” of claim 21, “each oxidation cycle oxidizing a portion of the nanostructure and each etch cycle removing the oxidized portion of the nanostructure” of claim 23, “forming a second recess by recessing a top surface of the gate contact” of claim 25.
Claims 28-32 are allowed, because the prior arts cited in this Office Action do not teach the claimed limitations, “after forming the gate contact, forming a second source/drain region below the nanostructure” recited on lines 9-10 of claim 28, and claims 29-32 depend on claim 28.
Conclusion
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/WOO K LEE/Examiner, Art Unit 2815