DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Election
Applicant’s election without traverse of Species I in the reply filed on December 3rd, 2025 is acknowledged. By virtue of this election claims 1-8 and 21-32 are presented in the instant application. Claims 9-20 have been cancelled by the applicant.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8, 21-24, 26-30, and 32 are rejected under 35 U.S.C. 103 as being unpatentable over Essert et al. (US 7,494,389 B1; hereinafter Essert) in view of Sudo et al. (US 2007/0138624 A1; hereinafter Sudo).
With respect to claim 1, Essert discloses an electronic device assembly in Figs. 1-4 comprising:
a substrate 35 having a surface (see Fig. 4, column 3, line 25-33, and column 3, line 64 - column 4, line 16);
a patterned metal layer 30 disposed on the surface of the substrate 35 (see Figs. 3, 4, column 3, line 11-28, and column 3, line 64 - column 4, line 6);
a semiconductor device circuit (of 36) implemented on the patterned metal layer 30 (see Figs. 3, 4, column 3, line 34-38, and column 3, line 64 - column 4, line 6); and
a molded body 40 including a plurality of pins (press-fit connectors with first and second parts 1 and 2) (see Figs. 1-4, column 1, line 55 - column 2, line 19, and column 3, line 25-63), a pin of the plurality of pins including:
a first portion (part 1 of press-fit connector) extending out of a first surface (outside of 40) of the molded body 40, the first portion being externally accessible (see Figs. 1-4, column 1, line 55-61, column 2, line 1-8, column 3, line 39-63, and column 4, line 17-33); and
a second portion (part 2 of press-fit connector) extending out of a second surface (inside of 40) of the molded body 40 opposite the first surface (outside of 40), the second portion: being internal in the electronic device assembly; electrically coupled with the patterned metal layer 30; and electrically continuous with the first portion (part 1 of press-fit connector) (see Figs. 1-4, column 1, line 55 - column 2, line 19, column 3, line 11 - column 4, line 33).
Essert does not explicitly disclose wherein the plurality of pins are signal pins.
Sudo discloses an electronic device assembly in at least Figs . 14 and 15 wherein a plurality of pins 16 are signal pins (see Fig. 14 and paragraphs 83, 84).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the plurality of pins of Essert would be signal pins as taught by Sudo because it is well known in the art that such electronic device assemblies include a plurality of DC (direct current) source terminals 12a, AC (alternate current) drive terminals 12b, and signal terminals 16 for proper functionality (see MPEP 2144 I and paragraph 84 of Sudo).
With respect to claim 2, the combination of Essert and Sudo discloses the electronic device assembly of claim 1, wherein the second portion (part 2 of press-fit connector) of the signal pin includes a plurality of bends (see Essert: Figs. 1-4, column 1, line 55-67, and column 2, line 38-47; note bends in 2 between ends 21 and 22. See Sudo: Fig. 14 and paragraph 84 for teaching of signal pins).
With respect to claim 3, the combination of Essert and Sudo discloses the electronic device assembly of claim 1, wherein the molded body 40 includes a plurality of alignment features 42 configured to position the electronic device assembly in an encapsulation molding tool (see Essert: Fig. 4, column 2, line 57-67, and column 4, line 7-16; the limitation “configured to position the electronic device assembly in an encapsulation molding tool” is an intended use limitation, and it has been held by the courts that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations (see MPEP 2114 II)).
With respect to claim 4, the combination of Essert and Sudo discloses the electronic device assembly of claim 3, wherein the plurality of alignment features 42 includes at least one of: a plurality of recesses in the first surface (outside of 40) of the molded body 40; or a plurality of through-holes in the molded body 40 (see Essert: Fig. 4 and column 4, line 7-16).
With respect to claim 5, the combination of Essert and Sudo discloses the electronic device assembly of claim 1, wherein the molded body 40 further includes a plurality of power tabs (other press-fit connectors with first and second parts 1 and 2), a power tab of the plurality of power tabs including: a first portion (part 1 of press-fit connector) arranged in a plane parallel to the first surface (outside of 40) of the molded body 40 (see Essert: Figs. 1-4, column 1, line 55-61, column 2, line 1-8, column 3, line 39-63, and column 4, line 17-33; note part of 1 is parallel to outside surface of 40 at side wall 41); and a second portion (part 2 of press-fit connector) orthogonal to the first portion (part 1 of press-fit connector), the second portion of the power tab: extending from the second surface (inside of 40) of the molded body 40; being electrically continuous with the first portion (part 1 of press-fit connector) of the power tab; and being electrically coupled with the patterned metal layer 30 (see Essert: Figs. 1-4, column 1, line 55 - column 2, line 19, column 3, line 1 - column 4, line 33; as seen in the Figs part of 2 is perpendicular to part 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the plurality of tabs of Essert would be power tabs as taught by Sudo because it is well known in the art that such electronic device assemblies include a plurality of DC (direct current) source terminals 12a, AC (alternate current) drive terminals 12b, and signal terminals 16 for proper functionality (see MPEP 2144 I and paragraph 84 of Sudo).
With respect to claim 6, the combination of Essert and Sudo discloses the electronic device assembly of claim 5, wherein the first portion (part 1 of press-fit connector) of the power tab is disposed in a slot defined in the molded body 40 (see Essert: Figs. 3, 4, and column 3, line 25-56).
With respect to claim 7, the combination of Essert and Sudo discloses the electronic device assembly of claim 5, wherein the power tab (other press-fit connectors with first and second parts 1 and 2) is a single body that is bent to define the first portion (part 1 of press-fit connector) of the power tab and the second portion (part 2 of press-fit connector) of the power tab (see Essert: Figs. 1-4, column 1, line 55 - column 2, line 19, column 2, line 38-47, column 3, line 25-63, and column 4, line 22-33; parts 1 and 2 are mechanically joined to form one press-fit connector; note bends in part 2).
With respect to claim 8, the combination of Essert and Sudo discloses the electronic device assembly of claim 5, wherein the second portion (part 2 of press-fit connector) of the power tab (other press-fit connectors with first and second parts 1 and 2) is a conductive post that electrically couples the first portion (part 1 of press-fit connector) of the power tab with the patterned metal layer 30 (see Essert: Figs. 3, 4, column 2, line 9-19, and column 3, line 11-33).
With respect to claim 21, Essert discloses an electronic device assembly in Figs. 1-4 comprising:
a semiconductor device circuit (of 36) coupled to a patterned metal layer 30 of a substrate 35 (see Figs. 3, 4, and column 3, line 33-38, and column 3 line 64 - column 4, line 16);
a molded body 40 coupled to the substrate 35 and disposed over the semiconductor device circuit (of 36), the molded body 40 including a plurality of pins (press-fit connectors with first and second parts 1 and 2) (see Figs. 1-4, column 1, line 55 - column 2, line 19, column 3, line 25-63, and column 4, line 7-16), a pin of the plurality of pins including:
a first portion (part 1 of press-fit connector) extending out of a first surface (outside of 40) of the molded body 40, the first portion being externally accessible (see Figs. 1-4, column 1, line 55-61, column 2, line 1-8, column 3, line 39-63, and column 4, line 17-33); and
a second portion (part 2 of press-fit connector) extending out of a second surface (inside of 40) of the molded body 40 opposite the first surface (outside of 40), the second portion including at least one bend (see Figs. 1-4, (see Figs. 1-4, column 1, line 55 - column 2, line 19, column 2, line 38-47, and column 3, line 11 - column 4, line 33; note bends in 2 between ends 21 and 22); and
molding compound (insulating soft pottant) at least partially encapsulating the substrate 35 and the molded body 40 (see Fig. 4 and column 4, line 7-16).
Essert does not explicitly disclose wherein the plurality of pins are signal pins.
Sudo discloses an electronic device assembly in at least Figs . 14 and 15 wherein a plurality of pins 16 are signal pins (see Fig. 14 and paragraphs 83, 84).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the plurality of pins of Essert would be signal pins as taught by Sudo because it is well known in the art that such electronic device assemblies include a plurality of DC (direct current) source terminals 12a, AC (alternate current) drive terminals 12b, and signal terminals 16 for proper functionality (see MPEP 2144 I and paragraph 84 of Sudo).
With respect to claim 22, the combination of Essert and Sudo discloses the electronic device assembly of claim 21, wherein the second portion (part 2 of press-fit connector) includes a plurality of bends (see Essert: Figs. 1-4, column 1, line 55-67, and column 2, line 38-47; note bends in 2 between ends 21 and 22).
With respect to claim 23, the combination of Essert and Sudo discloses the electronic device assembly of claim 21, wherein the second portion (part 2 of press-fit connector) is axially offset from the first portion (part 1 of press-fit connector) (see Essert: Figs. 1-4, column 1, line 55 - column 2, line 19, column 3, line 1 - column 4, line 33; note part 2 within interior of housing is offset from part 1).
With respect to claim 24, the combination of Essert and Sudo discloses the electronic device assembly of claim 21, wherein the second portion (part 2 of press-fit connector) is electrically coupled with a pad (of 30) of the patterned metal layer 30, and wherein the second portion (part 2 of press-fit connector) is electrically continuous with the first portion (part 1 of press-fit connector) (see Essert: Figs. 1-4, column 1, line 55 - column 2, line 19, column 3, line 11 - column 4, line 33).
With respect to claim 26, the combination of Essert and Sudo discloses the electronic device assembly of claim 21, wherein the molded body 40 further includes a plurality of power tabs (other press-fit connectors with first and second parts 1 and 2) (see Essert: Figs. 1-4, column 1, line 55 - column 2, line 19, and column 3, line 25-63).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the plurality of tabs of Essert would be power tabs as taught by Sudo because it is well known in the art that such electronic device assemblies include a plurality of DC (direct current) source terminals 12a, AC (alternate current) drive terminals 12b, and signal terminals 16 for proper functionality (see MPEP 2144 I and paragraph 84 of Sudo).
With respect to claim 27, the combination of Essert and Sudo discloses the electronic device assembly of claim 26, wherein a power tab of the plurality of power tabs includes: a first portion (part 1 of press-fit connector) arranged in a plane parallel to the first surface (outside of 40) of the molded body 40 (see Essert: Figs. 1-4, column 1, line 55-61, column 2, line 1-8, column 3, line 39-63, and column 4, line 17-33; note part of 1 is parallel to outside surface of 40 at side wall 41); and a second portion (part 2 of press-fit connector) orthogonal to the first portion (part 1 of press-fit connector), the second portion of the power tab: extending from the second surface (inside of 40) of the molded body 40; being electrically continuous with the first portion (part 1 of press-fit connector) of the power tab; and being electrically coupled with the patterned metal layer 30 (see Essert: Figs. 1-4, column 1, line 55 - column 2, line 19, column 3, line 1 - column 4, line 33; as seen in the Figs part of 2 is perpendicular to part 1).
With respect to claim 28, the combination of Essert and Sudo discloses the electronic device assembly of claim 21, the signal pin including a third portion within the molded body 40, the third portion (part of 1 within 40) extending in plane parallel to the first surface (outside of 40) and connecting the first portion (part 1 of press-fit connector) to the second portion (part 2 of press-fit connector) (see Essert: Figs. 1-4, column 1, line 55 - column 2, line 19, column 2, line 57-67, and column 3, line 25-63).
With respect to claim 29, the combination of Essert and Sudo discloses the electronic device assembly of claim 21, wherein the molded body 40 includes a plurality of alignment features 42 configured to position the electronic device assembly in an encapsulation molding tool (see Essert: Fig. 4, column 2, line 57-67, and column 4, line 7-16; the limitation “configured to position the electronic device assembly in an encapsulation molding tool” is an intended use limitation, and it has been held by the courts that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations (see MPEP 2114 II)).
With respect to claim 30, Essert discloses a method in Figs. 1-4 comprising:
coupling a semiconductor device circuit (of 36) to a patterned metal layer 30 of a substrate 35 (see Figs. 3, 4, and column 3, line 33-38, and column 3 line 64 - column 4, line 16);
coupling a molded body 40 to the substrate 35 and disposed over the semiconductor device circuit (of 36), the molded body 40 including a plurality of pins (press-fit connectors with first and second parts 1 and 2) (see Figs. 1-4, column 1, line 55 - column 2, line 19, column 3, line 25-63, and column 4, line 7-16), a pin of the plurality of pins including:
a first portion (part 1 of press-fit connector) extending out of a first surface (outside of 40) of the molded body 40, the first portion being externally accessible (see Figs. 1-4, column 1, line 55-61, column 2, line 1-8, column 3, line 39-63, and column 4, line 17-33); and
a second portion (part 2 of press-fit connector) extending out of a second surface (inside of 40) of the molded body 40 opposite the first surface (outside of 40), the second portion including at least one bend (see Figs. 1-4, (see Figs. 1-4, column 1, line 55 - column 2, line 19, column 2, line 38-47, and column 3, line 11 - column 4, line 33; note bends in 2 between ends 21 and 22); and
encapsulating at least a portion of the substrate 35 and the molded body 40 in a molding compound (insulating soft pottant) (see Fig. 4 and column 4, line 7-16).
Essert does not explicitly disclose wherein the plurality of pins are signal pins.
Sudo discloses a method in at least Figs . 14 and 15 wherein a plurality of pins 16 are signal pins (see Fig. 14 and paragraphs 83, 84).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the plurality of pins of Essert would be signal pins as taught by Sudo because it is well known in the art that methods of such electronic device assemblies include a plurality of DC (direct current) source terminals 12a, AC (alternate current) drive terminals 12b, and signal terminals 16 for proper functionality (see MPEP 2144 I and paragraph 84 of Sudo).
With respect to claim 32, the combination of Essert and Sudo discloses the method of claim 30, wherein the molded body 40 further includes a plurality of power tabs (other press-fit connectors with first and second parts 1 and 2) (see Essert: Figs. 1-4, column 1, line 55 - column 2, line 19, and column 3, line 25-63), wherein a power tab of the plurality of power tabs includes: a first portion (part 1 of press-fit connector) arranged in a plane parallel to the first surface (outside of 40) of the molded body 40 (see Essert: Figs. 1-4, column 1, line 55-61, column 2, line 1-8, column 3, line 39-63, and column 4, line 17-33; note part of 1 is parallel to outside surface of 40 at side wall 41); and a second portion (part 2 of press-fit connector) orthogonal to the first portion (part 1 of press-fit connector), the second portion of the power tab extending from the second surface (inside of 40) of the molded body 40 and contacting the substrate 35 (see Essert: Figs. 1-4, column 1, line 55 - column 2, line 19, column 3, line 1 - column 4, line 33; as seen in the Figs part of 2 is perpendicular to part 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the plurality of tabs of Essert would be power tabs as taught by Sudo because it is well known in the art that methods of such electronic device assemblies include a plurality of DC (direct current) source terminals 12a, AC (alternate current) drive terminals 12b, and signal terminals 16 for proper functionality (see MPEP 2144 I and paragraph 84 of Sudo).
Claims 25 and 31 are rejected under 35 U.S.C. 103 as being unpatentable over Essert et al. (US 7,494,389 B1; hereinafter Essert) in view of Sudo et al. (US 2007/0138624 A1; hereinafter Sudo) as applied to claims 21 or 30 above, and further in view of Nonaka (US 2023/0269868 A1).
With respect to claim 25, the combination of Essert and Sudo discloses the electronic device assembly of claim 21.
The combination does not disclose wherein the first portion extends through the molding compound.
Nonaka discloses an electronic device assembly in at least Fig. 1 wherein a first portion (part of 40a, 40b outside of 50 and 51) extends through a molding compound 60 (see Fig. 1 and paragraphs 44, 62, 63, 67).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the first portion of Essert and Sudo would extend through the molding compound as taught by Nonaka so as to further improve the dielectric strength of the assembly (see MPEP 2144 I).
With respect to claim 31, the combination of Essert and Sudo discloses the method of claim 30.
The combination does not disclose wherein the first portion extends through the molding compound.
Nonaka discloses a method for an electronic device assembly in at least Fig. 1 wherein a first portion (part of 40a, 40b outside of 50 and 51) extends through a molding compound 60 (see Fig. 1 and paragraphs 44, 62, 63, 67).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the first portion of Essert and Sudo would extend through the molding compound as taught by Nonaka so as to further improve the dielectric strength of the assembly (see MPEP 2144 I).
Citation of Pertinent Prior Art
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure because each reference disclose an electronic device assembly and method similar to that of the claimed invention: US 20160247735 A1, US 20170170084 A1, US 20190348342 A1, and US 20230268239 A1.
Inquiry
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JORDAN M KLEIN whose telephone number is (571)270-7544. The examiner can normally be reached 9:00 am - 5:00 pm.
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/J.M.K/Examiner, Art Unit 2893
/SUE A PURVIS/ Supervisory Patent Examiner, Art Unit 2893