DETAILED ACTION Election /Restrictions Applicant’s election without traverse of claims 15-3 4 with claims 21-3 4 are newly added in the reply filed on 01/02/2026 is acknowledged . Information Disclosure Statement The information disclosure statement (IDS) submitted on 11/01/2024 is filed after the mailing date of the application. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. Claim s 15- 16 , 26, 31 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Lin et al., U.S. Pub. No. 2022/0270893 . Regarding claim 15 , Lin discloses: A method for forming a chip package structure, comprising (Figs. 1A-2C): bonding a chip package to a wiring substrate 160 (Fig. 2B), bonding a first anti-warpage structure to the wiring substrate, wherein the first anti-warpage structure is made of a semiconductor material and electrically insulated from the chip package and a wiring structure of the wiring substrate (Figs. 1B, 2B; the ring structure 210 and ring dam 240 act as an anti-warpage, and electrically insulated from layer 160 by adhesive layer 180 (Fig. 1C) and electrically insulated from the chip package 122 by a trench between layers 210 and 140 (Fig. 1C), See Fig. 2B. bonding a heat dissipation structure 250 to the wiring substrate, wherein the heat dissipation structure surrounds the chip package and the first anti-warpage structure (Fig. 1D, Fig. 2B) . Regarding claim 16, Lin discloses forming an adhesive layer over the firs anti-warpage structure, wherein the heat dissipation structure 250 has a lid, and the adhesive layer 220 is bonded to the lid after the heat dissipation structure is bonded to the wiring structure. Regarding claim 26, Lin discloses wherein the first anti-warpage structure is between a first corner portion of the chip package and a second corner portion of the wiring substrate (Fig. 2B). Regarding claim 31 , Lin discloses: A method for forming a chip package structure, comprising (Figs. 1A-2C): bonding a chip package to a wiring substrate 160 (Fig. 2B), bonding a first anti-warpage structure to the wiring substrate, wherein the first anti-warpage structure is made of a semiconductor material and electrically insulated from the chip package and a wiring structure of the wiring substrate (Figs. 1B, 2B; the ring structure 210 and ring dam 240 act as an anti-warpage, and electrically insulated from layer 160 by adhesive layer 180 (Fig. 1C) and electrically insulated from the chip package 122 by a trench between layers 210 and 140 (Fig. 1C), See Fig. 2B. bonding a heat dissipation structure 250 to the chip package and the and the first anti-warpage structure (Fig. 1D, Fig. 2B). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim s 19 -25, 27 -30, 32-3 4 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al., U.S. Pub. No. 2022/0270893. Regarding claim s 19 -2 1 , Lin discloses bonding a second anti-warpage structure to the wiring substrate, wherein the second anti-warpage structure (the other ring 210 and ring dam 240 that are on the other side of the chip package) is made of the semiconductor material and electrically insulated from the chip package and the wiring structure of the wiring substrate. (Figs. 1B, 2B; the ring structure 210 and ring dam 240 act as an anti-warpage, and electrically insulated from layer 160 by adhesive layer 180 (Fig. 1C) and electrically insulated from the chip package 122 by a trench between layers 210 and 140 (Fig. 1C). Still regarding claims 19-2 1 , Lin fails to disclose the second anti-warpage is smaller or narrower than the first nor the shape of the first anti-warpage structure. It would have been obvious to one having ordinary skill in the art at the time the invention was made to modify and obtain variety size and shape of the anti-warpage layers. The selection of such parameters such as energy, concentration, temperature, time, molar fraction, depth, thickness, etc. , would have been obvious and involve routine optimization which has been held to be within the level of ordinary skill in the art. "Normally, it is to be expected that a change in energy, concentration, temperature, time, molar fraction, depth, thickness, etc. , or in conbination of the parameters would be an unpatentable modification. Under some circumstances, however, changes such as these may impart patentability to a process if the particular ranges claimed produce a new and unexpected result which is different in kind and not merely degree from the results of the prior art ... such ranges are termed "critical ranges and the applicant has the burden of proving such criticality.... More particularly, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller 105 USPQ233, 255 (CCPA 1955). See also In re Waite 77 USPQ 586 (CCPA 1948); In re Scherl 70 USPQ 204 (CCPA 1946); In re Irmscher 66 USPQ 314 (CCPA 1945); In re Norman 66 USPQ 308 (CCPA 1945); In re Swenson 56 USPQ 372 (CCPA 1942); In re Sola 25 USPQ 433 (CCPA 1935); In re Dreyfus 24 USPQ 52 (CCPA 1934). Regarding claim 22, Lin discloses the first anti-warpage is bonded to the wiring substrate through a first adhesive layer 180 (Fig. 1C) but fails to disclose the order of the steps that the adhesive layer is connected after the first anti-warpage is bonded to the wiring substrate. It would have been obvious to one having ordinary skill in the art at the time the invention was made that the orders of the steps can be change by routine experimentation if the final result yield the same and modification of the order of the steps would be unpatentable . Regarding claim 23, Lin discloses forming a second adhesive layer 220 over the anti-warpage structure before the heat dissipation structure is bonded to the wiring substrate (Fig. 1C) and the heat dissipation structure has a lid (Fig. 1D) and the second adhesive layer is bonded to the lid after the heat dissipation structure is bonded to the wiring (Figs. 1C, 1C). Regarding claims 24-25, Lin fails to disclose the second anti-warpage is thicker than the first nor the shape of the second anti-warpage structure. It would have been obvious to one having ordinary skill in the art at the time the invention was made to modify and obtain variety size and shape of the anti-warpage layers. The selection of such parameters such as energy, concentration, temperature, time, molar fraction, depth, thickness, etc. , would have been obvious and involve routine optimization which has been held to be within the level of ordinary skill in the art. "Normally, it is to be expected that a change in energy, concentration, temperature, time, molar fraction, depth, thickness, etc. , or in conbination of the parameters would be an unpatentable modification. Under some circumstances, however, changes such as these may impart patentability to a process if the particular ranges claimed produce a new and unexpected result which is different in kind and not merely degree from the results of the prior art ... such ranges are termed "critical ranges and the applicant has the burden of proving such criticality.... More particularly, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller 105 USPQ233, 255 (CCPA 1955). See also In re Waite 77 USPQ 586 (CCPA 1948); In re Scherl 70 USPQ 204 (CCPA 1946); In re Irmscher 66 USPQ 314 (CCPA 1945); In re Norman 66 USPQ 308 (CCPA 1945); In re Swenson 56 USPQ 372 (CCPA 1942); In re Sola 25 USPQ 433 (CCPA 1935); In re Dreyfus 24 USPQ 52 (CCPA 1934). Regarding claim 27 , Lin discloses: A method for forming a chip package structure, comprising (Figs. 1A-2C): bonding a chip package to a wiring substrate 160 (Fig. 2B), bonding a first anti-warpage structure to the wiring substrate, wherein the first anti-warpage structure is made of a semiconductor material and electrically insulated from the chip package and a wiring structure of the wiring substrate (Figs. 1B, 2B; the ring structure 210 and ring dam 240 act as an anti-warpage, and electrically insulated from layer 160 by adhesive layer 180 (Fig. 1C) and electrically insulated from the chip package 122 by a trench between layers 210 and 140 (Fig. 1C), See Fig. 2B. bonding a second anti-warpage to the wiring substrate, wherein the second anti-warpage structure is electrically insulated from the chip package (the other 210/240 from the other side of the chip package) bonding a heat dissipation structure 250 to the wiring substrate, wherein the heat dissipation structure surrounds the chip package and the first anti-warpage structure (Fig. 1D, Fig. 2B). Lin fails to disclose the second anti-warpage structure is wider than the first. However, it would have been obvious to one having ordinary skill in the art at the time the invention was made to modify and obtain variety size and shape of the anti-warpage layers. The selection of such parameters such as energy, concentration, temperature, time, molar fraction, depth, thickness, etc. , would have been obvious and involve routine optimization which has been held to be within the level of ordinary skill in the art. "Normally, it is to be expected that a change in energy, concentration, temperature, time, molar fraction, depth, thickness, etc. , or in conbination of the parameters would be an unpatentable modification. Under some circumstances, however, changes such as these may impart patentability to a process if the particular ranges claimed produce a new and unexpected result which is different in kind and not merely degree from the results of the prior art ... such ranges are termed "critical ranges and the applicant has the burden of proving such criticality.... More particularly, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller 105 USPQ233, 255 (CCPA 1955). See also In re Waite 77 USPQ 586 (CCPA 1948); In re Scherl 70 USPQ 204 (CCPA 1946); In re Irmscher 66 USPQ 314 (CCPA 1945); In re Norman 66 USPQ 308 (CCPA 1945); In re Swenson 56 USPQ 372 (CCPA 1942); In re Sola 25 USPQ 433 (CCPA 1935); In re Dreyfus 24 USPQ 52 (CCPA 1934). Regarding claim 28, Lin discloses the first anti-warpage is made of semiconductor material [0062]. Regarding claims 29-30, 32-33, Lin fails to disclose the thicknesses or lengths of the anti-warpage structures. However, i t would have been obvious to one having ordinary skill in the art at the time the invention was made to modify and obtain variety size and shape of the anti-warpage layers. The selection of such parameters such as energy, concentration, temperature, time, molar fraction, depth, thickness, etc. , would have been obvious and involve routine optimization which has been held to be within the level of ordinary skill in the art. "Normally, it is to be expected that a change in energy, concentration, temperature, time, molar fraction, depth, thickness, etc. , or in conbination of the parameters would be an unpatentable modification. Under some circumstances, however, changes such as these may impart patentability to a process if the particular ranges claimed produce a new and unexpected result which is different in kind and not merely degree from the results of the prior art ... such ranges are termed "critical ranges and the applicant has the burden of proving such criticality.... More particularly, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller 105 USPQ233, 255 (CCPA 1955). See also In re Waite 77 USPQ 586 (CCPA 1948); In re Scherl 70 USPQ 204 (CCPA 1946); In re Irmscher 66 USPQ 314 (CCPA 1945); In re Norman 66 USPQ 308 (CCPA 1945); In re Swenson 56 USPQ 372 (CCPA 1942); In re Sola 25 USPQ 433 (CCPA 1935); In re Dreyfus 24 USPQ 52 (CCPA 1934). Regarding claim 34, Lin discloses the chip oackage has a sidewall, the first corner portion and second corner portion of the chip package are on opposite sides of the sidewall, the second anti-warpage structure is between the first corner portion and the second corner portion and extends along the sidewall and the second anti-warpage structure is spaced apart from the chip package (the second anti-warpage is on the other side of the chip package and spaced apart from it, Fig. 2B). Claims 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al., U.S. Pub. No. 2022/0270893, in view of Park et al., U.S. Pub. No. 2022/0199577. Lin disclose s the use of adhesive to bond the anti-warpage to the wiring substrate but fails to disclose bonding the first anti warpage structure to the wiring substrate through a first conductive bump or a second conductive bump, wherein the conductive bump is bonded to a dummy pad of the wiring substrate. Park discloses the use of bump 42 connected to a pad 13 on the wiring substrate 14 of substrate 11 . It would have been obvious to one having ordinary skill in the art at the time the invention was made to apply Park ’s method in the method of Lin in order to improve reliability, obtain a better performance, lower resistance, have a short and direct bonding , and yield better power delivery. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT THAO P LE whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)272-1785 . The examiner can normally be reached on Monday-Friday 9AM-6PM FILLIN "Work schedule?" \* MERGEFORMAT . If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached on 571-272- 2266 . The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). /THAO P LE/ Primary Examiner, Art Unit 2818