DETAILED ACTION
Claims 15-24, 26-29, 31-32, 34-37 are pending.
Applicant’s arguments on 06/29/2026 are found persuasive. Accordingly, the Examiner withdraws the previous rejection. However, the arguments are rendered moot in view of the new ground of rejection set fourth herein.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 15-24, 26-29, 31-32, 34-37 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al., U.S. Pub. No. 2022/0270893, in view of Choi, U.S. Pub. No. 2019/0287873.
Regarding claim 15, Lin discloses a method for forming a chip package structure, comprising (Figs. 1A-2C),
bonding a chip package to a wiring substrate 160 (Fig. 2B),
bonding a first anti-warpage structure to the wiring substrate (Figs. 1B, 2B, the ring structure 210 and ring dam 240 act as an anti-warpage, and insulated from layer 160 by adhesive layer 180 (Fig. 1C) and electrically insulated from the chip package 122 by a trench between layers 210 and 240.
bonding a heat dissipation structure 250 to the wiring substrate, wherein the heat dissipation structure surrounds the chip package and the first anti-warpage structure (Figs. 1D, 2B).
Lin discloses the claimed anti-warpage structure (210 + 240), but fail to disclose that the anti-warpage structure is made of a semiconductor material.
Choi teaches the use of dummy structures 120 (Fig. 6a) comprising semiconductor material, such as silicon, in a semiconductor package for reducing warpage associated with semiconductor dies. It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the anti-warpage structure of Lin to comprise the semiconductor material taught by Choi in order to provide structural support and reduce warpage of the semiconductor package.
Regarding claim 16, Lin discloses forming an adhesive layer over the first anti-warpage structure, wherein the heat dissipation structure 250 has a lid, and the adhesive layer 220 is bonded to the lid after the heat dissipation structure is bonded to the wiring structure.
Regarding claims 17-18, Choi discloses bonding the first anti warpage structure to the wiring substrate through a first conductive bump or a second conductive bump, wherein the conductive bump is bonded to a dummy pad of the wiring substrate (Choi’s Fig. 3F).
Regarding claims 19-21, Lin discloses bonding a second anti-warpage structure to the wiring substrate, wherein the second anti-warpage structure (the other ring 210 and ring dam 240 that are on the other side of the chip package) is made of the semiconductor material and electrically insulated from the chip package and the wiring structure of the wiring substrate (Figs. 1B, 2B, the ring structure 210 and ring dam 240 act as an anti-warpage, and insulated from layer 160 by adhesive layer 180 (Fig. 1C) and insulated from the chip package 122 by a trench between layers 210 and 140 (Fig. 1C).
Lin fails to disclose that the anti-warpage structure is made of a semiconductor material.
Choi teaches the use of dummy structures 120 (Fig. 6a) comprising semiconductor material, such as silicon, in a semiconductor package for reducing warpage associated with semiconductor dies. It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the anti-warpage structure of Lin to comprise the semiconductor material taught by Choi in order to provide structural support and reduce warpage of the semiconductor package.
Still regarding claims 19-21, Lin and Choi fail to disclose the second anti-warpage is smaller or narrower than the first nor the shape of the first anti-warpage structure. However, it would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the dimension and/or shape of the structure to obtain the claimed configuration because the modification constitutes no more than a change in dimension and shape and would have yielded predictable results. Changes in size or dimensions do not ordinary impact patentability. See in re Rose, 220 F.2d. 459 (CCPA 1955).
Regarding claim 22, Lin and Choi fail to disclose the order of the steps that the adhesive layer is connected after the first anti-warpage is bonded to the wiring substrate. It would have been obvious to one having ordinary skill in the art at the time the invention was made that the orders of the steps can be change by routine experimentation if the final result yield the same and modification of the order of the steps would be unpatentable.
Regarding claim 23, Lin discloses forming a second adhesive layer 220 over the anti-warpage structure before the heat dissipation structure is bonded to the wiring substrate (Fig. 1C), and the heat dissipation structure has a lid (Fig. 1D) and the second adhesive layer is bonded to the lid after the heat dissipation structure is bonded to the wiring (Fig. 1C).
Regarding claim 24, Lin and Choi fail to disclose the second anti-warpage is thicker than the first anti-warpage. However, it would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the dimension and/or shape of the structure to obtain the claimed configuration because the modification constitutes no more than a change in dimension and shape and would have yielded predictable results. Changes in size or dimensions do not ordinary impact patentability. See in re Rose, 220 F.2d. 459 (CCPA 1955).
Regarding claim 26, Lin discloses wherein the first anti-warpage structure is between a first corner portion of the chip package and a second corner portion of the wiring substrate (Fig. 2B).
Regarding claim 27, Lin discloses a method for forming a chip package structure, comprising (Figs. 1A-2C):
bonding a chip package to a wiring substrate 160 (Fig. 2B),
bonding a first anti-warpage structure to the wiring substrate, electrically insulated from the chip package and a wiring structure of the wring substrate (Fig. 1B, 2B, the ring structure 210 and ring dam 240 act as an anti-warpage, and electrically insulated from layer 160 by adhesive layer 180 (Fig. 1C) and electrically insulated from the chip package 122 by a trench between layers 210 and 140 (Fig. 1C, 2B),
bonding a second anti-warpage to the wring substrate, wherein the second anti-warpage structure is electrically insulated from the chip package (the other 210/240 from the other side of the chip package),
bonding a heat dissipation structure 250 to the wiring substrate, wherein the heat dissipation structure surrounds the chip package and the first anti-warpage structure (Fig. 1D, Fig. 2B).
Lin discloses the claimed anti-warpage structure (210 + 240), but fail to disclose that the anti-warpage structure is made of a semiconductor material.
Choi teaches the use of dummy structures 120 (Fig. 6a) comprising semiconductor material, such as silicon, in a semiconductor package for reducing warpage associated with semiconductor dies. It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the anti-warpage structure of Lin to comprise the semiconductor material taught by Choi in order to provide structural support and reduce warpage of the semiconductor package.
Lin fails to disclose the second anti-warpage structure is wider than the first.
However, it would have been obvious to one having ordinary skill in the art at the time the invention was made to modify and obtain variety size and shape of the anti-warpage layers. The selection of the parameters such as energy, concentration, temperature, time, molar fraction, depth, thickness, etc., would have been obvious and involve routine optimization which has been held to be within the level of ordinary skill in the art. "Normally, it is to be expected that a change in energy, concentration, temperature, time, molar fraction, depth, thickness, etc., or in conbination of the parameters would be an unpatentable modification. Under some circumstances, however, changes such as these may impart patentability to a process if the particular ranges claimed produce a new and unexpected result which is different in kind and not merely degree from the results of the prior art ... such ranges are termed "critical ranges and the applicant has the burden of proving such criticality.... More particularly, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller 105 USPQ233, 255 (CCPA 1955). See also In re Waite 77 USPQ 586 (CCPA 1948); In re Scherl 70 USPQ 204 (CCPA 1946); In re Irmscher 66 USPQ 314 (CCPA 1945); In re Norman 66 USPQ 308 (CCPA 1945); In re Swenson 56 USPQ 372 (CCPA 1942); In re Sola 25 USPQ 433 (CCPA 1935); In re Dreyfus 24 USPQ 52 (CCPA 1934).
Regarding claim 28, Lin fails to disclose that the anti-warpage structure is made of a semiconductor material.
Choi teaches the use of dummy structures 120 (Fig. 6a) comprising semiconductor material, such as silicon, in a semiconductor package for reducing warpage associated with semiconductor dies. It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the anti-warpage structure of Lin to comprise the semiconductor material taught by Choi in order to provide structural support and reduce warpage of the semiconductor package.
Regarding claim 31, Lin discloses a method for forming a chip package structure comprising (Figs. 1A-2C):
bonding a chip package to a wiring substrate 160 (Fig. 2B),
bonding a first anti-warpage structure to the wiring substrate (Figs. 1B, 2B, the ring structure 210 and ring dam 240 act as an anti-warpage, and insulated from layer 160 by adhesive layer 180 (Fig. 1C) and electrically insulated from the chip package 122 by a trench between layers 210 and 240.
bonding a heat dissipation structure 250 to the wiring substrate, wherein the heat dissipation structure surrounds the chip package and the first anti-warpage structure (Figs. 1D, 2B).
Lin discloses the claimed anti-warpage structure (210 + 240), but fail to disclose that the anti-warpage structure is made of a semiconductor material.
Choi teaches the use of dummy structures 120 (Fig. 6a) comprising semiconductor material, such as silicon, in a semiconductor package for reducing warpage associated with semiconductor dies. It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the anti-warpage structure of Lin to comprise the semiconductor material taught by Choi in order to provide structural support and reduce warpage of the semiconductor package.
Regarding claims 29, 32, Lin fails to disclose the thicknesses or lengths of the anti-warpage structures.
However, it would have been obvious to one having ordinary skill in the art at the time the invention was made to modify and obtain variety size and shape of the anti-warpage layers. The selection of the parameters such as energy, concentration, temperature, time, molar fraction, depth, thickness, etc., would have been obvious and involve routine optimization which has been held to be within the level of ordinary skill in the art. "Normally, it is to be expected that a change in energy, concentration, temperature, time, molar fraction, depth, thickness, etc., or in conbination of the parameters would be an unpatentable modification. Under some circumstances, however, changes such as these may impart patentability to a process if the particular ranges claimed produce a new and unexpected result which is different in kind and not merely degree from the results of the prior art ... such ranges are termed "critical ranges and the applicant has the burden of proving such criticality.... More particularly, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller 105 USPQ233, 255 (CCPA 1955). See also In re Waite 77 USPQ 586 (CCPA 1948); In re Scherl 70 USPQ 204 (CCPA 1946); In re Irmscher 66 USPQ 314 (CCPA 1945); In re Norman 66 USPQ 308 (CCPA 1945); In re Swenson 56 USPQ 372 (CCPA 1942); In re Sola 25 USPQ 433 (CCPA 1935); In re Dreyfus 24 USPQ 52 (CCPA 1934).
Regarding claim 34, Lin discloses the chip package structure has a sidewall (wing substrate 130 with a top surface 131a and opposite bottom surface 131b, lateral/end surfaces connecting those surfaces), and the second warpage is spaced apart from the chip package (abstract: the anti warpage structure surrounds the chip structure and the chip is between the first anchor and the anchor structure is isolated from the chip structure, Figs. 1A-1C)).
Regarding claim 35, Lin discloses the semiconductor material comprises an elementary or compound material (Background).
Regarding claim 36, Lin discloses the claimed anti-warpage structure (210 + 240), but fail to disclose that the anti-warpage structure is made of a semiconductor material.
Choi teaches the use of dummy structures 120 (Fig. 6a) comprising semiconductor material, such as silicon, in a semiconductor package for reducing warpage associated with semiconductor dies. It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the anti-warpage structure of Lin to comprise the semiconductor material taught by Choi in order to provide structural support and reduce warpage of the semiconductor package.
Regarding claim 37, Lin discloses the first anti-warpage is bonded to the wiring through an adhesive layer (Fig. 1A), the adhesive layer 180 is a single-layer structure, the top surface of the adhesive layer 180 level with bottom surface of the first anti warpage structure and bottom surface level with second top surface of the wiring substrate (Figs. 1A-1C).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THAO P LE whose telephone number is (571)272-1785. The examiner can normally be reached on Monday-Friday 9AM-6PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached on 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306.
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/THAO P LE/Primary Examiner, Art Unit 2818
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