DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I in the reply filed on 11/19/2025 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3-6, and 10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nishioka (U.S. Publication No. 2019/0096776 A1).
With respect to claim 1, Nishioka discloses a testline structure of a semiconductor device, comprising: a substrate layer [680]; a frontside insulating layer [684/685] atop the substrate layer; a backside insulating layer [683] under the substrate layer; and a probe pad structure [FB/686/M1/M2/M3/M4/TSV4] vertically extending through the frontside insulating layer, the substrate layer, and the backside insulating layer, wherein the probe pad structure includes a frontside probe pad [FB/686] in the frontside insulating layer and a backside probe pad [BB/TSV4] in the backside insulating layer (see Figure 5-6 and ¶[0037]).
With respect to claim 3, Nishioka discloses wherein the semiconductor device is a packaged integrated circuit die, and the testline structure is located aside of a circuit region [510] of the packaged integrated circuit die (See Figure 5).
With respect to claim 4, Nishioka discloses a device under test (DUT) [518/519] in electrical connection with the probe pad structure (see ¶[0034-0035]).
With respect to claim 5, Nishioka discloses wherein the DUT is formed in the frontside insulating layer (see ¶[0044]).
With respect to claim 6, Nishioka discloses wherein the DUT is formed in the backside insulating layer (see ¶[0044]).
With respect to claim 10, Nishioka discloses wherein the frontside probe pad and the backside probe pad include metallic compositions different from other metal pieces of the probe pad structure formed in the frontside insulating layer and the backside insulating layer (See ¶[0038] and ¶[0040]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nishioka in view of Chen et al. (U.S. Publication No. 2021/0134685 A1; hereinafter Chen).
With respect to claim 2, Nishioka discloses wherein the semiconductor device is a wafer, but fails to disclose the testline structure is located in a scribe line region of the wafer. In the same field of endeavor, Chen teaches the testline structure [144] is located in a scribe line region of the wafer (see Figure 2B; scribe region removed by sawing paths [SP]).
Implementation of testline structures within the scribe line region, as taught by Chen, allows for the removal of testing structures from the wafer during singulation wherein the testing process has completed and functionality is finalized (see ¶[0038]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
Allowable Subject Matter
Claims 11-16 and 21-24 are allowed.
Claims 7-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
With respect to claims 7-9, none of the prior art teaches or suggests, alone or in combination, wherein the probe pad structure also includes: a plurality of doped epitaxial features in the substrate layer, frontside contact vias coupling the doped epitaxial features to the frontside probe pad, and backside contact vias coupling the doped epitaxial features to the backside probe pad.
With respect to claims 11-16, none of the prior art teaches or suggests, alone or in combination, a semiconductor device, comprising: wherein the testline region includes: a frontside metal pad in the frontside of the semiconductor device, a plurality of epitaxial features under the frontside metal pad, and a plurality of contact vias above the epitaxial features and electrically coupling the epitaxial features to the frontside metal pad, in combination with all other limitations of the claim.
With respect to claims 21-24, none of the prior art teaches or suggests, alone or in combination, a semiconductor device, comprising: a plurality of second transistors disposed over the substrate, the second transistors including a plurality of epitaxial features, a third frontside interconnect structure disposed over the substrate and electrically coupled to the epitaxial features, the third frontside interconnect structure including a frontside probe pad, and a second backside interconnect structure disposed under the substrate and electrically coupled to the epitaxial features, the second backside interconnect structure including a backside probe pad, in combination with all other limitations of the claim.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chong et al. (U.S. Patent No. 11,054,461 B1) discloses a device under test but fails to disclose a plurality of doped epitaxial features in the substrate layer, frontside contact vias coupling the doped epitaxial features to the frontside probe pad, and backside contact vias coupling the doped epitaxial features to the backside probe pad, or plurality of second transistors disposed over the substrate, the second transistors including a plurality of epitaxial features, a third frontside interconnect structure disposed over the substrate and electrically coupled to the epitaxial features, the third frontside interconnect structure including a frontside probe pad, and a second backside interconnect structure disposed under the substrate and electrically coupled to the epitaxial features, the second backside interconnect structure including a backside probe pad, in combination with all other limitations of the claim.
Hong et al. (U.S. Publication No. 2023/0326813 A1) discloses a device under test but fails to disclose a plurality of doped epitaxial features in the substrate layer, frontside contact vias coupling the doped epitaxial features to the frontside probe pad, and backside contact vias coupling the doped epitaxial features to the backside probe pad, or plurality of second transistors disposed over the substrate, the second transistors including a plurality of epitaxial features, a third frontside interconnect structure disposed over the substrate and electrically coupled to the epitaxial features, the third frontside interconnect structure including a frontside probe pad, and a second backside interconnect structure disposed under the substrate and electrically coupled to the epitaxial features, the second backside interconnect structure including a backside probe pad, in combination with all other limitations of the claim.
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/JONATHAN HAN/Primary Examiner, Art Unit 2818