DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
In view of Applicant’s amendments, some of the prior drawing objections are withdrawn.
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the barrier layer and well layer as found in claim 5; an entirety of an upper surface of the P-type semiconductor layer not covered by the cover layer as found in claim 22; and the cover layer directly covering only the sides surfaces of the P-type semiconductor layer without covering the upper surface of the P-type semiconductor layer as found in claim 23, must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
In view of Applicant’s amendments, the prior claim objections are withdrawn.
Claims 22-23 are objected to because of the following informalities: In claim 22, “of upper surface” should likely read --of an upper surface--. Appropriate correction is required.
Claim 23 inherits this objection.
Claim Rejections - 35 USC § 112
In view of Applicant’s amendments, the prior 112(b) rejection is withdrawn.
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 22-23 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
For claim 22, as the cover layer is shown to cover an entirety of the upper surface of the P-type semiconductor layer in the drawings, at least in a left-to-right direction as seen in e.g., Fig. 5, reciting “the cover layer does not cover an entirety of upper surface of the P-type semiconductor layer” introduces new matter. Furthermore, any claim containing a negative limitation which does not have basis in the original disclosure should be rejected under 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph, as failing to comply with the written description requirement.
Claim 23 inherits this rejection for new matter.
For claim 23, as the cover layer is shown to cover an entirety of the upper surface of the P-type semiconductor layer in the drawings, at least in a left-to-right direction as seen in e.g., Fig. 5, reciting “wherein the cover layer directly covers only the side surfaces of the P-type semiconductor layer without covering the upper surface of the P-type semiconductor layer” introduces new matter. Furthermore, any claim containing a negative limitation which does not have basis in the original disclosure should be rejected under 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph, as failing to comply with the written description requirement.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3-4 and 22-23 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
(Re Claim 3) “a thickness direction of the base layer” is recited twice, making the number of required directions unclear.
During examination, a subsequent “a thickness direction of the base layer” was read as “the thickness direction of the base layer”.
Claim 4 inherits this rejection for indefiniteness.
(Re Claim 4) “a thickness direction of the base layer” was recited twice in claim 3, making the number of required directions unclear.
During examination, a subsequent “a thickness direction of the base layer” was read as “the thickness direction of the base layer”.
(Re Claim 22) As “the cover layer does not cover an entirety of upper surface of the P-type semiconductor layer” was neither originally shown nor described, the relationship between parts required by the claim is unclear.
During examination, this was read as requiring only that the cover layer may have an opening exposing the upper surface of the P-type semiconductor layer.
Claim 23 inherits this rejection for indefiniteness.
(Re Claim 23) As “the cover layer directly covers only the side surfaces of the P-type semiconductor layer without covering the upper surface of the P-type semiconductor layer” was neither originally shown nor described, the relationship between parts required by the claim is unclear.
During examination, this was read as requiring only that the cover layer may have an opening exposing the upper surface of the P-type semiconductor layer.
Rejection 1/2
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-4 and 21-23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by He et al. (US 2020/0328327) of record.
(Re Claim 1) He teaches a display device comprising: a base layer (310; Fig. 6D); and light emitting elements (520d+520e+520f; Fig. 6C) disposed on the base layer, the light emitting elements including an N-type semiconductor layer (505; Fig. 6C, ¶57), a P-type semiconductor layer (540; Fig. 6C, ¶60), and an active layer (530; Fig. 6C, ¶65) disposed between the N-type semiconductor layer and the P-type semiconductor layer (Fig. 6C), wherein
the active layer is between the base layer and the N-type semiconductor layer (Fig. 6D);
the light emitting elements include a first light emitting element (520a; Fig. 6C) emitting light of a first color (¶59) and a second light emitting element emitting light (520b; Fig. 6C) of a second color (¶59),
the N-type semiconductor layer includes a first N-type semiconductor layer of the first light emitting element (boxed area on the left beneath the corresponding active area; Fig. 6C markup) and a second N-type semiconductor layer of the second light emitting element (boxed area in the middle beneath the corresponding active area; Fig. 6C markup),
the active layer includes a first active layer (left 530; Fig. 6C) of the first light emitting element and a second active layer (middle 530; Fig. 6C) of the second light emitting element, and
the first N-type semiconductor layer and the second N-type semiconductor layer are integral with each other, and form a plane surface in an area where the active layer is disposed (Fig. 6C).
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(Re Claim 2) He teaches the display device of claim 1, wherein the first light emitting element and the second light emitting element include a same N-type semiconductor layer (both include 505; ¶57).
(Re Claim 3) He teaches display device of claim 1, further comprising: a cover layer (620; Fig. 6C) disposed between the light emitting elements adjacent to each other, wherein the N-type semiconductor layer includes a first area and a second area, the first area overlaps the cover layer in a thickness direction of the base layer (top to bottom as seen in Fig. 6C), the second area does not overlap the cover layer in a thickness direction of the base layer (top to bottom as seen in Fig. 6C), and the active layer and the p-type semiconductor layer are disposed in the second area (Fig. 6D and the Fig. 6C markup).
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(Re Claim 4) He teaches the display device of claim 3, wherein a portion (under the middle active layer 530) of the N-type semiconductor layer disposed in the second area does not overlap the cover layer in a thickness direction (Fig. 6D and the Fig. 6C markup; also see the 112(b) rejection).
(Re Claim 21) He teaches the electronic device comprising a display device, the display device comprising: a base layer (310; Fig. 6D); and light emitting elements (520d+520e+520f; Fig. 6C) disposed on the base layer, the light emitting elements including an N-type semiconductor layer (505; Fig. 6C, ¶57), a P-type semiconductor layer (540; Fig. 6C, ¶60), and an active layer (530; Fig. 6C, ¶65) disposed between the N-type semiconductor layer and the P-type semiconductor layer, wherein
the active layer is between the base layer and the N-type semiconductor layer (Fig. 6D),
the light emitting elements include a first light emitting element (520a; Fig. 6C) emitting light of a first color (¶59) and a second light emitting element (520b; Fig. 6C) emitting light of a second color (¶59),
the N-type semiconductor layer includes a first N-type semiconductor layer (boxed area on the left beneath the corresponding active area; Fig. 6C markup) of the first light emitting element and a second N-type semiconductor layer of the second light emitting element (boxed area in the middle beneath the corresponding active area; Fig. 6C markup),
the active layer includes a first active layer (left 530; Fig. 6C) of the first light emitting element and a second active layer (middle 530; Fig. 6C) of the second light emitting element, and
the first N-type semiconductor layer and the second N-type semiconductor layer are integral with each other, and form a plane surface in an area where the active layer is disposed (Fig. 6C).
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(Re Claim 22) He teaches an electronic device comprising a display device, the display device comprising: a base layer (310; Fig. 6D); light emitting elements (520d+520e+520f; Fig. 6C) disposed on the base layer, the light emitting elements including an N-type semiconductor layer (505; Fig. 6C, ¶57), a P-type semiconductor layer (540; Fig. 6C, ¶60), and an active layer (530; Fig. 6C, ¶65) disposed between the N-type semiconductor layer and the P-type semiconductor layer; and a cover layer (620; Fig. 6C) disposed between the light emitting elements adjacent to each other, wherein the light emitting elements include a first light emitting element (520a; Fig. 6C) emitting light of a first color (¶59) and a second light emitting element (520b; Fig. 6C) emitting light of a second color (¶59),
the N-type semiconductor layer includes a first N-type semiconductor layer of the first light emitting element (boxed area on the left beneath the corresponding active area; Fig. 6C markup) and a second N-type semiconductor layer of the second light emitting element (boxed area in the middle beneath the corresponding active area; Fig. 6C markup),
the active layer includes a first active layer of the first light emitting element (left 530; Fig. 6C) and a second active layer of the second light emitting element (middle 530; Fig. 6C), the first N-type semiconductor layer and the second N-type semiconductor layer are integral with each other, and form a plane surface in an area where the active layer is disposed (Fig. 6C), and the cover layer does not cover an entirety of upper surface of the P-type semiconductor layer, and covers side surfaces of the P-type semiconductor layer (Fig. 6C; see the 112(a) and 112(b) rejections).
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(Re Claim 23) He teaches the electronic device of claim 22, wherein the cover layer directly covers only the side surfaces of the P-type semiconductor layer without covering the upper sur- face of the P-type semiconductor layer (Fig. 6C; see the 112(a) and 112(b) rejections).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 5 and 7 rejected under 35 U.S.C. 103 as being unpatentable over He et al. (US 2020/0328327) of record as applied to claim 1 above, and further in view of Su et al. (US 2012/0235116) of record.
(Re Claim 5) He teaches the display device of claim 1, wherein the first active layer and the second active layer are formed on the plane surface formed by the first N-type semiconductor layer and the second N-type semiconductor layer.
He has not been shown to explicitly teach the display device wherein the active layer includes a barrier layer and a well layer and the N-type semiconductor layer is in contact with the active layer to be adjacent to the barrier layer.
He teaches that the active layer may include at least one quantum well (He: ¶65).
Su teaches forming an active layer (208; Fig. 2F) including a barrier layer (272; Fig. 2F) and a well layer (quantum well contacting 272; Fig. 2F), such that an N-type semiconductor layer (206; Fig. 2F) is in contact with the active layer to be adjacent to the barrier layer.
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form each light emitting element stack of He, such that the active layer of He contacts the N-type semiconductor layer utilized for contact – He’s N-type semiconductor 505 (note contact metal location in Fig. 6C) – as taught by Su, as the active layer configuration taught by Su provides improved quantum efficiency (Su: ¶43).
Modified He then teaches the active layer includes a barrier layer (Su: 272; Fig. 2F) and a well layer (quantum well contacting 272; Fig. 2F), and the N-type semiconductor layer (He: 505) is in contact with the active layer to be adjacent to the barrier layer (compare the location of Su’s 206 with He’s 505).
(Re Claim 7) He teaches the display device of claim 1, wherein the N-type semiconductor layer includes GaN (¶77) doped with a first conductivity type dopant (n-type dopant; ¶57), and the P-type semiconductor layer includes GaN (¶77) doped with a second conductivity type dopant (p-type dopant; ¶60).
He has not been shown to explicitly teach the display device wherein the active layer includes a well layer including InGaN and a barrier layer including GaN.
He teaches that the active layer may include at least one quantum well (He: ¶65).
Su teaches forming an active layer (208; Fig. 2F) including a barrier layer (272; Fig. 2F) and a well layer (quantum well contacting 272; Fig. 2F), such that an N-type semiconductor layer (206; Fig. 2F) is in contact with the active layer to be adjacent to the barrier layer.
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form each light emitting element stack of He, such that the active layer of He contacts the N-type semiconductor layer utilized for contact – He’s N-type semiconductor 505 (note contact metal location in Fig. 6C) – as taught by Su, as the active layer configuration taught by Su provides improved quantum efficiency (Su: ¶43).
Furthermore, Su teaches forming quantum wells using InGaN and barrier layers using GaN (¶¶46, 51).
A PHOSITA would find it obvious to utilize InGaN to form the quantum wells, and GaN to form the barrier layers, of modified He, as Su teaches these are suitable materials to respectively form the quantum wells and barrier layers from. The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). "Reading a list and selecting a known compound to meet known requirements is no more ingenious than selecting the last piece to put in the last opening in a jig-saw puzzle." 325 U.S. at 335, 65 USPQ at 301.). See also In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over He et al. (US 2020/0328327) of record as applied to claim 1 above, and further in view of Hasegawa et al. (US 2016/0372631) of record.
(Re Claim 6) He teaches the display device of claim 1, wherein the N-type semiconductor layer, the active layer, and the P-type semiconductor layer are sequentially disposed in a stacked direction (stacked direction is from bottom to top; Fig. 6C), the N-type semiconductor layer includes a dopant (n-type; ¶57).
He has not been shown to explicitly teach that the dopant is a silicon dopant.
Hasegawa teaches that GaN is n-type doped using silicon dopant (¶42).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to utilize silicon dopant to dope the GaN of the N-type semiconductor layer, as this is a known n-type dopant for GaN.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over He et al. (US 2020/0328327) and Su et al. (US 2012/0235116) both of record as applied to claim 7 above, and further in view of Hu (US 2013/0214247) of record.
(Re Claim 8) Modified He teaches the display device of claim 7, but has not been shown to explicitly teach the display device wherein the light emitting elements further include: a superlattice layer disposed between the active layer and the N-type semiconductor layer, and an electron blocking layer disposed between the active layer and the P-type semiconductor layer.
Su teaches forming an electron blocking layer (EBL; Fig. 2F) between the active layer (208; Fig. 2F) and a P-type semiconductor layer (212; Fig. 2F, ¶49).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to incorporate the electron blocking layer of Su between the active layer and the P-type semiconductor layer of modified He, as electron blocking layers help confine radiative recombination within the active layer (Su: ¶48).
Hu teaches forming a superlattice layer between an active layer (145; Fig. 3) and an N-type semiconductor layer (140; Fig. 3).
A PHOSITA would find it obvious to form a superlattice layer between the active layer and the N-type semiconductor layer of modified He, in order to release stresses within the layers and improve internal quantum efficiency of the light emitting elements (Hu: ¶11).
Modified He then teaches that the light emitting elements further include:
a superlattice layer (Hu: 145; Fig. 3) disposed between the active layer (Su: 208; Fig. 2F) and the N-type semiconductor layer (He: 505; Fig. 6C), and
an electron blocking layer (Su: EBL; Fig. 2F) disposed between the active layer (Su: 208; Fig. 2F) and the P-type semiconductor layer (He: 540; Fig. 6C).
Rejection 2/2
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over He et al. (US 2020/0328327) and Wang (US 2021/0335884), both of record.
(Re Claim 22) He teaches an electronic device (110; Fig. 9B) comprising a display device (910; Fig. 9B), the display device comprising: a base layer (310; Fig. 6D); light emitting elements (520d+520e+520f; Fig. 6C) disposed on the base layer, the light emitting elements including an N-type semiconductor layer (505; Fig. 6C, ¶57), a P-type semiconductor layer (540; Fig. 6C, ¶60), and an active layer (530; Fig. 6C, ¶65) disposed between the N-type semiconductor layer and the P-type semiconductor layer (Fig. 6C); and wherein the light emitting elements include a first light emitting element (520a; Fig. 6C) emitting light of a first color (¶59) and a second light emitting element (520b; Fig. 6C) emitting light of a second color (¶59),
the N-type semiconductor layer includes a first N-type semiconductor layer of the first light emitting element (boxed area on the left beneath the corresponding active area; Fig. 6C markup) and a second N-type semiconductor layer of the second light emitting element (boxed area in the middle beneath the corresponding active area; Fig. 6C markup),
the active layer includes a first active layer of the first light emitting element (left 530; Fig. 6C) and a second active layer (middle 530; Fig. 6C) of the second light emitting element, the first N-type semiconductor layer and the second N-type semiconductor layer are integral with each other, and form a plane surface in an area where the active layer is disposed (Fig. 6C).
He has not been explicitly shown to teach the electronic device comprising a display device, the display device comprising:
a cover layer disposed between the light emitting elements adjacent to each other, and the cover layer does not cover an entirety of upper surface of the P-type semiconductor layer, and covers side surfaces of the P-type semiconductor layer.
He teaches utilizing a cover layer (the dielectric layer of ¶58) to define the placement of the light emitting elements during their growth.
Wang teaches forming separated light emitting elements (108+100; Fig. 1c) within openings in a cover layer (104; Fig. 1c).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form the light emitting elements of He using a cover layer as taught by Wang, for the cover layer taught by He (the dielectric layer of ¶58), as such a cover layer provides an increased growth rate (Wang: ¶44).
Wang’s cover layer is placed on a top surface of a common n-type layer 100 (Wang: ¶37), which corresponds to a top surface of the substrate 510 of He, which is the top surface of the layer 505 (He: “The substrate 510 may be part of a device and may be the same or similar to the one shown in the diagram 500a in FIG. 5A, and may include the bottom layer 503 and the one or more buffer or initiation layers 505”; ¶63), and so Wang’s cover layer 104 would be similarly positioned. This means He’s layers that form the light emitting elements located above He’s layer 505 are grown within Wang’s cover layer 104.
A PHOSITA would then find it obvious to omit forming the passivation layer 620 of He, as Wang’s cover layer 104 provides a barrier between atmosphere and the active layer. This omission also reduces the overall process steps when forming the light emitting elements using a cover layer like Wang’s.
This results in modified He teaching a cover layer (Wang: 104) disposed between the light emitting elements adjacent to each other (Wang: Fig. 1c), and the cover layer does not cover an entirety of an upper surface (topmost as seen in Wang’s Fig. 1c) of the P-type semiconductor material (the P-type semiconductor material 114 of Wang is uncovered), and covers side surfaces (left and right) of the P-type semiconductor layer (due to Wang’s cover layer surrounding each light emitting element; see Wang’s Fig. 1c).
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(Re Claim 23) Modified He teaches the electronic device of claim 22, wherein the cover layer directly covers only the side surfaces of the P-type semiconductor layer without covering the upper surface of the P-type semiconductor layer (Wang: Fig. 1c).
Response to Arguments
Applicant's arguments filed 6/2/2026 have been fully considered but they are moot in view of the new grounds of rejection.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Mezouari et al. (US 2024/0021759) teaches growing active layers in openings that emit light of different wavelengths (e.g., Fig. 15F, ¶160).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Christopher A Schodde whose telephone number is (571)270-1974. The examiner can normally be reached M-F 1000-1800 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at (571)272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHRISTOPHER A. SCHODDE/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
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