Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
Applicant's election, without traverse, of claims 16-20 in the “Response to Restriction Requirement” filed on 06/26/2026 is acknowledged and entered by the Examiner.
Applicant's cancellation of claims 21-35 and addition of new claims 36-50 in the “Claims” filed on 06/26/2026 is acknowledged and entered by the Examiner.
In regards to the Applicant’s addition of claims 21-30, the Examiner respectfully contends that newly added claims 21-30 are directed to different embodiments and impose a serious burden on the Examiner for the following reasons:
Species I: A method for forming a package module, as described in (Fig. 3; [0014, 0116]), of which claims 16-20 appear to read upon, respectively.
Species II: A method for forming a package module, as described in (Fig. 11A; [0024, 0161-0164]), of which claims 36-39 appear to read upon, respectively.
Species III: A method for forming a package module, as described in (Fig. 6; [0018, 0135-0145]), of which claims 40-50 appear to read upon, respectively.
Species I-III as claimed are independent or distinct because they have been disclosed in separate figures and different embodiments, and are characterized by mutually exclusive characteristics as follows:
Regarding Species I, II, and III, are mutually exclusive with “mounting a plurality of semiconductor dies on the interposer, wherein the plurality of semiconductor dies include a semiconductor die upper surface; forming an upper molding material layer on the plurality of semiconductor dies such that the upper molding material layer includes a recessed upper surface that is recessed from the semiconductor die upper surface; and forming a backside metal layer on the recessed upper surface of the upper molding material layer” (Fig. 3; [0014, 0116]) in Species I, and, “forming an interposer; mounting a plurality of semiconductor dies on the interposer, the plurality of semiconductor dies including a semiconductor die upper surface; forming an upper molding material layer around the plurality of semiconductor dies; and etching an upper surface of the upper molding material layer to form a recessed upper surface that is recessed from the semiconductor die upper surface of the plurality of semiconductor dies” (Fig. 11A; [0024, 0161-0164]) in Species II, and, “forming an interposer including an interposer redistribution layer (RDL) portion and an interposer molded portion on the interposer RDL portion, the interposer molded portion including at least one local silicon interconnect (LSI) die; mounting a plurality of semiconductor dies on the interposer molded portion; forming an upper molding material layer on and around the plurality of semiconductor dies; etching the upper molding material layer to create a recessed upper surface recessed from upper surfaces of the semiconductor dies; and depositing a backside metal layer conformally over the recessed upper surface of the upper molding material layer and over the upper surfaces of the semiconductor dies” (Fig. 6; [0018, 0135-0145]) in Species III.
There is a search and/or examination burden for the patentably distinct species as set forth above because at least the following reasons apply:
the species or groupings of patentably indistinct species have acquired a separate status in the art due to their recognized divergent subject matter as exemplified by the aforementioned mutually exclusive characteristics, while the species or groupings of patentably indistinct species require a different field of search (different search strategies or search queries, as evidenced by the above-defined distinctions between the species) (see MPEP § 808.02) and/or the prior art applicable to one species would not likely be applicable to another species; and/or the inventions are likely to raise different non-prior art issues under 35 U.S.C. 101 and/or 35 U.S.C. 112, first paragraph. Therefore, restriction for examination purposes as indicated is proper.
This Thus, the requirement is deemed proper and is therefore made FINAL.
office action consider claims 16-20 and 36-50 pending for prosecution, wherein claims 36-50 are withdrawn from further consideration, and claims 16-20 are presented for examination.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
1. Claims 16-20 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to
particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Regarding Claim 16, the instant claim recites limitations, wherein the metes and bounds of the claimed method are vague and ill-defined as a result of uncertainty in the different boundaries and new limitations “mounting a plurality of semiconductor dies on the interposer, wherein the plurality of semiconductor dies include a semiconductor die upper surface; forming an upper molding material layer on the plurality of semiconductor dies such that the upper molding material layer includes a recessed upper surface that is recessed from the semiconductor die upper surface; and forming a backside metal layer on the recessed upper surface of the upper molding material layer” (Claim 16; emphasis added). The claim is indefinite because of the following:
i) The claim is indefinite because “mounting a plurality of semiconductor dies on the interposer, wherein the plurality of semiconductor dies include a semiconductor die upper surface; forming an upper molding material layer on the plurality of semiconductor dies such that the upper molding material layer includes a recessed upper surface that is recessed from the semiconductor die upper surface; and forming a backside metal layer on the recessed upper surface of the upper molding material layer” (Claim 16) is ambiguous and unclear. It is not clear what is meant by how the plurality of semiconductor dies include a semiconductor die upper surface”. Do the plurality of semiconductor dies share a single semiconductor die upper surface or does each semiconductor die of the plurality of semiconductor dies have a single semiconductor die upper surface. Therefore, the limitation of “mounting a plurality of semiconductor dies on the interposer, wherein the plurality of semiconductor dies include a semiconductor die upper surface; forming an upper molding material layer on the plurality of semiconductor dies such that the upper molding material layer includes a recessed upper surface that is recessed from the semiconductor die upper surface; and forming a backside metal layer on the recessed upper surface of the upper molding material layer” (Claim 16) is indefinite and unclear.
The specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention, whereby the claims are rendered indefinite. Therefore, the resulting claim is indefinite and is failing to particularly point out and distinctly claim the subject matter. Appropriate clarification and/or correction are/is required within metes and bounds of the claimed invention.
Regarding Claims 17-20, those are rejected under 112(b) because of their dependency status from claim 16.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (100; Fig 3A; [0063]) = (element 100; Figure No. 3A; Paragraph No. [0063]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
2. Claims 16-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nair et al. (US 20200203248 A1; hereinafter Nair).
Regarding claim 16, Nair teaches a method of forming a package module (see the entire document, specifically Fig. 5; [0163+], and as cited below), the method comprising:
forming an interposer (12; Fig. 6A in view of Fig. 5A in view of Figs. 3A-3E;
see [0047] in view of [0046] in view of [0042-0044]);
mounting a plurality of semiconductor dies ({14-1, 14-2}; Fig. 6A in view of Fig. 5A in view of Figs. 3A-3E; see [0047] in view of [0046] in view of [0042-0044]), wherein the plurality of semiconductor dies ({14-1, 14-2}; Fig. 6A in view of Fig. 5A in view of Figs. 3A-3E; see [0047] in view of [0046] in view of [0042-0044]) include a semiconductor die upper surface (see Fig. 6A in view of Fig. 5A in view of Fig. 3A; see section 1 above; 112(b) rejection);
forming an upper molding material layer (16; Fig. 6A in view of Fig. 5A in view of Figs. 3B-3C; [0042-0044]) on the plurality of semiconductor dies ({14-1, 14-2}; Fig. 6A in view of Fig. 5A in view of Figs. 3B-3C; [0042-0044]) such that the upper molding material layer (16; see Fig. 3C; [0042-0044]) includes a recessed upper surface that is recessed from the semiconductor die upper surface (see Fig. 3C; see section 1 above; 112(b) rejection); and
forming a backside metal layer (20; Fig. 6A in view of Fig. 5A in view of Fig. 3E; [0044]) on the recessed upper surface of the upper molding material layer (16; Fig. 3E; [0042-0044]).
Regarding claim 17, Nair teaches all of the features of claim 16.
Nair further teaches wherein the forming of the upper molding material layer (16; Fig. 6A in view of Fig. 5A in view of Figs. 3B-3C; [0042-0044]) comprises forming the recessed upper surface of the upper molding material layer to include an inner recessed surface portion ({18-3}; Fig. 6A in view of Fig. 5A in view of Figs. 3B-3C; [0042-0044, 0046, 0047]) between the plurality of semiconductor dies ({14-1, 14-2}; Fig. 6A in view of Fig. 5A in view of Figs. 3B-3C; [0042-0044]), and the forming of the backside metal layer (20; Fig. 6A in view of Fig. 5A in view of Fig. 3E; [0044]) comprises forming the backside metal layer (20; Fig. 6A in view of Fig. 5A in view of Fig. 3E; [0044]) to include an inner backside metal layer portion on the inner recessed surface portion (see Fig. 3E).
Regarding claim 18, Nair teaches all of the features of claim 16.
Nair further teaches wherein the forming of the upper molding material layer (16; Fig. 6A in view of Fig. 5A in view of Figs. 3B-3C; [0042-0044]) comprises forming the recessed upper surface of the upper molding material layer to include an outer recessed surface portion ({18-1, 18-2}; Fig. 6A in view of Fig. 5A in view of Figs. 3B-3C; [0042-0044, 0046, 0047]) outside the plurality of semiconductor dies ({14-1, 14-2}; Fig. 6A in view of Fig. 5A in view of Figs. 3B-3C; [0042-0044, 0046, 0047]), and the backside metal layer (20; Fig. 6A in view of Fig. 5A in view of Figs. 3B-3C; [0042-0044, 0046, 0047]) comprises an outer backside metal layer portion on the outer recessed surface portion ({18-1, 18-2}; Fig. 6A in view of Fig. 5A in view of Figs. 3B-3C; [0042-0044, 0046, 0047]).
Regarding claim 19, Nair teaches all of the features of claim 16.
Nair further teaches wherein the forming of the backside metal layer (20; Fig. 6A in view of Fig. 5A in view of Figs. 3B-3C; [0042-0044, 0046, 0047]) comprises forming the backside metal layer on the semiconductor die upper surface (see section 1 above; 112(b) rejection) of the plurality of semiconductor dies ({14-1, 14-2}; Fig. 6A in view of Fig. 5A in view of Figs. 3B-3C; [0042-0044, 0046, 0047]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
3. Claim 20 is rejected under 35 U.S.C.103 as being unpatentable over Nair et al. (US 20200203248 A1; hereinafter Nair), in view of Shih (US 20180102311 A1; hereinafter Shih).
Regarding claim 20, Nair teaches all of the features of claim 16.
Nair further teaches wherein the forming of the interposer (12; Fig. 6A in view of Fig. 5A in view of Figs. 3A-3E; see [0032, 0038]) comprises: forming an interposer redistribution layer (RDL) portion ({12, 24}; Fig. 6A in view of Fig. 5A in view of Figs. 3A-3E; see [0032, 0038]) on a carrier substrate (26; Fig. 6A in view of Fig. 5A in view of Figs. 3A-3E; see [0047, 0040]); and forming (see below for “an interposer molded portion on”) the interposer RDL portion ({12, 24}; Fig. 6A in view of Fig. 5A in view of Figs. 3A-3E; see [0032, 0038]), (see below for “wherein the interposer molded portion comprises a local silicon interconnect (LSI) die interconnecting”) the plurality of semiconductor dies ({14-1, 14-2}; Fig. 6A in view of Fig. 5A in view of Figs. 3A-3E; see [0047] in view of [0046] in view of [0042-0044]).
As noted above, Nair does not expressly disclose “wherein the forming of the interposer comprises: forming an interposer redistribution layer (RDL) portion on a carrier substrate; and forming an interposer molded portion on the interposer RDL portion, wherein the interposer molded portion comprises a local silicon interconnect (LSI) die interconnecting the plurality of semiconductor dies”.
However, in the analogous art, Shih teaches the field of semiconductor packaging ([0001]), wherein (Fig. 1+; [0001+]) TSV interconnect ({100, 101, 550}; Fig. 13; see [0022, 0039-0040, 0056-0060]) comprising of silicon semiconductor substrate (see [0022, 0039-0040, 0056-0060]) in a molded compound (550; [0039]) that is connected to first semiconductor die and the second semiconductor die and over RDL structure (700; [0041]).
It would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Shih’s silicon substrate die comprising TSV interconnect in a molding layer into Nair’s method, and thereby, modified Nair’s (by Shih) method will have the forming of the interposer (Nair 12; Fig. 6A in view of Fig. 5A in view of Figs. 3A-3E; see [0032, 0038]) comprises: forming an interposer redistribution layer (RDL) portion (Nair {12, 24}; Fig. 6A in view of Fig. 5A in view of Figs. 3A-3E; see [0032, 0038]) on a carrier substrate (Nair 26; Fig. 6A in view of Fig. 5A in view of Figs. 3A-3E; see [0047, 0040]); and forming an interposer molded portion (Shih {100, 101, 550}; Fig. 13; see [0022, 0039-0040, 0056-0060]) on the interposer RDL portion (Nair {12, 24}; Fig. 6A in view of Fig. 5A in view of Figs. 3A-3E; see [0032, 0038]), wherein the interposer molded portion (Shih {100, 101, 550}; Fig. 13; see [0022, 0039-0040, 0056-0060]) comprises a local silicon interconnect (LSI) die (Shih {100, 101}; Fig. 13; see [0022, 0039-0040, 0056-0060]) interconnecting the plurality of semiconductor dies (Nair {14-1, 14-2}; Fig. 6A in view of Fig. 5A in view of Figs. 3A-3E; see [0047] in view of [0046] in view of [0042-0044]).
The ordinary artisan would have been motivated to modify Nair in the manner set forth above, at least, because this inclusion provides a silicon substrate die comprising TSV interconnect in a molding layer (Shih [0022, 0039-0040, 0056-0060]) that functions as a bridge and connects a first semiconductor die and a second semiconductor die to help increase the functionality of the device and perform complex operations.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Omar Mojaddedi whose telephone number is 313-446-6582. The examiner can normally be reached on Monday – Friday, 8:00 a.m. to 4:00 p.m..
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/OMAR F MOJADDEDI/Examiner, Art Unit 2898
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