DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to the communications dated 11/11/2025.
Claims 1-15, and 21-25 are pending in this application.
Applicant made a provisional election without traverse to prosecute the
invention of Group I, comprising original claims 1-15, and new claims 21-25, is acknowledged.
Claims 16-20 have been cancelled from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a non-elected group there being no allowable generic or linking claim.
Applicant has the right to file a divisional application covering the subject matter of the non-elected claims.
Acknowledges
2. Receipt is acknowledged of the following items from the Applicant.
Information Disclosure Statements (IDS) filed on 05/01/2023, and 10/25/2024. The references cited on the PTOL 1449 form have been considered.
Applicant is requested to cite any relevant prior art if being aware on form PTO-1449 in accordance with the guidelines set for in M.P.E.P. 609.
Specification
3. The specification has been checked to the extent necessary to determine the presence of possible minor errors. However, the applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Drawing
4. The drawing is objected to for the following reason:
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “438” (shown in figure 4) has been used to designate both a moisture-resistant dielectric layer (described at paragraphs [0056] of the specification) and a Through-Si via (TSV) (para. [0062]).
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
6. Claims 1-3, 5-7, 9-12, 14-15, 21-22, and 24-25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang et al. (US 2016/0379960)
Regarding claim 1, Huang discloses a semiconductor device, comprising:
a first chip 102 (see figs. 2A, 14A/B) that includes a first wafer 104 and a first dielectric layer 202/204 disposed thereon;
a second chip 201 that includes a second wafer 224 and a second dielectric layer 212/214 disposed thereon, the second chip 201 having a backside surface and a frontside surface opposed to the backside surface, the second chip 201 being bonded to the first chip 102 at the frontside surface to define a bond line (alone the interface between the chips 102, 201) between the first dielectric layer 202/204 and the second dielectric layer 212/214;
an opening 1408 (see fig. 14A) through the backside surface of the second chip 201 that extends into the second dielectric layer 212/214; and
a bond pad 216 disposed within the second dielectric layer 212/214 between the second wafer 224 and the bond line, and extending beyond the opening 1408 in a direction parallel to the bond line.
Regarding claim 2, Huang discloses the semiconductor device of claim 1, further comprising: an external connection 226/226B (fig. 2A) and/or 712 (fig. 8) to the semiconductor device that is electrically connected to the bond pad 216 through the opening.
Regarding claim 3, Huang discloses the semiconductor device of claim 1, wherein an entirety of the bond pad 216 is positioned below the second wafer 224 in a direction of the first chip 102. See fig. 2A.
Regarding claim 5, Huang discloses the semiconductor device of claim 1, further comprising: a moisture-resistant seal ring 228/230 at least partially surrounding the opening. See fig. 2A.
Regarding claim 6, Huang discloses the semiconductor device of claim 5, wherein the bond pad 216 extends beyond the moisture-resistant seal ring 228/230 in the direction parallel to the bond line. See fig. 8.
Regarding claim 7, Huang discloses the semiconductor device of claim 1, further comprising: a copper-copper hybrid bond 220 (see fig. 4, and paras. 0028, 0078, 0084) bonding the second chip to the first chip and defining the bond line. See also the title of the Huang reference.
Regarding claim 9, Huang discloses the semiconductor device of claim 1, wherein the second chip 201 (or chip 802 in fig. 8) includes an optical sensor chip (having sensor 818, 820) and the first chip 102 includes a circuit chip configured to operate and/or receive an output of the optical sensor chip 802. See figs. 2, 8.
Regarding claim 10, Huang discloses the semiconductor device of claim 1, further comprising: a color filter array (CFA) 810-814, and microlens array 816 disposed on the backside surface of the second chip 802. See para. 0047, and fig. 8.
Regarding claim 11, Huang discloses a semiconductor device, comprising:
a first chip 102 (see figs. 2A, 14A/B) that includes a first wafer 104 and a first dielectric layer 202/2024 disposed thereon;
a second chip 201 that includes a second wafer 224 and a second dielectric layer 212/214 disposed thereon, with a bond pad 216 disposed within the second dielectric layer 212/214, the second chip 201 having a backside surface and a frontside surface opposed to the backside surface and being bonded to the first chip 102 at the frontside surface to define a bond line (alone the interface between the chips 102, 201) between the first dielectric layer 202/204 and the second dielectric layer 212/214; and
an opening 1408 (fig. 14A) through the backside surface of the second chip 201 and through the second wafer 224, the opening 1408 extending into the second dielectric layer 212/214 to expose only a portion of an upper surface of the bond pad 216 for electrical connection (via bond bad 226/226b) thereto.
Regarding claim 12, Huang discloses the semiconductor device of claim 11, wherein an entirety of the bond pad 216 is positioned below the second wafer 224 in a direction of the first chip 102. See fig. 2A.
Regarding claim 14, Huang discloses the semiconductor device of claim 11, further comprising: a moisture-resistant seal ring 228/230 at least partially surrounding the opening. See fig. 2A, and para. 0027.
Regarding claim 15, Huang discloses the semiconductor device of claim 14, wherein the bond pad 216 extends beyond the moisture-resistant seal ring 228/230 in a direction parallel to the bond line. See fig. 8.
Regarding claim 21, Huang discloses a semiconductor device, comprising:
a first chip 102 (see figs. 2A, 14A/B) that includes a first wafer 204 and a first dielectric layer 202/204 disposed thereon;
a second chip 201 that includes a second wafer 224 and a second dielectric layer 212/214 disposed thereon, the second chip 201 having a backside surface and a frontside surface opposed to the backside surface and being bonded to the first chip 102 at the frontside surface to define a bond line (alone the interface between the chips 102, 201) between the first dielectric layer and the second dielectric layer;
a bond pad 216 disposed within the second dielectric layer 212/214 between the bond line and the second wafer 224;
an opening 1408 (fig. 14A) through the backside surface of the second chip 201 and through the second wafer 224, the opening 1408 extending into the second dielectric layer 212/214 to expose a portion of an upper surface of the bond pad 216; and
an external connection 226/226b and/or 712 (fig. 8) to the semiconductor device that is electrically connected to the bond pad 216 through the opening.
Regarding claim 22, Huang discloses the semiconductor device of claim 21, wherein an entirety of the bond pad 216 is positioned below the second wafer 224 in a direction of the first chip 102. See fig. 2A.
Regarding claim 24, Huang discloses the semiconductor device of claim 21, further comprising: a moisture-resistant seal ring 228/230 at least partially surrounding the opening. See figs. 2A, and para. 0027.
Regarding claim 25, Huang discloses the semiconductor device of claim 24, wherein the bond pad 216 extends beyond the moisture-resistant seal ring 228/230 in a direction parallel to the bond line. See fig. 2A., fig. 8.
7. Claims 1, 5-7, 11, 14, 15, 21, 24, and 25 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Iwata (US 12,396,274)
Regarding claim 1, Iwata discloses a semiconductor device, comprising:
a first chip 401 (see fig. 5) that includes a first wafer 411 and a first dielectric layer 412 disposed thereon;
a second chip 301 that includes a second wafer 311 and a second dielectric layer 312 disposed thereon, the second chip having a backside surface and a frontside surface opposed to the backside surface, the second chip 301 being bonded to the first chip 401 at the frontside surface to define a bond line 314, 414 between the first dielectric layer 412 and the second dielectric layer 312;
an opening 501-503 through the backside surface of the second chip 301 that extends into the second dielectric layer 312; and
a bond pad 511-513 disposed within the second dielectric layer between the second wafer 311 and the bond line 314, 414, and extending beyond the opening 501-503 in a direction parallel to the bond line.
Regarding claim 5, Iwata discloses the semiconductor device of claim 1, further comprising: a moisture-resistant seal ring 541 at least partially surrounding the opening 501-503. See fig. 5.
Regarding claim 6, Iwata discloses the semiconductor device of claim 5, wherein the bond pad 501 extends beyond the moisture-resistant seal ring 541 in the direction parallel to the bond line 314, 414. See fig. 5.
Regarding claim 7, Iwata discloses the semiconductor device of claim 1, further comprising: a copper-copper hybrid bond 332/333 – 432/433 & 312 – 412 bonding the second chip 301 to the first chip 401 and defining the bond line. See fig. 5.
Regarding claim 11, Iwata discloses a semiconductor device, comprising:
a first chip 401 (fig. 5) that includes a first wafer 411 and a first dielectric layer 412 disposed thereon;
a second chip 301 that includes a second wafer 311 and a second dielectric layer 312 disposed thereon, with a bond pad 511-513 disposed within the second dielectric layer 312, the second chip 301 having a backside surface and a frontside surface opposed to the backside surface and being bonded to the first chip 401 at the frontside surface to define a bond line 314, 414 between the first dielectric layer 412 and the second dielectric layer 312; and
an opening 501-503 through the backside surface of the second chip 301 and through the second wafer 311, the opening extending into the second dielectric layer 312 to expose only a portion of an upper surface of the bond pad 501-503 for electrical connection thereto.
Regarding claim 14, Iwata discloses the semiconductor device of claim 11, further comprising:
a moisture-resistant seal ring 541 at least partially surrounding the opening 501-503. See fig. 5.
Regarding claim 15, Iwata discloses the semiconductor device of claim 14, wherein the bond pad 511 extends beyond the moisture-resistant seal ring 541 in a direction parallel to the bond line 314, 414. See fig. 5.
Regarding claim 21, Iwata discloses a semiconductor device, comprising:
a first chip 401 (see fig. 5) that includes a first wafer 411 and a first dielectric layer 412 disposed thereon;
a second chip 301 that includes a second wafer 311 and a second dielectric layer 312 disposed thereon, the second chip having a backside surface and a frontside surface opposed to the backside surface and being bonded to the first chip 401 at the frontside surface to define a bond 314, 414 line between the first dielectric layer 412 and the second dielectric layer 312;
a bond pad 511-513 disposed within the second dielectric layer 312 between the bond line 314, 414 and the second wafer 311;
an opening 501-503 through the backside surface of the second chip 301 and through the second wafer 311, the opening extending into the second dielectric layer 312 to expose a portion of an upper surface of the bond pad 511-513; and
an external connection (solders and wires) to the semiconductor device that is electrically connected to the bond pad 511-513 through the opening 501-503 (see fig. 5).
Regarding claim 24, Iwata discloses the semiconductor device of claim 21, further comprising: a moisture-resistant seal ring 541 at least partially surrounding the opening 501-503. See fig. 5.
Regarding claim 25, Iwata discloses the semiconductor device of claim 24, wherein the bond pad 511 extends beyond the moisture-resistant seal ring 541 in a direction parallel to the bond line 314, 414. See fig. 5.
Claim Rejections - 35 U.S.C. § 103
8. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
9. Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Iwata (US 12,396,274)
Regarding claim 8, Iwata discloses the semiconductor device of claim 1, comprising all claimed limitations, as discussed above, except for wherein a thickness of the bond pad is at least 1 micron.
However, it has been held that where the only difference between the prior art and the claims was a recitation of relative dimensions/thickness of the claimed element, and a device having the claimed relative dimensions/thickness would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device (MPEP §2144.04). It would have been obvious that a mere change in size/thickness of a component is generally recognized as being within the level of ordinary skill in the art.
It is to be expected that a change in size, thickness would be an unpatentable modification.
Under some circumstances, however, changes such as these may impart patentability to a process if the particular ranges claimed produce a new and unexpected result which is different in kind and not merely degree from the results of the prior art...such ranges are termed "critical ranges and the applicant has the burden of proving such criticality. See In re Aller, 220 F.2d 454, 105 USPQ 233,235 (CCPA 1955).
The instant specification contains no disclosure of either the critical nature of the claimed dimensions/thickness or of any unexpected results arising therefrom. Where patentability is aid to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. (.In re Woodruff, 919 F.2d 1575, 1578 (Fed. Cir. 1990).)
The claimed limitation regarding to the thickness of the bonding pad do/does not bear any critical point that would establish patentability, and is/are not sufficient to patentable distinguish over the prior art, therefore being considered as unpatentable limitation(s) because it would have involve only a mere change in size/thickness of a component. A change in size/shape is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). See MPEP §2144.04).
Allowable Subject Matter
10. Claims 4, 13, and 23 allowable.
Claims 4, 13, and 23 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest the claimed semiconductor device (in addition to the other limitations in the claim) further comprising:
a moisture-resistant dielectric within the second dielectric layer and coplanar with the bond pad, and blocking a moisture path between the opening and the bond pad.
Conclusion
11. A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the day of this letter. Failure to respond within the period for response will cause the application to become abandoned (see M.P.E.P 710.02(b)).
A shortened time for reply may be extended up to the maximum six-month period (35 U.S.C. 133). An extension of time fee is normally required to be paid if the reply period is extended. The amount of the fee is dependent upon the length of the extension. Extensions of time are generally not available after an application has been allowed.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Dao H. Nguyen whose telephone number is (571)272-1791. The examiner can normally be reached on Monday-Friday, 9:00 AM – 5:00 PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke, can be reached on (571)272-1657. The fax numbers for all communication(s) is 571-273-8300.
Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (571)272-1633.
/DAO H NGUYEN/Primary Examiner, Art Unit 2818 December 13, 2025