Prosecution Insights
Last updated: April 18, 2026
Application No. 18/310,072

ELECTRONIC PACKAGE AND MANUFACTURING METHOD THEREOF

Non-Final OA §103
Filed
May 01, 2023
Examiner
TYNES JR., LAWRENCE C
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Siliconware Precision Industries Co. Ltd.
OA Round
2 (Non-Final)
85%
Grant Probability
Favorable
2-3
OA Rounds
2y 5m
To Grant
94%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allow Rate
649 granted / 763 resolved
+17.1% vs TC avg
Moderate +9% lift
Without
With
+8.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
38 currently pending
Career history
801
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
53.4%
+13.4% vs TC avg
§102
30.5%
-9.5% vs TC avg
§112
10.7%
-29.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 763 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant’s arguments, see Remarks, filed December 23, 2025, with respect to the rejection(s) of claim(s) 1-28 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Liang et al. (US-20150235915-A1; Liang). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-11,13-25,27,28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 20210043557 A1; Lee) in view of Liang et al. (US-20150235915-A1; Liang ) . Regarding claim 1, Lee discloses an electronic package, comprising: an electronic module (Fig.30, 79,565-2; ¶440) including an encapsulation layer (Fig.30, 565-2; ¶439), at least one bridge component (Fig.30, 471; ¶439) embedded in the encapsulation layer and at least one conductive pillar (Fig.30, 358; ¶439) embedded in the encapsulation layer; and a packaging module (Fig.30, 101/565-1/399-2/399-1; ¶429,436) stacked on the electronic module via a plurality of supporting elements (Fig.30, 563; ¶437) and including a circuit structure (Fig.30, 101; ¶437) and a plurality of electronic elements (Fig.30, 399-1/399-2; ¶436) disposed on the circuit structure, wherein the circuit structure is electrically connected to the bridge component and the conductive pillar via the plurality of supporting elements, and wherein the plurality of electronic elements are electrically bridged with each other via the circuit structure, the plurality of supporting elements and the bridge component. (clear from figures) Lee is silent on and a circuit build-up structure formed on the encapsulation layer; … wherein the plurality of supporting elements directly contact the circuit structure and the circuit build-up structure, the circuit structure and the circuit build-up structure are separate and connected by the plurality of supporting elements, and the circuit structure is electrically connected to the bridge component and the conductive pillar via the plurality of supporting elements and the circuit build-up structure, and wherein the plurality of electronic elements are electrically bridged with each other via the circuit structure, the plurality of supporting elements, the circuit build-up structure and the bridge component. At issue is a build-up structure between the electronic module and packaging module. Liang discloses an electronic package comprising a build-up structure (Fig. 10, 316; ¶86) between an electronic module (Fig. 10, 318; ¶86), a package module (Fig. 10, 550; ¶87); where electronic module and the packaging module are connected through supporting elements (Fig. 10, 218; ¶87) and the build-up structure, the build-up structure and the circuit structure are separate and connected through the supporting elements. Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to add a build-up structure between the modules of Lee for increasing the connection capacity/density of the overall package Regarding claim 2, Lee in view of Liang discloses the electronic package of claim 1, wherein the circuit structure (Fig.30, 101; ¶437) is defined with a first block (region of 101) corresponding to configuration of the bridge component (Fig.30, 471; ¶439) and a second block (second region of 101) corresponding to configuration of the conductive pillar (Fig.30, 358; ¶439), such that the first block has a first conductive portion (Fig.30, unlabeled pads of 101 aligned with 471 ; ¶440) electrically connected to the bridge component, and the second block has a second conductive portion (Fig.30, unlabeled pads of 101 aligned 358; ¶440) electrically connected to the conductive pillar. Regarding claim 3, Lee in view of Liang discloses the electronic package of claim 2, but is silent on wherein a line pitch of the first conductive portion and/or the second conductive portion is at most 45um. Applicant defines pitch as being from midpoint to midpoint of the conductive portion. Lee (¶10,123) discloses conductive portions having a diameter (Fig. 22A, 34 w2; ¶123) of 25um -150um and being spaced apart by less than 30um. Calculating the pitch as defined by the applicant would be 13 um plus a spacing distance of <30um plus13 um. Lees bridge side conductive portions are aligned with the die side conductive portions. It is reasonable to conclude the same pitch on both sides of 101. Therefore , Lee's pitch would be < 56 um which provides a range that overlaps the claimed range of "at most 45um". At most 45 um is interpreted as less than or equal to 45 um. While, Lee does not expressly teaches the range of at most 45um some of its value ” < 56 um” fall within the claim range of at most 45um, in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. See MPEP 2144.05, I. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to enable using “< 56 um”, as disclosed in prior art, to arrive at the recited limitation. Also, before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to adjust the size and spacing of conductive portions to increase circuit density. Regarding claim 4, Lee in view of Liang discloses the electronic package of claim 2, wherein the plurality of supporting elements (Fig.30, 563; ¶437) are defined with at least one first connecting portion (Fig.30, first 563; ¶437) electrically connected to the first block (region of 101) and the bridge component (Fig.30, 471; ¶439) and at least one second connecting portion (Fig.30, second 563; ¶437) electrically connected to the second block (second region of 101) and the conductive pillar (Fig.30, 358; ¶439) , and wherein a width of the first connecting portion (Fig.30, first 563; ¶437) is different from a line pitch of the first conductive portion. (Fig.30, unlabeled pads of 101 aligned with 471 ; ¶440) The width of 563 is less than a midpoint to midpoint distance (pitch) of the first conductive portion. Regarding claim 5, Lee in view of Liang discloses the electronic package of claim 1, wherein the plurality of supporting elements (Fig.30, 563; ¶437) are defined with at least one first connecting portion electrically connected to the bridge component (Fig.30, 471; ¶439) and at least one second connecting portion electrically connected to the conductive pillar (Fig.30, 358; ¶439), such that the first connecting portion (Fig.30, first 563; ¶437) is electrically connected to the bridge component and the circuit structure (Fig.30, 101; ¶437), and the second connecting portion (Fig.30, second 563; ¶437)is electrically connected to the conductive pillar and the circuit structure. (Fig.30, 101; ¶437) Regarding claim 6, Lee discloses the electronic package of claim 5, but is silent on wherein a width of the first connecting portion is at most 55 μm. Liang discloses an analogous first portion (Fig. 1N, 24; ¶29) of about 40mu Before the effective filing date it would have been obvious to one having ordinary skill to have a small connecting portion first portion to allow higher density connections as is common between bridge die and semiconductor die. Regarding claim 7, Lee discloses the electronic package of claim 5, but is silent on wherein a width of the second connecting portion is at least 100 μm. Liang discloses an analogous second portion (Fig. 1N, 26; ¶29) of about 140mu Before the effective filing date it would have been obvious to one having ordinary skill to have a large connecting portion first portion to allow stronger mechanical bonds between upper and lower layers. Regarding claim 8, Lee discloses the electronic package of claim 5, but is silent on wherein a width of the first connecting portion and a width of the second connecting portion are different. Liang discloses connecting portions (Fig. 1N,24/ 26; ¶29)of different widths Liang discloses connecting portions of different widths . Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to have different connecting portion widths for higher density connections on the bridge and stronger mechanical support away from the bridge. Regarding claim 9, Lee in view of Liang discloses the electronic package of claim 5, but is silent on wherein a width of the first connecting portion is the same as a line pitch of the bridge component. This is merely an adjustment in size or position of a disclosed element which would not modify the operation of the device. Therefore, before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to change the size or position of the connecting portion as an obvious matter of design choice. 2144.04 (VI)(C) Also, where the only difference between the prior art and the claims is a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. MPEP 2144.04 IV A Regarding claim 10, Lee in view of Liang discloses the electronic package of claim 1, wherein the electronic module (Fig.30, 79,565-2; ¶440) further includes a routing structure (Fig.30, 79; ¶440) formed on the encapsulation layer (Fig.30, 565-2; ¶438), and wherein the routing structure is electrically connected to the conductive pillar (Fig.30, 358; ¶439) and the bridge component. (Fig.30, 471; ¶438) Regarding claim 11, Lee in view of Liang discloses the electronic package of claim 10, wherein the electronic module (Fig.30, 79,565-2; ¶440) further includes a plurality of conductive elements (Fig.30, pads between 583 and 79; ¶441) formed on and electrically connected to the routing structure. (Fig.30, 79; ¶440) Regarding claim 13, Lee in view of Liang discloses the electronic package of claim 1, wherein the packaging module (Fig.30, 565-1,399-1,399-2; ¶436) further includes a packaging layer (Fig.30, 565-1; ¶436) encapsulating the plurality of electronic elements. (Fig.30, 399-1,399-2; ¶436) Regarding claim 14, Lee in view of Liang discloses the electronic package of claim 1, further comprising a packaging material (Fig.30, 564; ¶437) formed between the packaging module (Fig.30, 565-1,399-1,399-2; ¶436) and the electronic module (Fig.30, 79,565-2; ¶440) to encapsulate the plurality of supporting elements. (Fig.30, 563; ¶437) Regarding claim 15, Lee in view of Liang discloses a method of manufacturing an electronic package, comprising: providing an electronic module (Fig.30, 79,565-2; ¶440) and a packaging module (Fig.30, 565-1,399-1,399-2; ¶436), wherein the electronic module includes an encapsulation layer (Fig.30, 565-2; ¶440), at least one bridge component (Fig.30, 471; ¶440) embedded in the encapsulation layer and at least one conductive pillar (Fig.30,358; ¶440) embedded in the encapsulation layer, and wherein the packaging module includes a circuit structure (Fig.30, 101; ¶436) and a plurality of electronic elements (Fig.30, 399-1/399-2; ¶436) disposed on the circuit structure; and stacking the packaging module on the electronic module via a plurality of supporting elements (Fig.30, 563; ¶437) …, and the circuit structure is electrically connected to the bridge component and the conductive pillar via the plurality of supporting elements, and wherein the plurality of electronic elements are electrically bridged with each other via the circuit structure, the plurality of supporting elements… and the bridge component. Lee is silent on and a circuit build-up structure formed on the encapsulation layer; … wherein the plurality of supporting elements directly contact the circuit structure and the circuit build-up structure, the circuit structure and the circuit build-up structure are separate and connected by the plurality of supporting elements, and the circuit structure is electrically connected to the bridge component and the conductive pillar via the plurality of supporting elements and the circuit build-up structure, and wherein the plurality of electronic elements are electrically bridged with each other via the circuit structure, the plurality of supporting elements, the circuit build-up structure and the bridge component. At issue is a build-up structure between the electronic module and packaging module. Liang discloses an electronic package comprising a build-up structure (Fig. 10, 316; ¶86) between an electronic module (Fig. 10, 318; ¶86), a package module (Fig. 10, 550; ¶87); where electronic module and the packaging module are connected through supporting elements (Fig. 10, 218; ¶87) and the build-up structure, the build-up structure and the circuit structure are separate and connected through the supporting elements. Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to add a build-up structure between the modules of Lee for increasing the connection capacity/density of the overall package Regarding claim 16, Lee in view of Liang discloses the method of claim 15, wherein the circuit structure (Fig.30, 101; ¶436) is defined with a first block (region of 101 overlapping 471) corresponding to configuration of the bridge (Fig.30, 471; ¶440) component and a second block (region of 101 overlapping 358) corresponding to configuration of the conductive pillar (Fig.30,358; ¶440), such that the first block has a first conductive portion (Fig.30, unlabeled pads of 101; ¶436) electrically connected to the bridge component, and the second block has a second conductive portion (Fig.30, unlabeled pads of 101; ¶436) electrically connected to the conductive pillar. Regarding claim 17, Lee in view of Liang discloses the method of claim 16, wherein a line pitch of the first conductive portion and/or the second conductive portion is at most 45 um. Applicant defines pitch as being from midpoint to midpoint of the conductive portion. Lee (¶10,123) discloses conductive portions having a diameter (Fig. 22A, 34 w2; ¶123) of 25um -150um and being spaced apart by less than 30um. Calculating the pitch as defined by the applicant would be 13 um plus a spacing distance of <30um plus13 um. Lee’s bridge side conductive portions are aligned with the die side conductive portions. It is reasonable to conclude the same pitch on both sides of 101. Therefore , Lee's pitch would be < 56 um which provides a range that overlaps the claimed range of "at most 45um". At most 45 um is interpreted as less than or equal to 45 um. While, Lee does not expressly teaches the range of at most 45um some of its value ” < 56 um” fall within the claim range of at most 45um, in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. See MPEP 2144.05, I. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to enable using “< 56 um”, as disclosed in prior art, to arrive at the recited limitation. Also, before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to adjust the size and spacing of conductive portions to increase circuit density. Regarding claim 18, Lee in view of Liang discloses the method of claim 16, wherein the plurality of supporting elements (Fig.30, 563; ¶437) are defined with at least one first connecting portion (Fig.30, first 563; ¶437) electrically connected to the first block (region of 101) and the bridge component (Fig.30, 471; ¶439) and at least one second connecting portion (Fig.30, second 563; ¶437) electrically connected to the second block (second region of 101) and the conductive pillar (Fig.30, 358; ¶439) , and wherein a width of the first connecting portion (Fig.30, first 563; ¶437) is different from a line pitch of the first conductive portion. (Fig.30, unlabeled pads of 101 aligned with 471 ; ¶440) The width of 563 is less than a midpoint to midpoint distance (pitch) of the first conductive portion. Regarding claim 19, Lee in view of Liang discloses the method of claim 15, wherein the plurality of supporting elements (Fig.30, 563; ¶437) are defined with at least one first connecting portion electrically connected to the bridge component (Fig.30, 471; ¶439) and at least one second connecting portion electrically connected to the conductive pillar (Fig.30, 358; ¶439), such that the first connecting portion (Fig.30, first 358; ¶439) is electrically connected to the bridge component and the circuit structure (Fig.30, 101; ¶437), and the second connecting portion(Fig.30, second 358; ¶439) is electrically connected to the conductive pillar and the circuit structure. (Fig.30, 101; ¶437) Regarding claim 20, Lee in view of Liang discloses the method of claim 19, but is silent on wherein a width of the first connecting portion is at most 55 μm. Liang discloses an analogous first portion (Fig. 1N, 24; ¶29) of about 40mu Before the effective filing date it would have been obvious to one having ordinary skill to have a small connecting portion first portion to allow higher density connections as is common between bridge die and semiconductor die. Regarding claim 21, Lee in view of Liang discloses the method of claim 19, but is silent on wherein a width of the second connecting portion is at least 100 μm. Liang discloses an analogous second portion (Fig. 1N, 26; ¶29) of about 140mu Before the effective filing date it would have been obvious to one having ordinary skill to have a large connecting portion first portion to allow stronger mechanical bonds between upper and lower layers. Regarding claim 22, Lee in view of Liang discloses the method of claim 19, but is silent on wherein a width of the first connecting portion and a width of the second connecting portion are different. Liang discloses connecting portions (Fig. 1N,24/ 26; ¶29)of different widths Liang discloses connecting portions of different widths . Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to have different connecting portion widths for higher density connections on the bridge and stronger mechanical support away from the bridge. Regarding claim 23, Lee in view of Liang discloses the method of claim 19, but is silent on wherein a width of the first connecting portion is the same as a line pitch of the bridge component. This is merely an adjustment in size or position of a disclosed element which would not modify the operation of the device. Therefore, before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to change the size or position of the connecting portion as an obvious matter of design choice. 2144.04 (VI)(C) Also, where the only difference between the prior art and the claims is a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. MPEP 2144.04 IV A Regarding claim 24, Lee in view of Liang discloses the method of claim 15, wherein the electronic module (Fig.30, 79,565-2; ¶440) further includes a routing structure (Fig.30, 79; ¶440) formed on the encapsulation layer (Fig.30, 565-2; ¶438), and wherein the routing structure is electrically connected to the conductive pillar (Fig.30, 358; ¶439) and the bridge component. (Fig.30, 471; ¶438) Regarding claim 25, Lee in view of Liang discloses the method of claim 24, wherein the electronic module (Fig.30, 79,565-2; ¶440) further includes a plurality of conductive elements (Fig.30,pads between 583 and 79; ¶443) formed on and electrically connected to the routing structure. Regarding claim 27, Lee in view of Liang discloses the method of claim 15, wherein the packaging module (Fig.30, 565-1,399-1,399-2; ¶436) further includes a packaging layer (Fig.30, 565-1; ¶436)encapsulating the plurality of electronic elements. (Fig.30, 399-1,399-2; ¶436) Regarding claim 28, Lee in view of Liang discloses the method of claim 15, further comprising a packaging material (Fig.30, 564; ¶437) between the packaging module (Fig.30, 565-1,399-1,399-2; ¶436) and the electronic module (Fig.30, 79,565-2; ¶440) to encapsulate the plurality of supporting elements. (Fig.30, 563; ¶437) Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAWRENCE C TYNES JR. whose telephone number is (571)270-7606. The examiner can normally be reached 9AM-5PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached at 571-272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /LAWRENCE C TYNES JR./Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

May 01, 2023
Application Filed
Oct 04, 2025
Non-Final Rejection — §103
Dec 23, 2025
Response Filed
Apr 03, 2026
Non-Final Rejection — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12604595
DISPLAY DEVICE AND SPLICING DISPLAY DEVICE
2y 5m to grant Granted Apr 14, 2026
Patent 12604512
TRENCH MOSFET AND MANUFACTURING METHOD THEREFOR
2y 5m to grant Granted Apr 14, 2026
Patent 12593696
CHIP ON FILM PACKAGE AND DISPLAY DEVICE INCLUDING THE SAME
2y 5m to grant Granted Mar 31, 2026
Patent 12588494
DIE STITCHING AND HARVESTING OF ARRAYED STRUCTURES
2y 5m to grant Granted Mar 24, 2026
Patent 12575432
CHIP FINE LINE FAN-OUT PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREFOR
2y 5m to grant Granted Mar 10, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

2-3
Expected OA Rounds
85%
Grant Probability
94%
With Interview (+8.9%)
2y 5m
Median Time to Grant
Moderate
PTA Risk
Based on 763 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month