DETAILED ACTION
This Office action responds to the Amendments After Final Action filed on March 18, 2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant argues the Cheng et al. (US 2024/0088074) is not qualified prior art under the exception under 35 U.S.C. 102(b)(2)(C). Hence, the rejections relying on Cheng et al. has been withdrawn. Different prior arts published prior to the filing date of this application were found to reject Claims 19 and 21-23 under 35 U.S.C. 103.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 19 and 21-23 are rejected under 35 U.S.C. 103 as being unpatentable over Shen et al. (Shen hereinafter) (US 2021/0098400) in view of Yang et al. (Yang hereinafter) (US 2022/0367347).
Regarding Claims 19 and 21-23:
Shen (see Figs. 8-14B) teaches {19} a chip package structure, comprising: a die provided with a contact 209; a redistribution layer (RDL) feature 230 formed over the die, and electrically connected to the contact, wherein the RDL feature has a curved top surface 230C; and a bare passivation layer 240 over the RDL feature, and having an opening 242 over a portion of the RDL feature; {21} the RDL feature has a tapered side surface 230B; {22} a conductive layer 250 conformally disposed on the RDL feature and a side surface of the bare passivation layer in the opening, and on a portion of a top surface of the bare passivation layer adjacent to the opening; a metal pillar 250 disposed over the conductive layer and the RDL feature, and extending into the opening; and a solder ball 252 disposed over the metal pillar; and {23} the metal pillar has a side surface coplanar with a side surface of the conductive layer.
Shen (see ¶ [0003], [0039]-[0041]) teaches “ICs are formed on a semiconductor substrate that may be cut into individual device dies or IC chips. Each IC chip may be … to form a package or a device … a redistribution layer (RD) of conductive lines may be formed on an IC chip to reroute bond connection … one or more passivation layers have been implemented around the RDL to protect the semiconductor surface” and “the bump 250 includes a bulk conductive layer … may optionally include a seed layer (not depicted) disposed under the bulk conductive layer in the opening 248”; and “a solder layer (e.g., solder layer 252) is subsequently formed over the bump 250”; “the solder layer 252 may include … an alloy containing tin, silver, and cover”.
Yang (see FIGs. 1I and 1J and ¶ [0080]) teaches a chip structure comprising conductive layer 180 with a curved top surface, a passivation layer 190, a seed layer 220, a conductive layer 240, and a solder layer 250 and “the mask layer 230 is removed … the seed layer 220 originally under the mask layer 230 is removed”.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the teaching of Shen to further include the teaching of Yang to utilize the semiconductor structure with the redistribution layer and multiple passivation layers to interconnect the dies or chips in a semiconductor package and to expect the sides of the bump 250 and the underlying seed layer are coplanar which is a common practice in the semiconductor art.
Allowable Subject Matter
Claims are 1, 13, and 24-37 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding Claim 1: The prior art of record neither anticipates nor render obvious a method of forming a redistribution layer (RDL) structure, wherein patterning the passivation layer using the patterned etch mask layer disposed on the passivation layer to make the portion of the passivation layer cover the RDL feature with a reduced thickness; etching the passivation layer after the step of removing the patterned etch mask layer to remove the portion of the passivation layer that covers the RDL feature with the reduced thickness, thereby forming a passivation opening in the passivation layer, wherein the portion of the RDL feature is exposed through the passivation opening; and the passivation layer is completely exposed to an etchant that is used to etch the passivation layer. These features in combination with other elements in the claim are neither disclosed nor suggested by the prior art of record.
Regarding Claim 13: The prior art of record neither anticipates nor renders obvious a method for forming a redistribution layer (RDL) structure, wherein etching the metal seed layer and the barrier layer to remove the portion of the metal seed layer and a portion of the barrier layer that is outside the coverage of the RDL feature, wherein the etching of the metal seed layer and the barrier layer causes the RDL feature to have a tapered side surface; and performing a first etching on the second passivation layer with the second patterned photoresist layer serving as an etch mask to make the portion of the second passivation layer thinner than other portions of the second passivation layer that are covered by the second passivation layer. These features in combination with other elements in the claim are neither disclosed nor suggested by the prior art of record.
Claims 24-37 depend on Claim 1 or 13 so they are allowable for the same reason.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Correspondence
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALICE W TANG whose telephone number is (571)272-7227. The examiner can normally be reached Monday-Friday: 8:30 am to 5 pm..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached at (571)272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALICE W TANG/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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