DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant’s election without traverse of Group I, species 3 (1, 3, 4, 6-16, 21-24) in the reply filed on 02/03/2026 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 is not clear because it recites the limitation “wherein the BEOL memory die… has a lateral extent that is less than a lateral extent of each memory cell within the array of memory cells”. For the purpose of examination, the Examiner assumes the above limitation of ““wherein the BEOL memory die… has a lateral extent that is less than a lateral extent of each memory cell within the array of memory cells” is:
“wherein the BEOL memory die… has a lateral extent that is greater than a lateral extent of each memory cell within the array of memory cells” (emphasis added).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 3, 4, 6-16, 21-24 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by OKADA (U.S 2023/0307397 A1).
As to claim 1, OKADA discloses in Fig. 4 a chip assembly structure comprising: a first chip-containing structure (comprising 10, 110 & 20) that comprises a back-end-of-line (BEOL) memory die (“semiconductor chip” 10) including an array of memory cells (“the memory cell array” 110) (Fig. 4, [0070]-[0077], [0092]) and metal interconnect structures (comprising M0, M1, 31, 21, 31x, 32x, 32a, 32b, 391, 392, V1, & VB) that are electrically connected to a respective node of the array of memory cells (“the memory cell array” 110) (Fig. 4B, para. [0072], [0087], [0109]-[0113]), wherein the BEOL memory die (“semiconductor chip” 10) is free of any semiconductor material portion or each semiconductor material portions within the BEOL memory die (10) (see Fig. 4) has a lateral extent that is greater than a lateral extent of each memory cell (110) within the array of memory cells (110) (Fig. 4), the first chip-containing structure (comprising 10, 110 & 20) comprises first bonding structures (comprising VB & 392), and a subset of the first bonding structures (VB & 391-392) is electrically connected to the metal interconnect structures (comprising M0, M1, 31, 21, 31x, 32x, 32a, 32b, V1) in the BEOL memory die (10); and a second chip-containing structure (11/200, Figs. 3-4) comprises a control circuit (140, Figs. 1, 3-4, para. [0055]) including field effect transistors (TR) which are configured to control operation of the array of memory cells and further comprises second bonding structures (comprising CB & 491-492) (Fig. 4, para. [0115]-[0117]), wherein the second bonding structures (CB & 491-492) are bonded to the first bonding structures (VB & 392) through metal-to-metal bonding (metal-to-metal bonding is the bonds of CB, 491-492 and VB, 391-392, Fig. 4) (Fig. 4, para. [0074], [0076]-[0080], [0113], [0127]) or through-substrate-via-mediated bonding.
As to claim 3, as applied to claim 1 above, OKADA discloses in Fig. 4 all claimed limitations including the limitation: wherein at least one set of bonding structures (comprising VB, 392, CB, 491-492) selected from the first bonding structures (comprising VB & 392) or the second bonding structures (comprising CB & 491-492) comprise an array of metal bonding pads (“bonding members”/”vias” VB or CB) having a respective lateral dimension that is greater than a respective thickness (Fig. 4, para. [0076]-[0080]).
As to claim 4, as applied to claim 1 above, OKADA discloses in Fig. 4 all claimed limitations including the limitation: wherein: the first bonding structures (comprising VB & 392) are laterally surrounded by a first bonding-level dielectric layer (“the interlayer insulating film” that covers/includes VB, para. [0113]); the second bonding structures (comprising CB & 491-492) are laterally surrounded by a second bonding-level dielectric layer (“the interlayer insulating film” that covers/includes CB, para. [0127]) (Fig. 4, para. [0113], [0127]); and the second bonding-level dielectric layer (“the interlayer insulating film” that covers/includes CB, para. [0127]) is bonded to the first bonding-level dielectric layer (“the interlayer insulating film” that covers/includes VB, para. [0113]) through dielectric-to-dielectric bonding (the bonds between “the interlayer insulating film” that covers/includes VB and “the interlayer insulating film” that covers/includes CB, para. [0113], [0127]) (Fig. 4, para. [0113], [0127]).
As to claim 6, as applied to claim 1 above, OKADA discloses in Fig. 4 all claimed limitations including the limitation: wherein the BEOL memory die (“semiconductor chip” 10) is free of any field effect transistor (see Fig. 4).
As to claim 7, as applied to claim 1 above, OKADA discloses in Fig. 4 all claimed limitations including the limitation: wherein the BEOL memory die (“semiconductor chip” 10) is free of any semiconductor material (see Fig. 4).
As to claim 8, as applied to claim 1 above, OKADA discloses in Fig. 4 all claimed limitations including the limitation: where in: the array of memory cells (“the memory cell array” 110) and the metal interconnect structures (comprising M0, M1, 31, 21, 31x, 32x, 32a, 32b, 391, 392, V1, & VB) are laterally surrounded by a set of dielectric material layers (“the interlayer insulating film” that covers memory cells and metal interconnect structures, para. [0109], [0113]) (see Fig. 4, para. [0109], [0113]); and the set of dielectric material layers (“the interlayer insulating film”, para. [0109], [0113]) continuously extends from a bottom surface of the BEOL memory die (“semiconductor chip” 10) to a top surface of the BEOL memory die (“semiconductor chip” 10) without spacing between any neighboring pair of dielectric material layers (“the interlayer insulating film”, para. [0109], [0113]) within the set of dielectric material layers (“the interlayer insulating film”, para. [0109], [0113]) (see Fig. 4, para. [0109], [0113]).
As to claim 9, as applied to claim 1 above, OKADA discloses in Fig. 4 all claimed limitations including the limitation: wherein: the control circuit (140, Figs. 1, 3-4, para. [0055]) comprises a complementary metal-oxide-semiconductor (CMOS) circuit (200) located on a single crystalline semiconductor substrate (40) (Fig. 4, para. [0125]-[0127]); and additional metal interconnect structures {comprising “plurality of interconnect levels” D1, D2, D3, and D4; “contacts” C1, CS; “vias” C2, C3, and C4; and “conductive layers (interconnects)” 51, 52, 53, and 54} are located between the CMOS circuit (200) and the second bonding structures (comprising CB & 491-492) (Fig. 4, para. [0121], [0122], [0125]).
As to claim 10, as applied to claim 1 above, OKADA discloses in Fig. 4 all claimed limitations including the limitation: wherein: the first chip-containing structure (comprising 10, 110 & 20) comprises a redistribution structure (comprising “conductive layers” 32a and “the interlayer insulating film”, para. [0109], [0113]) including redistribution dielectric layers (“the interlayer insulating film”, para. [0109], [0113]) and redistribution wiring interconnects (“conductive layers” 32a) (Fig. 4, para. [0109], [0110], [0113]); the first bonding structures (comprising VB & 392) are located within the redistribution structure (comprising “conductive layers” 32a and “the interlayer insulating film”, para. [0109], [0113]) (Fig. 4, para. [0109], [0113]); and the BEOL memory die (“semiconductor chip” 10) is located on the redistribution structure (comprising “conductive layers” 32a and “the interlayer insulating film”, para. [0109], [0113]) on an opposite side of the second chip-containing structure (11/200, Figs. 3-4) (Fig. 4).
As to claim 11, as applied to claim 1 above, OKADA discloses in Fig. 4 all claimed limitations including the limitation: wherein: the first chip-containing structure (comprising 10, 110 & 20) comprises an interposer (comprising “conductive layers” 32a and “the interlayer insulating film”, para. [0109], [0113]) including redistribution dielectric layers (“the interlayer insulating film”, para. [0109], [0113]) and redistribution wiring interconnects (“conductive layers” 32a) (Fig. 4, para. [0109], [0110], [0113]); the first bonding structures (comprising VB & 392) are located within the interposer (Fig. 4, para. [0109], [0113]); and the BEOL memory die (“semiconductor chip” 10) is attached to the interposer (comprising “conductive layers” 32a and “the interlayer insulating film”, para. [0109], [0113]) on an opposite side of the second chip-containing structure (11/200, Figs. 3-4) via an array of solder material portions or via metal-to-metal bonding (the bonds of VB & CB) (Fig. 4) or through-substrate-via-mediated bonding.
As to claim 12, as applied to claim 1 above, OKADA discloses in Fig. 4 all claimed limitations including the limitation: wherein the first bonding structures (comprising VB & 392) are located within the BEOL memory die (“semiconductor chip” 10) (Fig. 4).
As to claim 13, OKADA discloses in Fig. 4 a chip assembly structure comprising: a first chip-containing structure (comprising 10, 110 & 20) that comprises a back-end-of-line (BEOL) memory die (“semiconductor chip” 10) including an array of memory cells (“the memory cell array” 110) (Fig. 4, [0070]-[0077], [0092]) and metal interconnect structures (comprising M0, M1, 31, 21, 31x, 32x, 32a, 32b, 391, 392, V1, & VB) that are electrically connected to a respective node of the array of memory cells (“the memory cell array” 110) (Fig. 4B, para. [0072], [0087], [0109]-[0113]), wherein the BEOL memory die (“semiconductor chip” 10) is free of any field effect transistors (see Fig. 4), the first chip-containing structure (comprising 10, 110 & 20) comprises first bonding structures (comprising VB & 392), and a subset of the first bonding structures (VB & 391-392) is electrically connected to the metal interconnect structures (comprising M0, M1, 31, 21, 31x, 32x, 32a, 32b, V1) in the BEOL memory die (10); and a second chip-containing structure (11/200, Figs. 3-4) comprises a control circuit (140, Figs. 1, 3-4, para. [0055]) including field effect transistors (TR) which are configured to control operation of the array of memory cells and further comprises second bonding structures (comprising CB & 491-492) (Fig. 4, para. [0115]-[0117]), wherein the second bonding structures (CB & 491-492) are bonded to the first bonding structures (VB & 392) through metal-to-metal bonding (metal-to-metal bonding is the bonds of CB, 491-492 and VB, 391-392, Fig. 4) (Fig. 4, para. [0074], [0076]-[0080], [0113], [0127]) or through-substrate-via-mediated bonding.
As to claim 14, as applied to claim 13 above, OKADA discloses in Fig. 4 all claimed limitations including the limitation: wherein a memory cell of the array of memory cells (“the memory cell array” 110) comprises a respective memory cell that is selected from: a resistive random access memory cell; a conductive bridge random access memory cell; a phase change memory cell (“a phase change random access memory (PCRAM)”, para. [0337]); a magneto resistive random access memory cell; a dynamic random access memory cell (“DRAM”, para. [0314], [0316], [0337]); or a ferroelectric random access memory cell.
As to claim 15, as applied to claim 13 above, OKADA discloses in Fig. 4 all claimed limitations including the limitation: wherein the BEOL memory die (“semiconductor chip” 10) further comprises an array of selector cells, wherein: a selector cell of the array of selector cells (“the memory cell array” 110) is electrically connected to a respective memory cell (“the memory cell array” 110) within the array of memory cells (“the memory cell array” 110); and each of the array of selector cells comprises a respective the selector cell (“the memory cell array” 110) that is selected from: an oxygen-vacancy-based selector cell; a diode selector cell; a metal-insulator-metal selector cell; or an ovonic threshold switch selector cell (“word line switch” 14, para. [0045]) (Fig. 4, para. [0045], [0048]).
As to claim 16, as applied to claim 13 above, OKADA discloses in Fig. 4 all claimed limitations including the limitation: wherein: the array of memory cells (“the memory cell array” 110) and the metal interconnect structures (comprising M0, M1, 31, 21, 31x, 32x, 32a, 32b, V1) are laterally surrounded by a set of dielectric material layers (“the interlayer insulating film” that covers memory cells and metal interconnect structures, para. [0109], [0113]) (Fig. 4, para. [0109], [0113]); and the set of dielectric material layers (“the interlayer insulating film” that covers memory cells and metal interconnect structures, para. [0109], [0113]) continuously extends from a bottom surface of the BEOL memory die (“semiconductor chip” 10) to a top surface of the BEOL memory die (“semiconductor chip” 10) without spacing between any neighboring pair of dielectric material layers (“the interlayer insulating film” that covers memory cells and metal interconnect structures, para. [0109], [0113]) within the set of dielectric material layers (“the interlayer insulating film” that covers memory cells and metal interconnect structures, para. [0109], [0113]) (Fig. 4, para. [0109], [0113]).
As to claim 21, OKADA discloses in Fig. 4 a chip assembly structure comprising: a first chip-containing structure (comprising 10, 110 & 20) that comprises a back-end-of-line (BEOL) memory die (“semiconductor chip” 10) including an array of memory cells (“the memory cell array” 110) (Fig. 4, [0070]-[0077], [0092]) and metal interconnect structures (comprising M0, M1, 31, 21, 31x, 32x, 32a, 32b, 391, 392, V1, & VB) that are electrically connected to a respective node of the array of memory cells (“the memory cell array” 110) (Fig. 4B, para. [0072], [0087], [0109]-[0113]), wherein the BEOL memory die (“semiconductor chip” 10) is free of any field effect transistors and is free of any semiconductor substrate (see Fig. 4); a redistribution structure (comprising “conductive layers” 32a and “the interlayer insulating film”, para. [0109], [0113]) including redistribution dielectric layers (“the interlayer insulating film”, para. [0109], [0113]) and redistribution wiring interconnects (“conductive layers” 32a) (Fig. 4, para. [0109], [0110], [0113]), wherein the BEOL memory die (“semiconductor chip” 10) is attached to a first side of the redistribution structure (comprising “conductive layers” 32a and “the interlayer insulating film”, para. [0109], [0113]) and the first chip-containing structure (comprising 10, 110 & 20) comprises first bonding structures (comprising VB & 392) located on a second side of the redistribution structure (comprising “conductive layers” 32a and “the interlayer insulating film”, para. [0109], [0113]) opposite to the BEOL memory die (“semiconductor chip” 10) (Fig. 4), and wherein a subset of the first bonding structures (comprising VB & 392) is electrically connected to the metal interconnect structures (comprising M0, M1, 31, 21, 31x, 32x, 32a, 32b, 391, 392, V1, & VB) in the BEOL memory die (“semiconductor chip” 10) through the redistribution wiring interconnects (“conductive layers” 32a) (Fig. 4); and and a second chip-containing structure (11/200, Figs. 3-4) comprises a control circuit (140, Figs. 1, 3-4, para. [0055]) including field effect transistors (TR) which are configured to control operation of the array of memory cells and further comprises second bonding structures (comprising CB & 491-492) (Fig. 4, para. [0115]-[0117]), wherein the second bonding structures (CB & 491-492) are bonded to the first bonding structures (VB & 392) through metal-to-metal bonding (metal-to-metal bonding is the bonds of CB, 491-492 and VB, 391-392, Fig. 4) (Fig. 4, para. [0074], [0076]-[0080], [0113], [0127]) or through-substrate-via-mediated bonding.
As to claim 22, as applied to claim 21 above, OKADA discloses in Fig. 4 all claimed limitations including the limitation: wherein: the BEOL memory die (“semiconductor chip” 10) is free of any semiconductor material (Fig. 4); the array of memory cells (“the memory cell array” 110) and the metal interconnect structures (comprising M0, M1, 31, 21, 31x, 32x, 32a, 32b, 391, 392, V1, & VB) are laterally surrounded by a set of dielectric material layers (“the interlayer insulating film” that covers memory cells and metal interconnect structures, para. [0109], [0113]) (see Fig. 4, para. [0109], [0113]); and the set of dielectric material layers (“the interlayer insulating film”, para. [0109], [0113]) that continuously extends from a bottom surface of the BEOL memory die (“semiconductor chip” 10) to a top surface of the BEOL memory die (“semiconductor chip” 10) without spacing between any neighboring pair of dielectric material layers (“the interlayer insulating film”, para. [0109], [0113]) within the set of dielectric material layers (“the interlayer insulating film”, para. [0109], [0113]) (see Fig. 4, para. [0109], [0113]); or the BEOL memory die (“semiconductor chip” 10) is free of any field effect transistors (TR) and is free of any semiconductor substrate (Fig. 4).
As to claim 23, as applied to claim 21 above, OKADA discloses in Fig. 4 all claimed limitations including the limitation: wherein: the control circuit (140) comprises design-for-testability circuits, built-in-self-test circuits, error correction circuits, phase-locked loop circuits, electrically-programmable fuse circuits, and voltage generator circuits; or the control circuit (140) is shared by a plurality of vertically stacked BEOL memory dies (“semiconductor chip” 10) within the first chip-containing structure (comprising 10, 110 & 20) (Fig. 4, para. [0045]).
As to claim 24, as applied to claim 21 above, OKADA discloses in Fig. 4 all claimed limitations including the chip assembly structure further comprising a plurality of additional BEOL memory dies (“semiconductor chip” 10) vertically stacked within the first chip-containing structure (comprising 10, 110 & 20), wherein: the plurality of additional BEOL memory dies (“semiconductor chip” 10) are interconnected to one another through metal-to-metal bonding (VB and CB) or through-substrate-via-mediated bonding and share the control circuit (140) of the second chip-containing structure (11); or backside through-substrate via structures are formed on a backside of the second chip- containing structure (11) (Fig. 4).
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THANH Y TRAN whose telephone number is (571)272-2110. The examiner can normally be reached M-F, 10am-10pm (flex) (PST).
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/Thanh Y. Tran/Primary Examiner, Art Unit 2817
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