DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-10, 21, 22, 25-27 and 30-33 have been considered but are moot on grounds of new rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (Chen’933) (US 2021/0125933 A1) in view of KIM (US 2015/0113195 A1).
In regards to claim 1, Chen’933 (Fig. 14B and associated text) discloses a package structure (item 250), comprising: a substrate (items 200) comprising a package substrate upper dielectric layer (item 122, paragraph 35); a plurality of dies (items 54A, 54B) on the substrate; and a bridge die (item 50) embedded in the package substrate upper dielectric layer (item 122) and including a first input/output structure (item 14) connected to a first semiconductor die (items 54A or 54B) of the plurality of dies (items 54A, 54B), and a second input/output structure (item 14) connected to a second semiconductor die (items 54A or 54B) of the plurality of dies (items 54A, 54B), wherein the first semiconductor die (items 54A or 54B) is connected to the second semiconductor die (items 54A or 54B) through the bridge die (item 50), wherein the substrate (item 200) comprises a package substrate upper surface layer (item 106) contacting a top surface of the package substrate upper dielectric layer (item 122) and contacting sidewalls of the first input/output structure (item 14) and sidewalls of the second input/output structure (item 14), but does not specifically disclose a memory bridge die.
KIM (Figs. 1, 5B and associated text) discloses a universal memory bridge (items 2, 30).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of KIM for the purpose of and electrical connections/signals, memory control, performing or controlling error checking and correction, refresh and test operations (paragraph 51).
Claim(s) 1-10, 21, 25, 25-27, 29, 32 and 33 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (Chen) (US 2019/0131273 A1) in view of KIM (US 2015/0113195 A1) in view of Chen et al. (Chen’933) (US 2021/0125933 A1).
In regards to claim 1, Chen (Fig. 12 and associated text) discloses a package structure (item 12), comprising: a substrate (items RDL1 plus E1 plus RDL2 or RDL1 plus E1 plus 106) comprising a package substrate upper dielectric layer (items E1, E1 plus RDL2 or E1 plus 106); a plurality of dies (items 100, 200, 300, 400, 500, 600) on the substrate; and a bridge die (item 150) embedded in the package substrate upper dielectric layer (items E1, E1 plus RDL2 or E1 plus 106) and including a first input/output structure (outermost connector on the left or right shown but not labeled) connected to a first semiconductor die (items 300 or 400) of the plurality of dies (items 100, 200, 300, 400, 500, 600), and a second input/output structure (outermost connector on the left or right shown but not labeled) connected to a second semiconductor die (items 300 or 400) of the plurality of dies (items 100, 200, 300, 400, 500, 600), wherein the first semiconductor die (items 300 or 400) is connected to the second semiconductor die (items 300 or 400) through the bridge die (item 150), wherein the substrate (items RDL1 plus E1 plus RDL2 or RDL1 plus E1 plus 106) comprises a package substrate upper surface layer (item RDL2 or 108) contacting a top surface of the package substrate upper dielectric layer (item E1), but does not specifically disclose a memory bridge die.
KIM (Figs. 1, 5B and associated text) discloses a universal memory bridge (items 2, 30).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of KIM for the purpose of and electrical connections/signals, memory control, performing or controlling error checking and correction, refresh and test operations (paragraph 51).
Chen as modified by KIM does not specifically disclose wherein the substrate comprises a package substrate upper surface layer contacting a top surface of the package substrate upper dielectric layer and contacting sidewalls of the first input/output structure and sidewalls of the second input/output structure.
Chen’933 (Fig. 14B and associated text) discloses a package structure (item 250), comprising: a substrate (items 200) comprising a package substrate upper dielectric layer (item 122, paragraph 35); a plurality of dies (items 54A, 54B) on the substrate; and a bridge die (item 50) embedded in the package substrate upper dielectric layer (item 122) and including a first input/output structure (item 14) connected to a first semiconductor die (items 54A or 54B) of the plurality of dies (items 54A, 54B), and a second input/output structure (item 14) connected to a second semiconductor die (items 54A or 54B) of the plurality of dies (items 54A, 54B), wherein the first semiconductor die (items 54A or 54B) is connected to the second semiconductor die (items 54A or 54B) through the bridge die (item 50), wherein the substrate (item 200) comprises a package substrate upper surface layer (item 106) contacting a top surface of the package substrate upper dielectric layer (item 122) and contacting sidewalls of the first input/output structure (item 14) and sidewalls of the second input/output structure (item 14).
Therefore it would have been obvious to one of ordinary skill in the art to incorporate the teachings of Chen’933 for the purpose of protection.
In regards to claim 2, Chen (Fig. 12 and associated text) as modified KIM (Figs. 1, 5B and associated text) discloses wherein the substrate (items RDL1 plus E1 plus RDL2, Chen) comprises a package substrate (items RDL1 plus E1 plus RDL2, Chen) and the memory bridge die (item 150, Chen, items 2, 30, KIM) is located in the package substrate (items RDL1 plus E1 plus RDL2, Chen).
In regards to claim 3, Chen (Fig. 12 and associated text) as modified KIM (Figs. 1, 5B and associated text) discloses wherein the first semiconductor die (items 300 or 400, Chen) and the second semiconductor die (items 300 or 400, Chen) are mounted on an upper surface of the memory bridge die (item 150, Chen, items 2, 30, KIM) and on an upper surface of the package substrate (items RDL1 plus E1 plus RDL2, Chen).
In regards to claim 4, Chen (Fig. 12 and associated text) as modified KIM (Figs. 1, 5B and associated text) discloses a ball grid array (BGA) (item 112, paragraph 2) on a lower surface of the package substrate (items RDL1 plus E1 plus RDL2, Chen) opposite the upper surface of the package substrate, (items RDL1 plus E1 plus RDL2, Chen) wherein the memory bridge die (item 150, Chen, items 2, 30, KIM) comprises a first through silicon via (TSV) (paragraph 65, Chen, items 60c-60f), and the package substrate (items RDL1 plus E1 plus RDL2, Chen) comprises a fourth TSV (vias shown in RDL1) connecting the first TSV (paragraph 65, Chen, items 60c-60f) to the BGA (item 112, paragraph 2).
In regards to claim 5, Chen (Fig. 12 and associated text) as modified KIM (Figs. 1, 5B and associated text) discloses wherein the memory bridge die (item 150, Chen, items 2, 30) extends longitudinally in a first direction, the first semiconductor die (items 300 or 400, Chen) and the second semiconductor die (items 300 or 400, Chen) are connected to opposite sides of the memory bridge die (item 150, Chen, items 2, 30) in a second direction perpendicular to the first direction.
In regards to claim 6, Chen (Fig. 12 and associated text) as modified KIM (Figs. 1, 5B and associated text) discloses wherein the memory bridge die (item 150, Chen, items 2, 30) comprises a first memory circuit (not shown but present) section extending longitudinally in the first direction and connected to the first semiconductor die (items 300 or 400, Chen), and a second memory circuit (not shown but present) section extending longitudinally in the first direction and connected to the second semiconductor die (items 300 or 400, Chen).
In regards to claim 7, Chen (Fig. 12 and associated text) as modified KIM (Figs. 1, 5B and associated text) discloses wherein the first memory circuit section (not shown but present, KIM) and the second memory circuit section (not shown but present, KIM) comprise at least one of a memory controller, a memory interface and a physical layer (PHY) circuit (paragraph 51, KIM).
In regards to claim 8, Chen (Fig. 12 and associated text) as modified KIM (Figs. 1, 5B and associated text) discloses wherein the memory bridge die (item 150, Chen, items 2, 30) further comprises a memory array section (not shown but present, KIM) between the first memory circuit section (not shown but present, KIM) and the second memory circuit section (not shown but present, KIM), and extending longitudinally in the first direction.
In regards to claim 9, Chen (Fig. 12 and associated text) as modified KIM (Figs. 1, 5B and associated text) discloses wherein the memory bridge die (item 150, Chen, items 2, 30) further comprises a data line (not shown but present, KIM) connecting the first memory circuit section (not shown but present, KIM) to the second memory circuit section (not shown but present, KIM), and the memory array section (not shown but present, KIM) comprises a plurality of memory arrays (not shown but present, KIM) connected to the data line (not shown but present, KIM, paragraph 51).
In regards to claim 10, Chen (Fig. 12 and associated text) as modified KIM (Figs. 1, 5B and associated text) discloses wherein the plurality of dies (items 100, 200, 300, 400, 500, 600) further comprises: a third semiconductor die (items 100 or 200) embedded in the package substrate (items RDL1 plus E1 plus RDL2, Chen) on a first side of the memory bridge die (item 150, Chen, items 2, 30), wherein the first semiconductor die (items 300 or 400, Chen) is mounted on the third semiconductor die (items 100 or 200); and a fourth semiconductor die (items 100 or 200) embedded in the package substrate (items RDL1 plus E1 plus RDL2, Chen) on a second side of the memory bridge die (item 150, Chen, items 2, 30) opposite the first side of the memory bridge die (item 150, Chen, items 2, 30) in the second direction, wherein the second semiconductor die (items 300 or 400, Chen) is mounted on the fourth semiconductor die (items 100 or 200).
In regards to claims 21, Chen (Figs. 4-6, 12, 14 and associated text) discloses a package structure (item 100), comprising: a package substrate (items RDL1 plus E1 plus RDL2 or RDL1 plus E1 plus 106) comprising package substrate upper dielectric layer (items E1, E1 plus RDL2 or E1 plus 106) including an opening (where item 150 resides) therein; a bridge die (item 150) located in the opening and comprising bottom bond pads (items 501 or pads not shown, Figs. 12, 14, Chen also discloses broadly that die can have bottom pads 100e, Figs. 406) contacting conducting structures (conductive structure of RDL1) in the package substrate (items RDL1 plus E1 plus RDL2 or RDL1 plus E1 plus 106); a first input/output structure (outermost connector on the left or right shown but not labeled) located on an opposite side of the bottom bond pads (items 501 or pads not shown, Figs. 12, 14, Chen also discloses broadly that die can have bottom pads 100e, Figs. 4-6), and a second input/output structure (outermost connector on the left or right shown but not labeled) laterally spaced from the first input/output structure (outermost connector on the left or right shown but not labeled); a first semiconductor die (items 300 or 400) of bonded to the first input/output structure (outermost connector on the left or right shown but not labeled) of the bridge die (item 150); and a second semiconductor die (items 300 or 400) bonded to the second input/output structure (outermost connector on the left or right shown but not labeled) of the bridge die (item 150);, wherein the first semiconductor die (items 300 or 400) is connected to the second semiconductor die (items 300 or 400) through the bridge die (item 150), wherein the substrate (items RDL1 plus E1 plus RDL2 or RDL1 plus E1 plus 106) comprises a package substrate upper surface layer (item RDL2 or 108) contacting a top surface of the package substrate upper dielectric layer (item E1), but does not specifically disclose a memory die/memory bridge die.
KIM (Figs. 1, 5B and associated text) discloses a universal memory bridge (items 2, 30).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of KIM for the purpose of and electrical connections/signals, memory control, performing or controlling error checking and correction, refresh and test operations (paragraph 51).
Chen as modified by KIM does not specifically disclose wherein the substrate comprises a package substrate upper surface layer contacting a top surface of the package substrate upper dielectric layer and contacting sidewalls of the first input/output structure and sidewalls of the second input/output structure.
Chen’933 (Fig. 14B and associated text) discloses a package structure (item 250), comprising: a substrate (items 200) comprising a package substrate upper dielectric layer (item 122, paragraph 35) including an opening (where item 50 resides) therein…wherein the substrate (item 200) comprises a package substrate upper surface layer (item 106) contacting a top surface of the package substrate upper dielectric layer (item 122) and contacting sidewalls of the first input/output structure (item 14) and sidewalls of the second input/output structure (item 14).
Therefore it would have been obvious to one of ordinary skill in the art to incorporate the teachings of Chen’933 for the purpose of protection.
In regards to claims 25, Chen (Fig. 12 and associated text) discloses a third semiconductor die (items 100 or 200) embedded in the package substrate (items RDL1 plus E1 plus RDL2, Chen) and bonded to the first semiconductor die (items 300 or 400, Chen) through an additional array of microbumps (shown but not labeled); and a fourth semiconductor die (items 100 or 200, Chen) embedded within the packaging substrate and bonded to the second semiconductor die (items 300 or 400, Chen) through a yet additional array of microbumps ((item 100d).
In regards to claims 26, Chen (Figs. 4-6, 12, 14 and associated text) as modified by KIM (Figs. 1, 5B and associated text) discloses a first underfill material portion (item UF to the left or right ) laterally surrounding the first semiconductor die (items 300 or 400) and contacting a first segment of a top surface of the packaging substrate (items RDL1 plus E1 plus RDL2 or RDL1 plus E1 plus 106); a second underfill material portion (item UF to the left or right) laterally surrounding the second semiconductor die (items 300 or 400) and contacting a second segment of the top surface of the packaging substrate (items RDL1 plus E1 plus RDL2 or RDL1 plus E1 plus 106); and a molding material layer (item E2) laterally surrounding the first underfill material portion (item UF to the left or right) and the second underfill material portion (item UF to the left or right) and contacting a third segment of the top surface of the packaging substrate (items RDL1 plus E1 plus RDL2 or RDL1 plus E1 plus 106).
It would have been obvious to one having ordinary skill in the art at the time of the invention to a first and second underfill portion and a mold material surrounding the first and second underfill, since it has been held that constructing a formerly integral structure in various elements involves only routine skill in the art (Nerwin v. Erlichman, 168 USPQ 177, 179).
In regards to claims 27, Chen (Figs. 4-6, 12, 14 and associated text) discloses a package structure (item 100), comprising: a package substrate (items RDL1 plus E1 plus RDL2 or RDL1 plus E1 plus 106) comprising package substrate upper dielectric layer (items E1, E1 plus RDL2 or E1 plus 106) including an opening (where item 150 resides) therein; a bridge die (item 150) located in the opening and comprising a first input/output structure (outermost connector on the left or right shown but not labeled) and a second input/output structure (outermost connector on the left or right shown but not labeled); a first semiconductor die (items 300 or 400) comprising first microbumps (item 300e or 400e) that are (indirectly) bonded to the first input/output structure (outermost connector on the left or right shown but not labeled) of the bridge die (item 150) through first (microbumps )solder balls (item 300e or 400e) and a second semiconductor die (items 300 or 400) bonded to the second input/output structure (outermost connector on the left or right shown but not labeled) of the bridge die (item 150) through second (microbumps) solder balls (item 300e or 400e), wherein the first semiconductor die (items 300 or 400) is connected to the second semiconductor die (items 300 or 400) through the bridge die (item 150), wherein the substrate (items RDL1 plus E1 plus RDL2 or RDL1 plus E1 plus 106) comprises a package substrate upper surface layer (item RDL2 or 108) contacting a top surface of the package substrate upper dielectric layer (item E1), but does not specifically disclose a memory die/memory bridge die.
KIM (Figs. 1, 5B and associated text) discloses a universal memory bridge (items 2, 30).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of KIM for the purpose of and electrical connections/signals, memory control, performing or controlling error checking and correction, refresh and test operations (paragraph 51).
Chen as modified by KIM does not specifically disclose wherein the substrate comprises a package substrate upper surface layer contacting a top surface of the package substrate upper dielectric layer and contacting sidewalls of the first input/output structure and sidewalls of the second input/output structure.
Chen’933 (Fig. 14B and associated text) discloses a package structure (item 250), comprising: a substrate (items 200) comprising a package substrate upper dielectric layer (item 122, paragraph 35) including an opening (where item 50 resides) therein…wherein the substrate (item 200) comprises a package substrate upper surface layer (item 106) contacting a top surface of the package substrate upper dielectric layer (item 122) and contacting sidewalls of the first input/output structure (item 14) and sidewalls of the second input/output structure (item 14).
Therefore it would have been obvious to one of ordinary skill in the art to incorporate the teachings of Chen’933 for the purpose of protection.
In regards to claims 29, Chen (Figs. 4-6, 12, 14 and associated text) as modified by KIM (Figs. 1, 5B and associated text) discloses a first underfill material portion (item UF to the left or right ) laterally first (microbumps )solder balls (item 300e or 400e) and contacting a first segment of a top surface of the packaging substrate (items RDL1 plus E1 plus RDL2 or RDL1 plus E1 plus 106); a second underfill material portion (item UF to the left or right) laterally surrounding the second (microbumps )solder balls (item 300e or 400e) and contacting a second segment of the top surface of the packaging substrate (items RDL1 plus E1 plus RDL2 or RDL1 plus E1 plus 106).
It would have been obvious to one having ordinary skill in the art at the time of the invention to a first and second underfill portion and a mold material surrounding the first and second underfill, since it has been held that constructing a formerly integral structure in various elements involves only routine skill in the art (Nerwin v. Erlichman, 168 USPQ 177, 179).
In regards to claims 32, Chen (Figs. 4-6, 12, 14 and associated text) as modified by KIM (Figs. 1, 5B and associated text) and Chen’933 (Fig. 14B and associated text) discloses wherein the plurality of dies (items 100, 200, 300, 400, 500, 600) further comprises: a third semiconductor die (items 100 or 200) embedded in the package substrate upper dielectric layer (items E1, E1 plus RDL2 or E1 plus 106, Che, item 122, Chen’933) on a first side of the memory bridge die (item 150, Chen, item 2, 30, Kim) and connected to the first semiconductor die (items 300 or 400); and a fourth semiconductor die (items 100 or 200) embedded in the package substrate upper dielectric layer on a second side of the memory bridge die (item 150, Chen, item 2, 30, Kim) and connected to the second semiconductor die (items 300 or 400), wherein the package substrate upper surface layer (item 106, Chen’933) contacts a top surface of the third semiconductor die (items 100 or 200) and contacts a top surface of the fourth semiconductor die (items 100 or 200).
In regards to claims 33, Chen (Figs. 4-6, 12, 14 and associated text) as modified by KIM (Figs. 1, 5B and associated text) and Chen’933 discloses a first underfill material portion (item UF to the left or right ) laterally surrounding the first semiconductor die (items 300 or 400) and contacting a first segment of a top surface of the packaging substrate (items RDL1 plus E1 plus RDL2 or RDL1 plus E1 plus 106); a second underfill material portion (item UF to the left or right) laterally surrounding the second semiconductor die (items 300 or 400) and contacting a second segment of the top surface of the packaging substrate (items RDL1 plus E1 plus RDL2 or RDL1 plus E1 plus 106); and a molding material layer (item E2) laterally surrounding the first underfill material portion (item UF to the left or right) and the second underfill material portion (item UF to the left or right) and contacting a top surface of the package substrate upper surface layer (item 106, Chen’933), but does not specifically disclose a first package underfill layer located between the package substrate upper surface layer and the first semiconductor die; a second package underfill layer located between the package substrate upper surface layer and the second semiconductor die.
It would have been obvious to one having ordinary skill in the art at the time of the invention to include a first underfill layer and second underfill layer, since it has been held that constructing a formerly integral structure in various elements involves only routine skill in the art (Nerwin v. Erlichman, 168 USPQ 177, 179).
Claim(s) 22 and 30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (Chen) (US 2019/0131273 A1) in view of KIM (US 2015/0113195 A1) in view of Chen et al. (Chen’933) (US 2021/0125933 A1) as applied to claims 1-10, 21, 26, 27 and 29 above, and further in view of Elsherbini et al. (Elsherbini) (US 2020/0219815 A1 now US 11,217,535 B2).
In regards to claims 22, Chen as modified KIM and Chen’933 does not specifically disclose wherein the bottom bonding pads are in contact with top surfaces of through vias within a core of the packaging substrate.
In regards to claims 22, Elsherbini (Fig. 1 and associated text) discloses wherein the bottom bonding pads (items 122, 150 or 122 plus 150) are in contact with top surfaces of through vias (paragraph 34) within a core of the packaging substrate (item 102).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Elsherbini for the purpose of an electrical connection.
In regards to claims 30, Chen as modified by Kim and Chen’933 discloses all the limitations except a package lid.
In regards to claims 30, Elsherbini (Figs. 1, 21 and associated text) as modified by KIM (Figs. 1, 5B and associated text) discloses further comprising a package lid (item 131) attached to a top surface of the packaging substrate (item 102) via an adhesive and attached to top surfaces of the first semiconductor die (items 114-2 or 114-3) and the second semiconductor die (items 114-2 or 114-3) via a thermal interface material layer (item 129).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Elsherbini for the purpose of protection.
Claim(s) 31 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (Chen) (US 2019/0131273 A1) in view of KIM (US 2015/0113195 A1) in view of Chen et al. (Chen’933) (US 2021/0125933 A1) as applied to claims 1-10, 21, 26, 27 and 29 above, and further in view of We et al. (We) (US uS 9,443,824 B1).
In regards to claim 31, Chen as modified by Kim and Chen’933 discloses all of the limitations except the substrate comprises a core composed of epoxy resin or a woven glass laminate; the substrate further comprises through vias vertically extending through the core.
We (Fig. 3 and associated text) discloses substrate (item 310) comprises a core (item core) composed of epoxy resin (epoxy-based laminate, col. 6, lines 44-52) or a woven glass laminate; the substrate further comprises through vias (item 312) vertically extending through the core (item core).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of We for the purpose of the desired material and an electrical connection, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use (In re Leshin, 125 USPQ 416).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TELLY D GREEN whose telephone number is (571)270-3204. The examiner can normally be reached M-F 8am-5pm.
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TELLY D. GREEN
Examiner
Art Unit 2898
/TELLY D GREEN/Primary Examiner, Art Unit 2898 February 11, 2026