The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA
DETAILED ACTION
Election/Restrictions
Applicant's election with traverse of the embodiment of figure 9 in the reply filed on 11/19/2025 is acknowledged. The traversal is on the ground(s) that “Figures 5 and 6 (Species 1) illustrate elements in the thin film transistor layer (TF TL) of the display panel according to the present disclosure. Figure 9 further illustrates some elements of the light-emitting element layer (EML), in particular, the third metal layer and the bank that are disposed on the TFTL elements shown in Figures 5 and 6. See, é.g., present application, para. [0164] (as published) (“FIG. 9 is a schematic view in which the third metal layer MTL3 and the bank are added to FIGS. 5 and 6.”). Similarly, Figure 13 illustrates, in addition to the EML elements shown in Figure 9, the light-emitting elements, and the contact electrodes of the fourth metal layer of the light-emitting element layer (EML)”.
This is not found persuasive because the fact that the three species comprise some common elements does not mean that said three species are not separate and distinct inventions.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-9, 11-13 and 18-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The claimed limitation of “the plurality of light emitting elements aligned between the alignment line and the first electrode and aligned between the alignment line and the second electrode”, as recited in claim 1, is unclear as to how the plurality of light emitting elements are aligned between the alignment line and the first electrode and aligned between the alignment line and the second electrode, since the plurality of light emitting elements are not located in the space separating (i.e. “between”) the alignment line and the first electrode and between the alignment line and the second electrode.
The claimed limitation of “a plurality of light emitting elements aligned between the alignment line and the first electrode”, as recited in claim 11, is unclear as to how a plurality of light emitting elements are aligned between the alignment line and the first electrode, since the plurality of light emitting elements are not located in the space separating (i.e. “between”) the alignment line and the first electrode.
The claimed limitation of “the plurality of light emitting elements aligned between the alignment line and the first electrode and aligned between the alignment line and the second electrode”, as recited in claim 18, is unclear as to how the plurality of light emitting elements can be aligned between the alignment line and the first electrode and between the alignment line and the second electrode, since the plurality of light emitting elements are not located in the space separating (i.e. “between”) the alignment line and the first electrode and between the alignment line and the second electrode.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-17, as best understood, are rejected under 35 U.S.C. 103 as being unpatentable over Ikeda et al. (2021/0210513) in view of Son et al. (2021/0091163).
Regarding claims 1 and 10, Ikeda et al. teach in figure 5 and related text a display device comprising:
a pixel circuit of a first pixel formed of:
a first metal layer ML1 disposed on a substrate 21,
an active layer 71, 75 disposed on the first metal layer, and
a second metal layer ML2 disposed on the active layer;
a first electrode 24 formed of a third metal layer ML3 disposed on the second metal layer, the first electrode overlapping the pixel circuit of the first pixel;
a pixel circuit of a second pixel (see figures 1 and 4) spaced apart from the pixel circuit of the first pixel in a first direction, the pixel circuit of the second pixel formed of:
the first metal layer,
the active layer, and
the second metal layer;
a second electrode L4a formed of the third metal layer and overlapping the pixel circuit of the second pixel;
an alignment line L9 formed of the third metal layer and extending in the first direction; and
a plurality of light emitting elements 3 disposed on the third metal layer, the plurality of light emitting elements 3 aligned between (as defined by applicants) the alignment line L9 and the first electrode 24 and aligned between the alignment line L9 and the second electrode L4a.
Ikeda et al. do not explicitly state that the pixel circuit of the second pixel formed of the first metal layer, the active layer, and the second metal layer.
Son et al. teach in figure 16 and related text that the pixel circuit of the second pixel formed of the first metal layer, the active layer, and the second metal layer.
Ikeda et al. and Son et al. are analogous art because they are directed to display devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Ikeda because they are from the same field of endeavor.It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the pixel circuit of the second pixel formed of the first metal layer, the active layer, and the second metal layer, as taught by Son et al., in Ikeda et al.’s device, in order to simplify the processing steps of making the device.
Regarding claim 2, Ikeda et al. teach in figure 5 and related text that the pixel circuit of the first pixel inherently comprises: a first capacitor electrode formed of the active layer 75, and a second capacitor electrode formed of the first metal layer 78, and the first electrode overlaps the first capacitor electrode of the first pixel and is electrically connected to the second capacitor electrode of the first pixel.
Regarding claims 3, 13 and 15, Ikeda et al. teach in figure 5 and related text that a low potential line L4a formed of the second metal layer and extending in a second direction intersecting the first direction; a first contact electrode 26 formed of a fourth metal layer disposed on the third metal layer ML3, the first contact electrode 26 connected between the first electrode 24 and the plurality of light emitting elements 3; and a second contact electrode (another 26) formed of the fourth metal layer, the second contact electrode connected between the plurality of light emitting elements 3 and the low potential line L4a.
Regarding claim 4, Ikeda et al. teach in figure 5 and related text a pixel circuit of a third pixel (see figures 1 and 4) disposed between the pixel circuit of the first pixel and the pixel circuit of the second pixel, the pixel circuit of the third pixel formed of: the first metal layer, the active layer, and the second metal layer; and a third electrode another portion of element 24) formed of the third metal layer ML3 and overlapping the pixel circuit of the third pixel.
Regarding claim 5, Ikeda et al. teach in figure 5 and related text a fourth electrode L9 formed of the third metal layer ML3 and spaced apart from the third electrode, the fourth electrode connected to the pixel circuit of the third pixel, wherein the alignment line is disposed between the third electrode and the fourth electrode.
Regarding claims 6, 16 and 17, Ikeda et al. teach in figure 5 and related text that the pixel circuit of the second pixel comprises: a first capacitor electrode (see numerals in claim 2) formed of the active layer, and a second capacitor electrode formed of the first metal layer, and the second electrode overlaps the first capacitor electrode of the second pixel and is electrically connected to the second capacitor electrode of the second pixel.
Regarding claims 7 and 10, Ikeda et al. teach in figure 5 and related text a bank 27 disposed on the first electrode 24 and the second electrode 26, the bank comprising an open portion disposed between the first electrode and the second electrode.
Regarding claims 8 and 12, Ikeda et al. teach in figure 5 and related text that a light emitting opening 3 extending in the first direction, and the plurality of light emitting elements 3 are disposed in the light emitting opening.
Regarding claim 9, Ikeda et al. teach in figure 3 and related text a gate line L5, L8 formed of the second metal layer and extending in a second direction intersecting the first direction, the gate line that supplies a gate signal RG, IG to the pixel circuit of the first pixel and the pixel circuit of the second pixel, wherein the gate line is disposed between the pixel circuit of the first pixel and the pixel circuit of the second pixel (see figure 4).
Ikeda et al. do not teach forming the gate line of the second metal layer.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the gate line of the second metal layer in prior art’s device, in order to optimize the layout of the device.
Regarding claims 11 and 14, as articulated in claim 1, Ikeda et al. teach in figure 3 and related text an alignment line formed of the third metal layer and spaced apart from the first electrode and the second electrode in a second direction intersecting the first direction; and a plurality of light emitting elements aligned between the alignment line and the first/second electrode.
Claims 18-20, as best understood, are rejected under 35 U.S.C. 103 as being unpatentable over Son et al. (2021/0091163) in view of Ikeda et al. (2021/0210513).
Regarding claim 18, Son et al. teach in figure 16 and related text a display device comprising:
a first voltage line 1110 formed of a first metal layer disposed on a substrate 1010;
a first transistor comprising:
a drain electrode formed of an active layer 1210 disposed on the first metal layer, the drain electrode electrically connected to the first voltage line,
a source electrode formed of the active layer 1210, and a
gate electrode 1325 formed of a second metal layer disposed on the active layer;
a first capacitor electrode formed of the active layer 1210 and electrically connected to the gate electrode of the first transistor;
a second capacitor electrode 1125 formed of the first metal layer and overlapping the first capacitor electrode;
a first electrode CAP formed of a third metal layer disposed on the second metal layer, the first electrode overlapping the first capacitor electrode 1210 and electrically connected to the second capacitor electrode;
an alignment line (another CAP element) formed of the third metal layer and extending in a first direction.
Son et al. do not explicitly state that a plurality of light emitting elements aligned between the alignment line and the first electrode disposed on the third metal layer.
Son et al. teach in figure 2 and related text a plurality of light emitting elements EML aligned between (as defined by applicants) the alignment line and the first electrode disposed on the third metal layer (since the structure of figure is located under pixel electrode PXE).
Ikeda et al. teach in figures 1, 4, 5 and related text a plurality of light emitting elements 3 aligned between (as defined by applicants) the alignment line L9 and the first electrode 24 disposed on the third metal layer.
Ikeda et al. and Son et al. are analogous art because they are directed to display devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Ikeda because they are from the same field of endeavor.It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form a plurality of light emitting elements aligned between the alignment line and the first electrode disposed on the third metal layer, as taught by Ikeda et al., in Son et al.’s device, in order to be operate the device in its intended use
Regarding claim 19, Son et al. teach in figure 16 and related text a data line 1130 formed of the first metal layer and extending in the first direction; and a second transistor STR1 electrically connecting the data line and the first capacitor electrode.
Regarding claim 20, Son et al. teach in figure 16 and related text an initialization voltage line 1110 formed of the first metal layer and extending in the first direction; and a third transistor DTR electrically connecting the initialization voltage line and the second capacitor electrode.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ORI NADAV whose telephone number is 571-272-1660. The examiner can normally be reached between the hours of 7 AM to 4 PM (Eastern Standard Time) Monday through Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached on 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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O.N. /ORI NADAV/
1/27/2026 PRIMARY EXAMINER
TECHNOLOGY CENTER 2800