The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA
DETAILED ACTION
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-17 are rejected under 35 U.S.C. 103 as being unpatentable over Ikeda et al. (2021/0210513) in view of Son et al. (2021/0091163).
Regarding claims 1 and 10, Ikeda et al. teach in figure 5 and related text a display device comprising:
a pixel circuit of a first pixel formed of:
a first metal layer ML1 disposed on a substrate 21,
an active layer 71, 75 disposed on the first metal layer, and
a second metal layer ML2 disposed on the active layer;
a first electrode 24 formed of a third metal layer ML3 disposed on the second metal layer, the first electrode overlapping the pixel circuit of the first pixel;
a pixel circuit of a second pixel (see figures 1 and 4) spaced apart from the pixel circuit of the first pixel in a first direction, the pixel circuit of the second pixel formed of:
the first metal layer,
the active layer, and
the second metal layer;
a second electrode L4a formed of the third metal layer and overlapping the pixel circuit of the second pixel;
an alignment line L9 formed of the third metal layer and extending in the first direction; and
a plurality of light emitting elements 3 disposed on the third metal layer, the plurality of light emitting elements 3 aligned above a space between the alignment line L9 and the first electrode 24 and aligned between the alignment line L9 and the second electrode L4a (see figures 1 and 4).
Ikeda et al. do not explicitly state that the pixel circuit of the second pixel formed of the first metal layer, the active layer, and the second metal layer.
Son et al. teach in figure 16 and related text that the pixel circuit of the second pixel formed of the first metal layer, the active layer, and the second metal layer.
Ikeda et al. and Son et al. are analogous art because they are directed to display devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Ikeda because they are from the same field of endeavor.It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the pixel circuit of the second pixel formed of the first metal layer, the active layer, and the second metal layer, as taught by Son et al., in Ikeda et al.’s device, in order to simplify the processing steps of making the device.
Regarding the claimed limitations of “a first electrode formed of a third metal layer” and
“a second electrode formed of the third metal layer” and “an alignment line formed of the third metal layer”, these are process limitations which would not carry patentable weight in this claim drawn to a structure, because distinct structure is not necessarily produced.
Obtaining various elements by forming them from various layers does not produce a structure which is different from a structure which comprises said various element obtained of formed from different layers.
Note that a “product by process” claim is directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wertheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); and In re Marosi et al., 218 USPQ 289, all of which make it clear that it is the patentability of the final product per se which must be determined in a “product by process” claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in “product by process” claims or not. Note that the applicant has the burden of proof in such cases, as the above case law makes clear.
Regarding claim 2, Ikeda et al. teach in figure 5 and related text that the pixel circuit of the first pixel inherently comprises: a first capacitor electrode formed of the active layer 75, and a second capacitor electrode formed of the first metal layer 78, and the first electrode overlaps the first capacitor electrode of the first pixel and is electrically connected to the second capacitor electrode of the first pixel.
Regarding claims 3, 13 and 15, Ikeda et al. teach in figure 5 and related text that a low potential line L4a formed of the second metal layer and extending in a second direction intersecting the first direction; a first contact electrode 26 formed of a fourth metal layer disposed on the third metal layer ML3, the first contact electrode 26 connected between the first electrode 24 and the plurality of light emitting elements 3; and a second contact electrode (another 26) formed of the fourth metal layer, the second contact electrode connected between the plurality of light emitting elements 3 and the low potential line L4a.
Regarding claim 4, Ikeda et al. teach in figure 5 and related text a pixel circuit of a third pixel (see figures 1 and 4) disposed between the pixel circuit of the first pixel and the pixel circuit of the second pixel, the pixel circuit of the third pixel formed of: the first metal layer, the active layer, and the second metal layer; and a third electrode another portion of element 24) formed of the third metal layer ML3 and overlapping the pixel circuit of the third pixel.
Regarding claim 5, Ikeda et al. teach in figure 5 and related text a fourth electrode L9 formed of the third metal layer ML3 and spaced apart from the third electrode, the fourth electrode connected to the pixel circuit of the third pixel, wherein the alignment line is disposed between the third electrode and the fourth electrode.
Regarding claims 6, 16 and 17, Ikeda et al. teach in figure 5 and related text that the pixel circuit of the second pixel comprises: a first capacitor electrode (see numerals in claim 2) formed of the active layer, and a second capacitor electrode formed of the first metal layer, and the second electrode overlaps the first capacitor electrode of the second pixel and is electrically connected to the second capacitor electrode of the second pixel.
Regarding claims 7 and 10, Ikeda et al. teach in figure 5 and related text a bank 27 disposed on the first electrode 24 and the second electrode 26, the bank comprising an open portion disposed between the first electrode and the second electrode.
Regarding claims 8 and 12, Ikeda et al. teach in figure 5 and related text that a light emitting opening 3 extending in the first direction, and the plurality of light emitting elements 3 are disposed in the light emitting opening.
Regarding claim 9, Ikeda et al. teach in figure 3 and related text a gate line L5, L8 formed of the second metal layer and extending in a second direction intersecting the first direction, the gate line that supplies a gate signal RG, IG to the pixel circuit of the first pixel and the pixel circuit of the second pixel, wherein the gate line is disposed between the pixel circuit of the first pixel and the pixel circuit of the second pixel (see figure 4).
Ikeda et al. do not teach forming the gate line of the second metal layer.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the gate line of the second metal layer in prior art’s device, in order to optimize the layout of the device.
Regarding claim 10, Ikeda et al. teach in figure 5 and related text that the bank 27 comprising an open portion (located where light emitting element 3 is formed) disposed between the first electrode and the second electrode and exposing at least a portion of each of the first electrode 24 (the left side thereof) and wherein figure 7 of Ikeda (another cross-sectional view of the structure) depicts that at least a portion of the second electrode L9 is exposed by bank 27 at the location of light emitting element 3.
Regarding claims 11 and 14, as articulated in claim 1, Ikeda et al. teach in figure 3 and related text an alignment line formed of the third metal layer and spaced apart from the first electrode and the second electrode in a second direction intersecting the first direction; and a plurality of light emitting elements aligned above a space between the alignment line and the first/second electrode.
Claims 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Son et al. (2021/0091163) in view of Ikeda et al. (2021/0210513).
Regarding claim 18, Son et al. teach in figure 16 and related text a display device comprising:
a first voltage line 1110 formed of a first metal layer disposed on a substrate 1010;
a first transistor comprising:
a drain electrode formed of an active layer 1210 disposed on the first metal layer, the drain electrode electrically connected to the first voltage line,
a source electrode formed of the active layer 1210, and a
gate electrode 1325 formed of a second metal layer disposed on the active layer;
a first capacitor electrode 1230 formed of the active layer 1230 and electrically connected to the gate electrode 1325 of the first transistor;
a second capacitor electrode 1121 formed of the first metal layer and overlapping the first capacitor electrode 1230;
a first electrode CAP formed of a third metal layer disposed on the second metal layer, the first electrode overlapping the first capacitor electrode 1230 and electrically connected to the second capacitor electrode 1121;
an alignment line (another CAP element) formed of the third metal layer and extending in a first direction.
Son et al. do not explicitly state that a plurality of light emitting elements aligned above a space between the alignment line and the first electrode disposed on the third metal layer.
Son et al. teach in figure 2 and related text a plurality of light emitting elements EML aligned above a space between the alignment line and the first electrode disposed on the third metal layer (since the structure of figure is located under pixel electrode PXE).
Ikeda et al. teach in figures 1, 4, 5 and related text a plurality of light emitting elements 3 aligned above a space between (as defined by applicants) the alignment line L9 and the first electrode 24 disposed on the third metal layer.
Ikeda et al. and Son et al. are analogous art because they are directed to display devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Ikeda because they are from the same field of endeavor.It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form a plurality of light emitting elements aligned between the alignment line and the first electrode disposed on the third metal layer, as taught by Ikeda et al., in Son et al.’s device, in order to be operate the device in its intended use
Regarding claim 19, Son et al. teach in figure 16 and related text a data line 1130 formed of the first metal layer and extending in the first direction; and a second transistor STR1 electrically connecting the data line and the first capacitor electrode.
Regarding claim 20, Son et al. teach in figure 16 and related text an initialization voltage line 1110 formed of the first metal layer and extending in the first direction; and a third transistor DTR electrically connecting the initialization voltage line and the second capacitor electrode.
Response to Arguments
1. Applicants argue that Ikeda does not disclose "a first electrode formed of a third metal layer" and "a second electrode formed of the third metal layer" as recited in claim”, because “First, as can be seen at least in Figure 5 of Ikeda (reproduced below), which is a cross-sectional view of the cited Figure 4 of Ikeda2, the alleged first electrode [24] is formed of a different metal layer than that of the alleged second electrode [L4a]. In particular, the alleged second electrode [L4a] is formed of the third metal layer ML3 on the second insulating film 93 and below the third insulating film 94 but the alleged first electrode [24] is formed of a different layer on the third insulating film 94 and below the fourth insulating film 954”.
1. It is noted that the second electrode [L4a] and at least part of the first electrode [24] are located in the third metal layer ML3.
Furthermore, as recited in the rejection, Regarding the claimed limitations of “a first electrode formed of a third metal layer” and “a second electrode formed of the third metal layer” and “an alignment line formed of the third metal layer”, these are process limitations which would not carry patentable weight in this claim drawn to a structure, because distinct structure is not necessarily produced. Obtaining various elements by forming them from various layers does not produce a structure which is different from a structure which comprises said various element obtained of formed from different layers.
2. Applicants argue that Ikeda “as can also be seen at least in Figure 5 of Ikeda, none of the alleged light emitting elements [3] are aligned between (or aligned above a space between) the alleged alignment line [L9] and the alleged second electrode [L4a]. Rather, as can be seen, the space above the area between elements L9 and L4a is devoid of any of the alleged light emitting elements [3]”.
2. Figure 5 of Ikeda clearly depicts that light emitting elements [3] are located at the space above (i.e. at higher elevation) the area between elements L9 and L4a.
3. Applicants argue regarding claim 10 that “as can be seen at least in Figure 5 of Ikeda (reproduce above), the flattening film 27 does not expose any portion the alleged first electrode [24] and the alleged second electrode [L9]. Rather, the alleged first electrode [24] is covered by both the fourth insulating film 95 and the anode electrode 23, both of which are then covered by the alleged bank [27]6. Further, the alleged second electrode [L9] is covered by both the third insulating film 94 and the fourth insulating film 95, which is then covered by the alleged bank [27]”.
3. Figure 5 of Ikeda clearly depicts that at least a portion of the first electrode 24 (the left side thereof) is exposed by bank 27 at the location of light emitting element 3. Figure 7 of Ikeda (another cross-sectional view of the structure) depicts that at least a portion of the second electrode L9 is exposed by bank 27 at the location of light emitting element 3.
4. Applicants argue regarding claim 18 that “In rejecting claim 18, the Office action does not appear to equate any element of Son with the recited first capacitor electrodes. Further, at least Figure 16 of Son does not appear to disclose any capacitor electrode formed of any active layer, let alone the active layer as recited in claim 18. For example, in the capacitor region CPR of Son, the capacitor upper electrode 1331 does not include any part of the alleged active layer [1210]; rather, the capacitor upper electrode 1331 is formed on the gate insulating film 1620 and the interlayer insulating film 16109. The capacitor lower electrode 1121 and the capacitor lower electrode second extension 1125 are formed on the substrate 1010 and is described as being part of a "conductive pattern,"10 which is different from how Son describes the alleged active layer, that is, the first semiconductor pattern 1210.11. Further, the alleged second capacitor electrode [1125] does not appear to overlap any first capacitor electrode. The only apparent capacitor electrode above the alleged second capacitor electrode [1125] is the capacitor upper electrode 1331, but as can be seen below in Figure 16, the alleged second capacitor electrode [1125] is offset from and does not appear to overlap the capacitor upper electrode 1331”.
4. In the current Office action, the first capacitor electrode and the rest of Son’s capacitor elements are identified.
5. Applicants argue that “Moreover, Son does not appear to disclose "the first electrode overlapping the first capacitor electrode and electrically connected to the second capacitor electrode" as recited in claim 18”.
6. It is noted that all the elements in one device are electrically connected to one another.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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O.N. /ORI NADAV/
5/16/2026 PRIMARY EXAMINER
TECHNOLOGY CENTER 2800
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