DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the following communications: the Amendment filed 1/16/2026
Claims 1-40 are pending.
Election/Restrictions
Applicant's election with traverse of Group I and Species I in the reply filed on 1/16/2026 is acknowledged. The traversal is on the ground(s) that “the present application discloses a unified configuration of an electronic package in which conductors are grounded at a substrate, formed within an encapsulation layer, and connected to a conductive layer and a heat dissipation structure. This specific arrangement collectively enhances EMI shielding (anti-EMI effects) on the top and peripheral surfaces of the electronic package. Thus, any variations in singulation types or the specific geometries of the encapsulation layer and substrate formed among Species I, II, and III do not constitute an undue search burden.” (Remarks 9) This is not found persuasive, because Species I, II and III contain features that are mutually exclusive from one another and thereby there would be a search/examination burden to search for all the features of Species I-III given that they would require a different field of search such as searching different classes/subclasses or electronic resources, or employing different search strategies or search queries.
The requirement is still deemed proper and is therefore made FINAL.
Claims 3 and 11-40 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Group/Species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 1/16/2026.
A. Prior-art rejections based at least in part by Yada
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4-6 and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yada et al. (US 2021/0193587 A1, hereinafter “Yada”).
Regarding independent claim 1, Figures 9-9B of Yada disclose an electronic package, comprising:
a substrate structure 11 (“substrate”- ¶0069) having electrical contact pads 1111a, 1112a (“pads”- ¶0030) and ground pads 1114a-1114c (“grounding… terminals”- ¶0069);
an electronic component 12 (“electronic component”- ¶0069) disposed on the substrate structure 11 and electrically connected to the electrical contact pads 1111a, 1112a (¶0030);
conductors 455B, 455C (“interconnects”- ¶0069) disposed on the substrate structure 11 and spaced apart from the electronic component 12, wherein the conductors 455B, 455C are of wires (¶0071) and electrically connected to the ground pads 1114a-1114c (¶0069);
an encapsulation layer 14 (“package body”- ¶0069) formed on the substrate structure 11 and covering the electronic component 12 and the conductors 455B, 455C, wherein the encapsulation layer 14 is defined with a first surface, a second surface opposing the first surface, and side surfaces adjacent to the first surface and the second surface, the encapsulation layer 14 is bonded onto the substrate structure 11 by the first surface of the encapsulation layer 14, and the conductors 455B, 455C are exposed from the side surfaces of the encapsulation layer 14; and
a conductive layer 45 (“shield”- ¶¶0047-0048, 0069) formed on the encapsulation layer 14 and in contact with the conductors 455B, 455C.
Regarding claim 2, Figures 9-9B of Yada disclose wherein the side surfaces of the encapsulation layer 14 are step-shaped.
Regarding claim 4, Figures 9-9B of Yada disclose wherein the side surfaces of the encapsulation layer 14 are flush with side surfaces of the substrate structure 11.
Regarding claim 5, Figures 9-9B of Yada disclose wherein the conductive layer 45 is flush with sides surfaces of the substrate structure 11.
Regarding claim 6, Figures 9-9B of Yada disclose wherein the conductive layer 45 is formed on a portion of each of the side surfaces of the encapsulation layer 14 or the entire side surfaces of the encapsulation layer 14.
Regarding claim 10, Figures 9-9B of Yada disclose wherein the electronic component 12 is an active element, a passive element, or a combination of the active element and the passive element (¶0040).
B. Prior-art rejections based at least in part by Lin
Claim Rejections - 35 USC § 102
Claims 1 and 7-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin (US 2019/0067208 A1).
Regarding independent claim 1, Figures 3-4 of Lin disclose an electronic package, comprising:
a substrate structure CB’ (“circuit board”- ¶0020) having electrical contact pads BP (“pads”- ¶0020) and ground pads GBP (“ground pads”- ¶0020);
an electronic component CH (“electronic device”- ¶0017) disposed on the substrate structure CB’ and electrically connected to the electrical contact pads BP (¶0017);
conductors GS (“conductive structures”- ¶0020) disposed on the substrate structure CB’ and spaced apart from the electronic component CH, wherein the conductors GS are of wires (¶0020) and electrically connected to the ground pads GBP (¶0020);
an encapsulation layer EN (“encapsulation”- ¶0020) formed on the substrate structure CB’ and covering the electronic component CH and the conductors GS, wherein the encapsulation layer EN is defined with a first surface, a second surface opposing the first surface, and side surfaces adjacent to the first surface and the second surface, the encapsulation layer EN is bonded onto the substrate structure CB’ by the first surface of the encapsulation layer EN, and the conductors GS are exposed from the side surfaces of the encapsulation layer EN; and
a conductive layer EL (“EMI protection layer”- ¶0020) formed on the encapsulation layer EN and in contact with the conductors GS.
Regarding claim 7, Figures 3-4 of Lin disclose wherein the conductive layer EL is formed on the entire side surfaces of the encapsulation layer EN and extends onto side surfaces of the substrate structure CB’.
Regarding claim 8, Figures 3-4 of Lin disclose wherein the conductive layer EL is formed on a portion of each of the side surfaces of the substrate structure CB’ or the entire side surfaces of the substrate structure CB’.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Fang (US 2020/0185286 A1).
Regarding claim 9, Lin does not expressly disclose the electronic package further comprising a heat dissipation structure formed on the second surface of the encapsulation layer, wherein the heat dissipation structure is covered by the conductive layer.
Figure 1D of Fang discloses an electronic package comprising an electronic component 20 (“electronic component”- ¶0019) on a substrate structure 10 (“substrate”- ¶0019), an encapsulation layer 50 (“encapsulant”- ¶0019) covering the electronic component 20, wherein the encapsulation layer 50 comprises a second surface facing away from the substrate structure 10, a conductive layer 40/70 (collectively 40 and 70, which is comprised of conductive materials- ¶¶0023, 0026) covering the second surface of the encapsulation layer 50 and a heat dissipation structure 60 (“thermal conductive material”- ¶0019) formed on the second surface of the encapsulation layer 50, wherein the heat dissipation structure 60 is covered by the conductive layer 40/70.
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lin such that electronic package further comprises a heat dissipation structure formed on the second surface of the encapsulation layer, wherein the heat dissipation structure is covered by the conductive layer as taught by Fang for the purpose of utilizing a suitable and well-known structural element and associated configuration which improves the heat dissipation of the electronic package (Fang ¶0034).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Otsubo et al. (US 2024/0203902 A1), which discloses an electronic package comprising wires which are exposed at the side surfaces of an encapsulation layer
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY C CHANG whose telephone number is (571)272-6132. The examiner can normally be reached Mon- Fri 12pm-10pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571)-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAY C CHANG/Primary Examiner, Art Unit 2817