DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of claims 1-10 in the reply filed on 9/26/25 is acknowledged. The traversal is on the ground(s) that it would not constitute a burdensome search upon the Examiner to examine the separate statutory class of invention (the method claims). This is not found persuasive because method and device claims are separate statutory classes of invention- method steps are not usually afforded patentable weight in device claims and vice versa. An exhaustive search has been conducted on the elected device claims and allowable subject matter has been identified. Applicant is entitled to one invention per application and a second statutory class of invention (method) is effectively (potentially) a second invention.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 6, 8, 10 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Cho et al (US 2020/0328187).
1. An electronic package, comprising:
a carrier structure (Fig.2A (100) and [0019]) having a first surface (top) and a second surface (bottom) opposing the first surface (top), the carrier structure (Fig.2A (100) and [0019]) including an insulating layer (Fig.2A (110) and [0022-0023]) and a circuit layer (Fig.2A (140) and [0020]) formed on the insulating layer (Fig.2A (110) and [0022-0023]);
a first electronic element (Fig.2A (310- left) and [0032-0033]) disposed on the first surface (top) of the carrier structure (Fig.2A (100) and [0019]) and electrically connected (Fig.2A (BW1- left) and [0060]) to the circuit layer (Fig.2A (140) and [0020]);
a second electronic element (Fig.2A (310- right) and [0032-0033]) disposed on the first surface (top) of the carrier structure (Fig.2A (100) and [0019]) and electrically connected (Fig.2A (BW1- right) and [0060]) to the circuit layer (Fig.2A (140) and [0020]), wherein the first electronic element (Fig.2A (310- left) and [0032-0033]) and the second electronic element (Fig.2A (310- right) and [0032-0033]) are electrically connected to each other by a wire (Fig.2A (BW2) and [0060]); and a packaging layer (Fig.2A (400) and [0061]) formed on the first surface (top) of the carrier structure (Fig.2A (100) and [0019]) and covering the wire (Fig.2A (BW2) and [0060]), the first electronic element (Fig.2A (310- left) and [0032-0033]) and the second electronic element (Fig.2A (310- right) and [0032-0033]).
2. The electronic package of claim 1, wherein the wire is a gold wire [0047].
3. The electronic package of claim 1, wherein the first electronic element (Fig.2A (310- left) and [0032-0033]) is electrically connected to the circuit layer (Fig.2A (140) and [0020]) by wire bonding (Fig.2A (BW1- left) and [0060]).
4. The electronic package of claim 1, wherein the second electronic element (Fig.2A (310- right) and [0032-0033]). is electrically connected to the circuit layer (Fig.2A (140) and [0020]) by wire bonding (Fig.2A (BW1- right) and [0060]).
6. The electronic package of claim 1, further comprising at least one conductive pillar (Fig.2A (230/220-pad connection terminal are interpreted as a pillar) and [0029]) and formed on the first surface (top) of the carrier structure (Fig.2A (100) and [0019]) and covered by the packaging layer (Fig.2A (400) and [0061]), wherein the at least one conductive pillar (Fig.2A (230/220) and [0029]) is electrically connected to the circuit layer (Fig.2A (140) and [0020]).
8. The electronic package of claim 6, further comprising a circuit structure or a conductive element (Fig.1A (430/420) and 0042-0044]) disposed on the packaging layer (Fig.1A (400)) and electrically connected (through 300) to the at least one conductive pillar (Fig.1A (230/220) and [0029]).
10. The electronic package of claim 1, further comprising at least one package module disposed on the second surface of the carrier structure (Fig.1A (130/150- connected to unshown system board) and [0021]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cho et al (US 2020/0328187) as applied to claim 1 above, and further in view of Hembree (US 2007/0296090).
Cho teaches the limitations of claim 1 as cited above, however fails to teach the limitations of claim 5 as recited below:
5. The electronic package of claim 1, wherein the wire between the first electronic element and the second electronic element is connected to a jumper pad disposed on the carrier structure.
Hembree teaches the use of jumper pads form wire bonded circuit elements (Fig.7A-7B and [0020]).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Cho’s teachings to include two wire bonds connected together through a jumper pad as taught by Hembree because doing so is a matter of design choice which would facilitate a substantially similar electrical connection. Cho teaches to electrically connect the electronic elements to the circuit layer through BW1 and to each other using BW2; one of ordinary skill in the art would understand the same connection could be facilitated using a jumper pad and connecting the wire bonds to both the first and second electronic elements.
Allowable Subject Matter
Claims 7 and 9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Prior art fails to teach nor suggest the limitations of claims 1 and 6-7, in combination, as required by claim 7 as recited below:
7. The electronic package of claim 6, wherein the first electronic element and/or the second electronic element and the at least one conductive pillar are electrically connected to each other by another wire and a jumper pad, and the jumper pad is disposed on the carrier structure and is electrically connected to the first electronic element and/or the second electronic element and the circuit layer via the another wire.
Similarly, prior art fails to teach nor suggest the limitations of claim 1 and 9 in combination as required by claim 9, and recited below:
9. The electronic package of claim 1, wherein the first electronic element and/or the second electronic element are electrically connected to the circuit layer via another wire and a jumper pad, and the jumper pad is disposed on the carrier structure, such that the first electronic element and/or the second electronic element are electrically connected to the jumper pad by wire bonding, and the another wire is electrically connected to the circuit layer and the jumper pad.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Chi et al (US 20250087635); Chen et al (US 20170141080); and Camacho et al (US 20110233753) teach similar structures.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAURA M MENZ whose telephone number is (571)272-1697. The examiner can normally be reached Monday-Friday 7:00-3:30.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier can be reached at 571-270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LAURA M MENZ/Primary Examiner, Art Unit 2813
12/13/25