DETAILED ACTION
This action is responsive to the amendment and request for continued examination filed on 05/26/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 05/26/2026 has been entered.
Priority
Acknowledgment is made of applicant's claim for priority under 35 U.S.C. 119(a)-(d) or (f), 365(a) or (b), or 386(a) based upon an application filed in TAIWAN on 02/09/2023.
Election/Restrictions
Claim(s) 21-26 and 28-31 is/are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species and invention, respectively, there being no allowable generic or linking claim.
Applicant timely traversed the restriction (election) requirement in the reply filed on 09/26/2025. Reasons indicating why applicant’s traversal arguments were not found persuasive were provided in the non-final rejection mailed on 11/05/2025.
Claim Rejections - 35 USC § 102/103
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 12-13 and 15-19 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as anticipated by US 2023/0030176 A1; Lee et al.; 02/2023; (“Lee”) or, in the alternative, under 35 U.S.C. 103 as obvious over Lee in view of US 2019/0096842 A1; Fountain et al.; 03/2019; (“Fountain”). Annotated versions of Figures 2 and 3 from Lee are provided below and referenced in the following rejection.
PNG
media_image1.png
444
609
media_image1.png
Greyscale
PNG
media_image2.png
332
331
media_image2.png
Greyscale
Regarding Claim 12. Lee discloses A semiconductor device (Figure 2, a DRAM device according to [0011] with Figure 3 being a corresponding plan view according to [0021]), comprising:
a substrate (#100, Figure 2, substrate) having a first region (#R1, Figure 2 annotated) and a second region (#R2, Figure 2 annotated) adjacent to the first region (Figure 2, #R1 and #R2 are adjacent);
a plurality of first components (#120, Figure 2, bit line structures) formed over the substrate and in the first region (Figure 2 annotated, #120s are formed over #100 in #R1);
a second component (#124 and #102, Figure 2, transistor and its adjacent isolation structure) formed over the substrate and in the second region (Figure 2 annotated, #124 and #102 are formed over #100 in #R2);
a first material layer (#244, #242a, and #254, Figure 2, upper electrode, polishing stop layer, and third insulating interlayer; examiner notes that [0027]-[0028] of the instant application indicates that the first material layer may comprise a plurality of different materials) formed over the first components (Figure 2, #244, #242a, and #254 are over #120s);
a second material layer (#262, Figure 2, fourth insulating interlayer) formed over the second component (Figure 2, #262 is over #124 and #102), wherein the second material layer and the first material layer comprise different materials ([0065], #262 is an insulating interlayer, i.e. comprises only an insulating material; [0051], #240a of #244 comprises the conductive material tungsten; i.e. the first and second material layers comprise different materials); and
a patterned dummy layer (#252a and #246a, Figure 2, filling insulation pattern and second insulating interlayer pattern) formed over the first components (Figure 2, #252a is formed over #120s), wherein the patterned dummy layer is embedded in the first material layer (Figure 2, #252a is embedded in #240a of #244 and #242a) and an upper surface of the patterned dummy layer is covered by the first material layer (Figure 2, the upper surface of both #252a and #246a is covered by #254),
wherein the patterned dummy layer (#252a and #246a) comprises first pattern portions (Figure 3 annotated, portions of #252a in region #CR) and second pattern portions (Figure 3 annotated, portions of #252a in region #ER), and the first pattern portions and the second pattern portions are respectively arranged in a central region and an edge region of the first region of the substrate (Figure 3 annotated, the first portions of #252a are in a central region #CR and the second pattern portions are in an edge region #ER), wherein a spacing between the first pattern portions is less than a spacing between the second pattern portions (Figure 3 annotated, a lateral, or left to right, spacing between portions of #252a in region #CR is less than a lateral spacing between portions of #252a in region #ER due to the presence of portions of #252a in region #CR therebetween).
In the alternative, an interpretation may be made that “spacing between the first pattern portions” and “spacing between the second pattern portions” is in reference to the spacing between two of the associated pattern portions which are closest together. Under this possible interpretation, Lee does not appear to disclose that a spacing between the first pattern portions is less than a spacing between the second pattern portions when referring to those which are closest together.
However, Fountain teaches a semiconductor device (Figures 7 and 8A-8D, [0100], conductive pad layouts on a wafer surface) comprising a first material layer (#702 and #704, Figure 7, dielectric and barrier layers) with a patterned layer (#716/#800, Figures 7 and 8, conductive pads) embedded in the first material layer wherein the patterned layer comprises first pattern portions (#800 right, Figure 8D) and second pattern portions (#800 left, Figure 8D), wherein a spacing between the first pattern portions is less than a spacing between the second pattern portions (Figure 8D, a spacing between the #800s on the right is smaller than the #800s on the left of the wafer structure).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider increasing the separation distance of patterned layers in the outer areas of the device and/or decreasing the separation distance of patterned layers in the inner area of the device of Lee based on the teachings of Fountain. Fountain teaches in [0123] that the metal density, pitch, and layout of the pads in different regions may be adjusted as necessary to achieve steady state polishing since the density of different regions will modify the polishing rate. Lee teaches in [0146]-[0148] that the patterned layer is used in part to control polishing procedures and the extent of polishing. This is therefore interpreted by the examiner as routine optimization (MPEP 2144.05.II) to achieve optimal polishing during manufacturing processes in Lee in view of Fountain.
Regarding Claim 13. Lee in view of Fountain discloses The semiconductor device as claimed in claim 12, wherein a pattern distribution density of the first pattern portions is greater than a pattern distribution density of the second pattern portions (Lee, Figure 3 annotated, the distribution density of first portions of #252a in the #CR region is greater than the density of second pattern portions #252a in the #ER region; Fountain, Figure 8D, a density of the #800s on the right is greater than the #800s on the left of the wafer structure).
Regarding Claim 15. Lee in view of Fountain discloses The semiconductor device as claimed in claim 12, wherein the patterned dummy layer (Lee,#252a and #246a) further extends to the second region (Lee, Figure 2 annotated, #246a extends into #R2), and the patterned dummy layer is disposed over the second component (Figure 2, #246a is disposed over #124 and #102).
Regarding Claim 16. Lee in view of Fountain discloses The semiconductor device as claimed in claim 15, wherein the first material layer (Lee,#244, #242a, and #254) further extends to the second region (Lee, Figure 2 annotated, #244, #242a, and #254 extend into #R2) and the first material layer is disposed over the second component (Lee, Figure 2, #244, #242a, and #254 are disposed over the combination of #124 and #102),
wherein the patterned dummy layer (Lee, #252a and #246a) further comprises:
a continuous portion (Lee, #CP of #246a, Figure 2 annotated), correspondingly disposed in the second region and embedded in the first material layer (Lee, Figure 2 annotated, #CP of #246a is embedded into the side of #244 and #242a),
wherein the second material layer is formed over the continuous portion of the patterned dummy layer and a portion of the first material layer (Lee, Figure 2 annotated, #262 is formed over #CP of #246a and a portion of #244, #242a, and #254).
Regarding Claim 17. Lee in view of Fountain discloses The semiconductor device as claimed in claim 12, wherein the patterned dummy layer comprises:
a marking portion (Lee, #MP of #246a, Figure 2 annotated) in the first region and adjacent to a boundary between the first region and the second region (Lee, Figure 2 annotated, #MP is in #R1 and adjacent to a boundary between #R1 and #R2).
Regarding Claim 18. Lee in view of Fountain discloses The semiconductor device as claimed in claim 17, wherein the marking portion extends from the first region to the second region, and continuously crosses the boundary (Lee, Figure 2 annotated, #MP extends from #R1 to #R2 and continuously crosses the boundary between #R1 and #R2).
Regarding Claim 19. Lee in view of Fountain discloses The semiconductor device as claimed in claim 12, wherein the patterned dummy layer (Lee, #252a and #246a) and the first material layer (Lee, #244, #242a, and #254) comprise different materials (Lee, [0051], #240a of #244 comprises tungsten; [0054], #252a comprises tetraethyl orthosilicate, i.e. the first material layer and the pattern dummy layer comprise different materials).
Claim(s) 12 and 20 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as anticipated by US 2023/0030176 A1; Lee et al.; 02/2023; (“Lee”) or, in the alternative, under 35 U.S.C. 103 as obvious over Lee in view of US 2019/0096842 A1; Fountain et al.; 03/2019; (“Fountain”). Annotated versions of Figures 2 and 3 from Lee are provided above and referenced in the following rejection.
Regarding Claim 12. Lee discloses A semiconductor device (Figure 2, a DRAM device according to [0011] with Figure 3 being a corresponding plan view according to [0021]), comprising:
a substrate (#100, Figure 2, substrate) having a first region (#R1, Figure 2 annotated) and a second region (#R2, Figure 2 annotated) adjacent to the first region (Figure 2, #R1 and #R2 are adjacent);
a plurality of first components (#120, Figure 2, bit line structures) formed over the substrate and in the first region (Figure 2 annotated, #120s are formed over #100 in #R1);
a second component (#124 and #102, Figure 2, transistor and its adjacent isolation structure) formed over the substrate and in the second region (Figure 2 annotated, #124 and #102 are formed over #100 in #R2);
a first material layer (#244, #242a, and #254, Figure 2, upper electrode, polishing stop layer, and third insulating interlayer; examiner notes that [0027]-[0028] of the instant application indicates that the first material layer may comprise a plurality of different materials) formed over the first components (Figure 2, #244, #242a, and #254 are over #120s);
a second material layer (#230, Figure 2, dielectric layer) formed over the second component (Figure 2, #230 is at least partially over the combination of #124 and #102), wherein the second material layer and the first material layer comprise different materials ([0043], #230 is a high-k dielectric layer, i.e. comprises only an insulating material; [0051], #240a of #244 comprises the conductive material tungsten; i.e. the first and second material layers comprise different materials); and
a patterned dummy layer (#252a and #246a, Figure 2, filling insulation pattern and second insulating interlayer pattern) formed over the first components (Figure 2, #252a is formed over #120s), wherein the patterned dummy layer is embedded in the first material layer (Figure 2, #252a is embedded in #240a of #244 and #242a) and an upper surface of the patterned dummy layer is covered by the first material layer (Figure 2, the upper surface of both #252a and #246a is covered by #254),
wherein the patterned dummy layer (#252a and #246a) comprises first pattern portions (Figure 3 annotated, portions of #252a in region #CR) and second pattern portions (Figure 3 annotated, portions of #252a in region #ER), and the first pattern portions and the second pattern portions are respectively arranged in a central region and an edge region of the first region of the substrate (Figure 3 annotated, the first portions of #252a are in a central region #CR and the second pattern portions are in an edge region #ER), wherein a spacing between the first pattern portions is less than a spacing between the second pattern portions (Figure 3 annotated, a lateral, or left to right, spacing between portions of #252a in region #CR is less than a lateral spacing between portions of #252a in region #ER due to the presence of portions of #252a in region #CR therebetween).
In the alternative, an interpretation may be made that “spacing between the first pattern portions” and “spacing between the second pattern portions” is in reference to the spacing between two of the associated pattern portions which are closest together. Under this possible interpretation, Lee does not appear to disclose that a spacing between the first pattern portions is less than a spacing between the second pattern portions when referring to those which are closest together.
However, Fountain teaches a semiconductor device (Figures 7 and 8A-8D, [0100], conductive pad layouts on a wafer surface) comprising a first material layer (#702 and #704, Figure 7, dielectric and barrier layers) with a patterned layer (#716/#800, Figures 7 and 8, conductive pads) embedded in the first material layer wherein the patterned layer comprises first pattern portions (#800 right, Figure 8D) and second pattern portions (#800 left, Figure 8D), wherein a spacing between the first pattern portions is less than a spacing between the second pattern portions (Figure 8D, a spacing between the #800s on the right is smaller than the #800s on the left of the wafer structure).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider increasing the separation distance of patterned layers in the outer areas of the device and/or decreasing the separation distance of patterned layers in the inner area of the device of Lee based on the teachings of Fountain. Fountain teaches in [0123] that the metal density, pitch, and layout of the pads in different regions may be adjusted as necessary to achieve steady state polishing since the density of different regions will modify the polishing rate. Lee teaches in [0146]-[0148] that the patterned layer is used in part to control polishing procedures and the extent of polishing. This is therefore interpreted by the examiner as routine optimization (MPEP 2144.05.II) to achieve optimal polishing during manufacturing processes in Lee in view of Fountain.
Regarding Claim 20. Lee in view of Fountain discloses The semiconductor device as claimed in claim 12, wherein the first material layer (Lee, #244, #242a, and #254) includes a conductive material (Lee, [0051], #240a of #244 includes tungsten), and
the second material layer (Lee, #230) includes an oxide layer (Lee, [0043], #230 may comprise a plurality of different oxide layers including hafnium oxide layer, a zirconium oxide layer, an aluminum oxide layer, or a lanthanum oxide layer).
Response to Arguments/Amendments
Applicant’s amendments to claim 12 and corresponding arguments, see pages 8-11 of the remarks, filed 05/26/2026, with respect to the 35 U.S.C. 102 rejection of claim 12 and its dependent claims as being anticipated by US 2023/0030176 A1; Lee et al.; 02/2023; (“Lee”) have been fully considered but are not found persuasive. Applicant argues that Lee does not disclose “a spacing between the first pattern portions is less than a spacing between the second pattern portions”. Examiner respectfully disagrees.
Applicant points out that Lee states that all of the #252a patterns are regularly disposed on the device (see [0120] of Lee such that the spacing between them is interpreted to be the same throughout rather than irregular as required by the claim.
While the applicant is correct that the openings which #252a are formed in are regularly spaced, this does not preclude the spacing of different portions the #252a patterns being different from one another. In particular this is because applicant has divided the dummy layer into arbitrary “portions” which are located in the central and edge regions of the device. In the annotated Figure 3 of Lee provided above, there is a difference in the lateral spacings between the first portions (those located in the center of the device) and the second portions (those located on the edge of the device) because of the presence of the central region in the middle of the device. In the annotated Figure 3, a lateral, or left to right, spacing between portions of #252a in region #CR is less than a lateral spacing between portions of #252a in region #ER due to the presence of portions of #252a in region #CR therebetween. Therefore, it is the examiner’s interpretation that Lee does disclose all of the limitations of amended claim 12.
In addition, examiner has provided an alternative 35 U.S.C. 103 rejection of claim 12 over US 2023/0030176 A1; Lee et al.; 02/2023; (“Lee”) in view of US 2019/0096842 A1; Fountain et al.; 03/2019; (“Fountain”) which may be more in line with applicant’s intended interpretation of the amended claim limitation. As described above, Fountain teaches a patterned layer (#716/#800, Figures 7 and 8, conductive pads) embedded in a first material layer wherein the patterned layer comprises first pattern portions (#800 right, Figure 8D) and second pattern portions (#800 left, Figure 8D), wherein a spacing between the first pattern portions is less than a spacing between the second pattern portions (Figure 8D, a spacing between the #800s on the right is smaller than the #800s on the left of the wafer structure). Fountain further provides motivation as routine optimization (MPEP 2144.05.II) to achieve optimal polishing during manufacturing processes in Lee in view of Fountain. This is the same motivation of the instant application for the differences in spacings/densities of the patterned layers (see [0036]-[0039] of the instant application). Therefore, it is the examiner’s interpretation that Lee in view of Fountain teach all of the limitations of amended claim 12 and in greater overlap with the instant application.
Applicant’s request for the rejoinder of claims 21-26 and 28-31, see page 11 of the remarks, filed 05/26/2026, has been fully considered. Currently, claim 12 stands rejected, as described above, such that there is no allowable generic or linking claim and the claims stand withdrawn from consideration. Should claim 12 be determined as allowable, claims 21-26 and 28-31 will be considered for potential rejoinder.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TYLER JAMES WIEGAND whose telephone number is (571)270-0096. The examiner can normally be reached Mon-Fri. 8AM-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHRISTINE KIM can be reached at (571) 272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TYLER J WIEGAND/Examiner, Art Unit 2812
Prosecution Insights