DETAILED ACTION
This action is responsive to the amendment filed on 01/23/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for priority under 35 U.S.C. 119(a)-(d) or (f), 365(a) or (b), or 386(a) based upon an application filed in TAIWAN on 02/09/2023.
Election/Restrictions
Claim(s) 14 and 21-31 is/are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species and invention, respectively, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 09/26/2025. Reasons indicating why applicant’s traversal arguments were not found persuasive were provided in the non-final rejection mailed on 11/05/2025.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 12-13 and 15-19 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by US 2023/0030176 A1; Lee et al.; 02/2023; (“Lee”). Annotated versions of Figures 2 and 3 from Lee are provided below and referenced in the following rejection.
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Regarding Claim 12. Lee discloses A semiconductor device (Figure 2, a DRAM device according to [0011] with Figure 3 being a corresponding plan view according to [0021]), comprising:
a substrate (#100, Figure 2, substrate) having a first region (#R1, Figure 2 annotated) and a second region (#R2, Figure 2 annotated) adjacent to the first region (Figure 2, #R1 and #R2 are adjacent);
a plurality of first components (#120, Figure 2, bit line structures) formed over the substrate and in the first region (Figure 2 annotated, #120s are formed over #100 in #R1);
a second component (#124 and #102, Figure 2, transistor and its adjacent isolation structure) formed over the substrate and in the second region (Figure 2 annotated, #124 and #102 are formed over #100 in #R2);
a first material layer (#244, #242a, and #254, Figure 2, upper electrode, polishing stop layer, and third insulating interlayer; examiner notes that [0027]-[0028] of the instant application indicates that the first material layer may comprise a plurality of different materials) formed over the first components (Figure 2, #244, #242a, and #254 are over #120s);
a second material layer (#262, Figure 2, fourth insulating interlayer) formed over the second component (Figure 2, #262 is over #124 and #102), wherein the second material layer and the first material layer comprise different materials ([0065], #262 is an insulating interlayer, i.e. comprises only an insulating material; [0051], #240a of #244 comprises the conductive material tungsten; i.e. the first and second material layers comprise different materials); and
a patterned dummy layer (#252a and #246a, Figure 2, filling insulation pattern and second insulating interlayer pattern) formed over the first components (Figure 2, #252a is formed over #120s), wherein the patterned dummy layer is embedded in the first material layer (Figure 2, #252a is embedded in #240a of #244 and #242a) and an upper surface of the patterned dummy layer is covered by the first material layer (Figure 2, the upper surface of both #252a and #246a is covered by #254).
Regarding Claim 13. Lee discloses The semiconductor device as claimed in claim 12, wherein the patterned dummy layer (#252a and #246a) comprises first pattern portions (Figure 3 annotated, portions of #252a in region #CR) and second pattern portions (Figure 3 annotated, portions of #252a in region #ER), and the first pattern portions and the second pattern portions are respectively arranged in a central region and an edge region of the first region of the substrate (Figure 3 annotated, the first portions of #252a are in a central region #CR and the second pattern portions are in an edge region #ER), wherein a pattern distribution density of the first pattern portions is greater than a pattern distribution density of the second pattern portions (Figure 3 annotated, the same number of portions of #252a are located in #CR and #ER, respectively, and #ER is larger than #CR in area, therefore the distribution density of first portions of #252a is greater than the density of second pattern portions).
Regarding Claim 15. Lee discloses The semiconductor device as claimed in claim 12, wherein the patterned dummy layer (#252a and #246a) further extends to the second region (Figure 2 annotated, #246a extends into #R2), and the patterned dummy layer is disposed over the second component (Figure 2, #246a is disposed over #124 and #102).
Regarding Claim 16. Lee discloses The semiconductor device as claimed in claim 15, wherein the first material layer (#244, #242a, and #254) further extends to the second region (Figure 2 annotated, #244, #242a, and #254 extend into #R2) and the first material layer is disposed over the second component (Figure 2, #244, #242a, and #254 are disposed over the combination of #124 and #102),
wherein the patterned dummy layer (#252a and #246a) further comprises:
a continuous portion (#CP of #246a, Figure 2 annotated), correspondingly disposed in the second region and embedded in the first material layer (Figure 2 annotated, #CP of #246a is embedded into the side of #244 and #242a),
wherein the second material layer is formed over the continuous portion of the patterned dummy layer and a portion of the first material layer (Figure 2 annotated, #262 is formed over #CP of #246a and a portion of #244, #242a, and #254).
Regarding Claim 17. Lee discloses The semiconductor device as claimed in claim 12, wherein the patterned dummy layer comprises:
a marking portion (#MP of #246a, Figure 2 annotated) in the first region and adjacent to a boundary between the first region and the second region (Figure 2 annotated, #MP is in #R1 and adjacent to a boundary between #R1 and #R2).
Regarding Claim 18. Lee discloses The semiconductor device as claimed in claim 17, wherein the marking portion extends from the first region to the second region, and continuously crosses the boundary (Figure 2 annotated, #MP extends from #R1 to #R2 and continuously crosses the boundary between #R1 and #R2).
Regarding Claim 19. Lee discloses The semiconductor device as claimed in claim 12, wherein the patterned dummy layer (#252a and #246a) and the first material layer (#244, #242a, and #254) comprise different materials ([0051], #240a of #244 comprises tungsten; [0054], #252a comprises tetraethyl orthosilicate, i.e. the first material layer and the pattern dummy layer comprise different materials).
Claim(s) 12 and 20 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by US 2023/0030176 A1; Lee et al.; 02/2023; (“Lee”). Annotated versions of Figures 2 and 3 from Lee are provided above and referenced in the following rejection.
Regarding Claim 12. Lee discloses A semiconductor device (Figure 2, a DRAM device according to [0011] with Figure 3 being a corresponding plan view according to [0021]), comprising:
a substrate (#100, Figure 2, substrate) having a first region (#R1, Figure 2 annotated) and a second region (#R2, Figure 2 annotated) adjacent to the first region (Figure 2, #R1 and #R2 are adjacent);
a plurality of first components (#120, Figure 2, bit line structures) formed over the substrate and in the first region (Figure 2 annotated, #120s are formed over #100 in #R1);
a second component (#124 and #102, Figure 2, transistor and its adjacent isolation structure) formed over the substrate and in the second region (Figure 2 annotated, #124 and #102 are formed over #100 in #R2);
a first material layer (#244, #242a, and #254, Figure 2, upper electrode, polishing stop layer, and third insulating interlayer; examiner notes that [0027]-[0028] of the instant application indicates that the first material layer may comprise a plurality of different materials) formed over the first components (Figure 2, #244, #242a, and #254 are over #120s);
a second material layer (#230, Figure 2, dielectric layer) formed over the second component (Figure 2, #230 is at least partially over the combination of #124 and #102), wherein the second material layer and the first material layer comprise different materials ([0043], #230 is a high-k dielectric layer, i.e. comprises only an insulating material; [0051], #240a of #244 comprises the conductive material tungsten; i.e. the first and second material layers comprise different materials); and
a patterned dummy layer (#252a and #246a, Figure 2, filling insulation pattern and second insulating interlayer pattern) formed over the first components (Figure 2, #252a is formed over #120s), wherein the patterned dummy layer is embedded in the first material layer (Figure 2, #252a is embedded in #240a of #244 and #242a) and an upper surface of the patterned dummy layer is covered by the first material layer (Figure 2, the upper surface of both #252a and #246a is covered by #254).
Regarding Claim 20. Lee discloses The semiconductor device as claimed in claim 12, wherein the first material layer (#244, #242a, and #254) includes a conductive material ([0051], #240a of #244 includes tungsten), and
the second material layer (#230) includes an oxide layer ([0043], #230 may comprise a plurality of different oxide layers including hafnium oxide layer, a zirconium oxide layer, an aluminum oxide layer, or a lanthanum oxide layer).
Response to Arguments
Applicant’s amendments to claim 12 and corresponding arguments, see pages 7-10 of the remarks, filed 01/23/2026, with respect to the 35 U.S.C. 102 rejection of claim 12 as being anticipated by US 2023/0030176 A1; Lee et al.; 02/2023; (“Lee”) have been fully considered but are not found persuasive. Applicant argues that Lee does not disclose “a first material layer . . . and a patterned dummy layer . . . wherein the patterned dummy layer is embedded in the first material layer and an upper surface of the patterned dummy layer is covered by the first material layer”. Examiner respectfully disagrees. Applicant is correct in relation to the original interpretation made in the non-final rejection mailed on 11/05/2025 that the interpreted first material layer (#244 and #242a) does not cover the top surface of the dummy layer (#252a), a new interpretation is made herein in response to the amendment to claim 12. Lee discloses a first material layer (#244, #242a, and #254, Figure 2, upper electrode, polishing stop layer, and third insulating interlayer; examiner notes that [0027]-[0028] of the instant application indicates that the first material layer may comprise a plurality of different materials) . . . and a patterned dummy layer (#252a and #246a, Figure 2, filling insulation pattern and second insulating interlayer pattern) . . . wherein the patterned dummy layer is embedded in the first material layer (Figure 2, #252a is embedded in #240a of #244 and #242a) and an upper surface of the patterned dummy layer is covered by the first material layer (Figure 2, the upper surface of both #252a and #246a is covered by #254). Therefore, it is the examiner’s interpretation that Lee does disclose all of the limitations of amended claim 12.
Applicant’s request for the rejoinder of claims 21-31 and claim 14, see page 10 of the remarks, filed 01/23/2026, with respect to the withdrawal of both claims as being drawn to a non-elected invention and species, respectively, have been fully considered. Currently, claim 12 stands rejected, as described above, such that there is no allowable generic or linking claim and the claims stand withdrawn from consideration. Should claim 12 be determined as allowable, claims 21-31 and 14 will be considered for potential rejoinder.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2017/0256711 A1; Chen et al.; 09/2017 – Figure 2E discloses a plurality of first and second components (#10, transistors) with a first layer (#104) and a second layer (#114) with a patterned layer (#108) embedded in the first layer.
US 2020/0343256 A1; Tsai et al; 10/2020 – Figure 1H discloses a plurality of first components (#110) and a second component (#140) with a first layer (#130) and a second layer (#30) with a patterned dummy layer (#10a) embedded in the first layer.
US 10,943,908 B2; Bae et al.; 03/2021 – Figure 13 discloses a plurality of first components (#30) and a second component (#33p) with a first layer (#62) and a second layer (#85) with a patterned layer (#42a and #46a) embedded in the first layer.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TYLER JAMES WIEGAND whose telephone number is (571)270-0096. The examiner can normally be reached Mon-Fri. 8AM-5PM.
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/TYLER J WIEGAND/Examiner, Art Unit 2812 /CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812