DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kawa et al. (US 2015/0370950).
Regarding claim 1, Kawa teaches various vertical CMOS devices using a backside contact and metal 0 over the diffusion areas (FIG. 11 – 15):
A device, comprising:
a first vertical field effect transistor (Gate A) having a first drain/source region and a second drain/source region (FIG. 12);
a second vertical field effect transistor (Gate B) having a third drain/source region and a fourth drain/source region (FIG. 12);
a first power contact (Vdd) situated on a frontside of the device and coupled to the first drain/source region;
a second power contact (Vss) situated on the frontside of the device and coupled to the third drain/source region; and
a contact situated (n+ source) on a backside of the device and coupled to the second drain/source region and to the fourth drain/source region (FIG. 12).
Regarding claim 2, Kawa teaches (FIG. 11 – 15):
The device of claim 1, wherein the first power contact is electrically coupled through a first metal layer (M1) and a metal over diffusion layer (M0 is a metal layer placed directly over the diffusion areas) to the first drain/source region.
Regarding claim 3, Kawa teaches (FIG. 11):
The device of claim 2, wherein the metal over diffusion layer is L shaped, H shaped, I shaped, Z shaped, P shaped, F shaped, U shaped, T shaped, or four shaped.
Regarding claim 4, Kawa teaches (FIG. 13):
The device of claim 1, wherein the second power contact is electrically coupled through a first metal layer (M1) and a metal over diffusion layer (M0 is a metal layer placed directly over the diffusion areas) to the third drain/source region.
Regarding claim 5, Kawa teaches (FIG. 12):
The device of claim 1, wherein the contact is directly connected to the second drain/source region and to the fourth drain/source region.
Regarding claim 6, Kawa teaches (FIG. 13):
The device of claim 1, comprising a gate contact (773) situated on the frontside of the device and coupled to a polycrystalline silicon layer that is connected to a first gate of the first vertical field effect transistor and to a second gate of the second vertical field effect transistor (FIG. 13).
Regarding claim 7, Kawa teaches (FIG. 12):
The device of claim 1, comprising a filler portion configured to electrically connect the contact situated on the backside of the device to the frontside of the device (780).
Regarding claim 8, Kawa teaches (FIG. 12):
The device of claim 7, wherein the filler portion includes a deep via electrically connected to the contact and to a polycrystalline silicon layer that is coupled to a frontside metal layer (780).
Regarding claim 9, Kawa teaches (FIG. 11, 15):
The device of claim 1, wherein the contact is L shaped, H shaped, I shaped, Z shaped, P shaped, F shaped, U shaped, or T shaped.
Regarding claim 10, Kawa teaches (FIG. 11, 15):
The device of claim 1, wherein the contact is fork shaped, hammer shaped, or spoon shaped.
Regarding claim 11, Kawa teaches (FIG. 11 – 15):
A device, comprising:
a first vertical field effect transistor (Gate A) having a first drain/source region and a second drain/source region (FIG. 12);
a second vertical field effect transistor (Gate B) having a third drain/source region and a fourth drain/source region (FIG. 12);
a first power contact (Vdd) situated on a frontside of the device and connected to a first frontside metal layer portion (M1) that is connected to a first metal over diffusion layer portion (M0 is a metal layer placed directly over the diffusion areas) that is connected to the first drain/source region; and
a backside contact (n+ source) situated on a backside of the device and directly connected to the second drain/source region and the fourth drain/source region (FIG. 12).
Regarding claim 12, Kawa teaches (FIG. 11 – 15):
The device of claim 11, comprising a second power contact (Vss) situated on the frontside of the device and connected to the third drain/source region (FIG. 13).
Regarding claim 13, Kawa teaches (FIG. 11 – 15):
The device of claim 12, wherein the second power contact is connected to a second frontside metal layer portion (M1) that is connected to a second metal over diffusion layer portion (M0 is a metal layer placed directly over the diffusion areas) that is connected to the third drain/source region.
Regarding claim 14, Kawa teaches (FIG. 11 – 15):
The device of claim 11, comprising a gate contact (773) situated on the frontside of the device and connected to a polycrystalline silicon layer that is connected to a first gate of the first vertical field effect transistor and to a second gate of the second vertical field effect transistor (FIG. 13).
Regarding claim 15, Kawa teaches (FIG. 11 – 15):
The device of claim 11, comprising a filler (780) configured to electrically connect the backside contact situated on the backside of the device to the frontside of the device.
Regarding claim 16, Kawa teaches (FIG. 11 – 15):
The device of claim 15, wherein the filler includes a deep via electrically connected to the backside contact and a polycrystalline silicon layer that is connected to a second frontside metal layer portion (780, FIG. 12).
Regarding claim 17, Kawa teaches (FIG. 11 – 15):
A method of fabricating a device, the method comprising:
forming a first vertical field effect transistor (Gate A) over a substrate, the first vertical field effect transistor having a first drain/source region and a second drain/source region (FIG. 12);
forming a second vertical field effect transistor (Gate B) over the substrate, the second vertical field effect transistor having a third drain/source region and a fourth drain/source region (FIG. 12);
forming a first power contact (Vdd) on a frontside of the device and coupled to the first drain/source region (FIG. 13);
forming a second power contact (Vss) on the frontside of the device and coupled to the third drain/source region (FIG. 13); and
forming a contact (n+ source) on a backside of the device and coupled to the second drain/source region and to the fourth drain/source region (FIG. 12).
Regarding claim 18, Kawa teaches (FIG. 11 – 15):
The method of claim 17, wherein forming the first power contact comprises forming a first metal over diffusion layer (M0 is a metal layer placed directly over the diffusion areas) over the first drain/source region and electrically connected to the first drain/source region and forming a first metal layer portion (M1) over the first metal over diffusion layer and electrically connected to the first metal over diffusion layer, and forming the second power contact comprises forming a second metal over diffusion layer (M0 is a metal layer placed directly over the diffusion areas) over the third drain/source region and electrically connected to the third drain/source region and forming another first metal layer portion (M1) over the second metal over diffusion layer and electrically connected to the second metal over diffusion layer (FIG. 11, 13).
Regarding claim 19, Kawa teaches (FIG. 11 – 15):
The method of claim 17, wherein forming the contact comprises forming the contact to be directly connected to the second drain/source region and to the fourth drain/source region (FIG. 12).
Regarding claim 20, Kawa teaches (FIG. 11 – 15):
The method of claim 17, comprising forming a filler portion (780) that electrically connects the contact to the frontside of the device, wherein forming the filler portion includes forming a deep via configured to be electrically connected to the contact and forming a polycrystalline silicon layer that is electrically connected to a frontside metal layer (FIG. 12).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CORY W ESKRIDGE whose telephone number is (571)272-0543. The examiner can normally be reached M - F 9 - 5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jerry O'Connor can be reached at (571) 272-6787. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CORY W ESKRIDGE/Primary Examiner, Art Unit 3624