Prosecution Insights
Last updated: April 19, 2026
Application No. 18/311,907

THERMAL INTERFACE MATERIAL INCLUDING A MULTI-LAYER STRUCTURE AND METHODS OF FORMING THE SAME

Non-Final OA §102
Filed
May 04, 2023
Examiner
HO, ANTHONY
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company Limited
OA Round
1 (Non-Final)
91%
Grant Probability
Favorable
1-2
OA Rounds
2y 5m
To Grant
93%
With Interview

Examiner Intelligence

Grants 91% — above average
91%
Career Allow Rate
1007 granted / 1110 resolved
+22.7% vs TC avg
Minimal +2% lift
Without
With
+2.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
38 currently pending
Career history
1148
Total Applications
across all art units

Statute-Specific Performance

§101
2.3%
-37.7% vs TC avg
§103
31.8%
-8.2% vs TC avg
§102
40.5%
+0.5% vs TC avg
§112
16.1%
-23.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1110 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Group II, claims 10-16, in the reply filed on September 29, 2025 is acknowledged. Information Disclosure Statement The information disclosure statement (IDS) submitted on February 27, 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Eid et al (US Pub 2019/0323785). Eid et al discloses a thermal interface material, comprising: a planar shape extending along a width direction, a length direction, and a thickness direction (i.e. see at least Figure 1); and a multi-layer structure comprising alternating layers of a first component (i.e. 150) and a second component (i.e. 160) stacked along the width direction such that interfaces between adjacent layers are perpendicular to the width direction and extend in the length direction and the thickness direction, wherein each of the first component and the second component comprises a thermally conductive material comprising one or more of graphite, graphene, carbon nanotubes, a metal, and a phase change material (i.e. paragraph 0041 discloses 150 is made of at least carbon nanotubes; paragraph 0040 discloses 160 is made of at least metal). Allowable Subject Matter Claims 11-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 21-33 are allowed. The following is an examiner’s statement of reasons for allowance: The closest prior art of Eid et al (US Pub 2019/0323785) either singularly or in combination fails to anticipate or render obvious a semiconductor package, comprising: a package substrate; at least one semiconductor die mounted on the package substrate; a package lid overlying the at least onc semiconductor die and attached to the package substrate; and a thermal interface material located between a top surface of the at least one semiconductor die and an interior surface of the package lid, wherein the thermal interface material comprises: a first component comprising graphite dispersed in an adhesive polymer matrix such that the first component adheres to at least one of the top surface of the at least one semiconductor die or the interior surface of the package lid, wherein the first component has a first surface roughness; and a second component comprising a thermally conductive material dispersed in a polymer matrix, wherein the thermal interface material has a multi-layer structure comprising alternating layers of the first component and the second component stacked along a width direction such that interfaces between adjacent layers are perpendicular to the width direction and extend in a length direction and the thickness direction, wherein the second component has a second surface roughness lower than the first surface roughness as recited in claim 21 and a thermal interface material, comprising: a multi-layer structure comprising alternating layers of a first component and a second component, wherein the multi-layer structure includes a planar shape extending along a width direction, a length direction, and a thickness direction; wherein the first component and the second component are stacked along the width direction such that interfaces between adjacent layers are perpendicular to the width direction and extend in the length direction and the thickness direction, wherein the first component comprises a thermally conductive material dispersed in a first polymer matrix, the first polymer matrix being an adhesive polymer matrix such that the first component has adhesive properties; wherein the second component comprises a thermally conductive material dispersed in a second polymer matrix; and wherein the first component has a first thermal conductivity, and the second component has a second thermal conductivity greater than the first thermal conductivity as recited in claim 29. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. a. Cola et al (US Pub 2020/0404809) b. Kim et al (US Pub 2019/0036186) Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHONY HO whose telephone number is (571)270-1432. The examiner can normally be reached 9AM - 5PM, Monday-Friday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ANTHONY HO/Primary Examiner, Art Unit 2817
Read full office action

Prosecution Timeline

May 04, 2023
Application Filed
Feb 07, 2026
Non-Final Rejection — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12604478
SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME
2y 5m to grant Granted Apr 14, 2026
Patent 12593662
ELECTRONIC DEVICE FOR DETECTING DEFECT IN SEMICONDUCTOR PACKAGE AND OPERATING METHOD THEREOF
2y 5m to grant Granted Mar 31, 2026
Patent 12575309
PRODUCTION METHOD FOR PATTERNED ORGANIC FILM, PRODUCTION APPARATUS FOR PATTERNED ORGANIC FILM, ORGANIC SEMICONDUCTOR DEVICE PRODUCED BY SAME, AND INTEGRATED CIRCUIT INCLUDING ORGANIC SEMICONDUCTOR DEVICE
2y 5m to grant Granted Mar 10, 2026
Patent 12575267
DISPLAY SUBSTRATE AND PREPARATION METHOD THEREFOR, AND DISPLAY APPARATUS
2y 5m to grant Granted Mar 10, 2026
Patent 12568758
LIGHT-EMITTING DEVICE AND ELECTRONIC APPARATUS INCLUDING THE SAME
2y 5m to grant Granted Mar 03, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
91%
Grant Probability
93%
With Interview (+2.3%)
2y 5m
Median Time to Grant
Low
PTA Risk
Based on 1110 resolved cases by this examiner. Grant probability derived from career allow rate.

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