DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group II in the reply filed on 9/27/2025 is acknowledged. Claims 11-30 are under consideration.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 11-12, 18-19 and 23-26 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Matsunaga et al (10,840,213).
With respect to Claim 11, Matsunaga et al discloses a wafer bonding method (Figures 16D – 16H) comprising: coupling a first wafer (Figure 16D, W1b) to a first wafer chuck (Figure 16D, 230); coupling a second wafer (Figure 16D, W2b) to a second wafer chuck (Figure 16D, 231), wherein at least one of the first wafer chuck and the second wafer chuck is provided with a plurality of bonding pins (Figure 13, 245, 251 and 265) configured to be moveable to apply pressure to bend at least one of the first wafer and the second wafer; Initiating a wafer bonding process by bringing the first wafer and the second wafer into contact at a first bonding position (Figure 16E, center) using at least one of the plurality of bonding pins; and continuing the wafer bonding process by bringing the first wafer and the second wafer into contact in a second bonding position (Figures 16F – 16H) further from a center position of the first wafer and the second wafer than the first bonding position using at least another one of the plurality of bonding pins (Figures 14-15, 245 and 265). See Figures 13-16H, and corresponding text, especially column 20, line 60 to column 24, line 40.
With respect to Claim 12, Matsunaga et al discloses wherein the bonding between the first wafer and the second wafer starts from the first bonding position (center) , passes through the second bonding position, and spreads to edge regions of the first wafer and the second wafer in a radial and wave-like fashion (the spreading in a wave-like fashion is inherent as all of the claim components and steps are disclosed). See Figures 16E – 16F.
With respect to Claim 18, Matsunaga et al discloses wherein the first wafer is vacuum coupled to the first wafer chuck, and the second wafer is vacuum coupled to the second wafer chuck. See column 21, lines 1-30.
With respect to Claim 19, Matsunaga et al discloses a wafer bonding method (Figure 16E) comprising: coupling a first wafer (Figure 16E, W1b) to a first wafer chuck (Figure 16E, 230), wherein the first wafer chuck is provided with a plurality of first apertures (Figure 16E-16F, 240c, 240b, 240a) capable of applying gas pressure to bend the first wafer; coupling a second wafer (Figure 16E, W2b) to a second wafer chuck (Figure 16E, 231), wherein the second wafer chuck is provided with a plurality of second apertures Figure 16E-16F, 260b, 260a) capable of applying gas pressure to bend the second wafer; initiating a wafer bonding process by bringing the first wafer and the second wafer into contact at a first bonding position using one of the plurality of first apertures (Figure 16E, 240b) and corresponding one of the plurality of second apertures (Figure 16E, 260a) ; and continuing the wafer bonding process by bringing the first wafer and the second wafer into contact in a second bonding position further from a center region of the first wafer and the second wafer than the first bonding position using more of the first apertures (Figure 16E, 240c) and more of the second apertures (Figure 16E, 260b).
With respect to Claim 23, Matsunaga et al discloses wherein the bonding between the first wafer and the second wafer starts from the first bonding position (center) , passes through the second bonding position, and spreads to edge regions of the first wafer and the second wafer in a radial and wave-like fashion (the spreading in a wave-like fashion is inherent as all of the claim components and steps are disclosed). See Figures 16E – 16G.
With respect to Claim 24, Matsunaga et al discloses wherein the first wafer is vacuum coupled to the first wafer chuck, and the second wafer is vacuum coupled to the second wafer chuck. See column 21, lines 1-30.
With respect to Claim 25, Matsunaga et al disclose coupling a first wafer (16D, W1b) to a first wafer chuck (Figure 16D, 230), the first wafer chuck comprising a plurality of first bonding pins (Figure 13, 245) configured to be retracted into or extended from the first wafer chuck, wherein the extended first bonding pins are capable of applying pressure to bend the first wafer (Figure 14 and 16E, inherent, as pressure in contacted areas would inherently cause non-contacted areas to sag) ; coupling a second wafer (Figure 16D, W2b) to a second wafer chuck (Figure 16D, 231), the second wafer chuck comprising a plurality of second bonding pins (Figure 13, 265) configured to be retracted into or extended from the second wafer chuck, wherein the extended second bonding pins are capable of applying pressure to bend the second wafer (Figure 14 and 16E, inherent, as pressure in contacted areas would inherently cause non-contacted areas to sag); initiating a wafer bonding process by bringing the first wafer and the second wafer into contact at a first bonding position using one of the plurality of first bonding pins and a corresponding one of the plurality of second bonding pins (Figure 13-15 and 16E); and continuing the wafer bonding process by bringing the first wafer and the second wafer into contact in a second bonding position further from a center region of the first wafer and the second wafer than the first bonding position using more of the plurality of first bonding pins and more of the plurality of second bonding pins (Figure 13-15 and Figure 16F-16G). See Claim 1 and Figures 14-15, 245 and 265, and Figures 13, 16D -16E-G and corresponding text, especially column 20, line 60 to column 24, line 40.
With respect to Claim 26, Matsunaga et al discloses wherein the bonding between the first wafer and the second wafer starts from the first bonding position (center) , passes through the second bonding position, and spreads to edge regions of the first wafer and the second wafer in a radial and wave-like fashion (the spreading in a wave-like fashion is inherent as all of the claim components and steps are disclosed).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 14-17, 21-22 and 28-30 are rejected under 35 U.S.C. 103 as being unpatentable over Matsunaga et al (10,840,213).
Matsunaga et al is relied upon as discussed.
However , Matsunaga et al do not explicitly disclose symmetrical and asymmetrical wafer structures (Claims 14-15, 21-22, 28-29), and a plurality of bonding pins which are moved simultaneously or separately by a controller (Claims 16-17, 30).
With respect to Claims 14-15, 21-22, 28-29 and the symmetrical or asymmetrical shapes of the wafers , it would have been obvious to one of ordinary skill in the art, before the effective date of the invention, to arrive at the limitation of symmetrical or asymmetrical shapes, as changes in shape are prima facie obvious in the absence of unobvious results. See In re Dailey, 149 USPQ 47 (CCPA 1966). As Matsunaga et al pertains to wafers in general, the use of symmetrical or asymmetrical wafers would have been within the skill of one of ordinary skill in the art.
With respect to Claims 16-17 and 30 and a plurality of bonding pins which are moved simultaneously or separately by a controller, it would have been obvious to one of ordinary skill in the art, before the effective date of the invention, to arrive at the limitation as Matsunaga et al discloses moveable pins and a controller (see Claim 1 of Matsunaga et al) and the use of simultaneous or separate process steps is prima facie to one of ordinary skill in the art, as selection of order of performing process steps is prima facie obvious in the absence of new or unexpected results. See In re Burhans, 69 USPQ 330 (CCPA 1946).
With respect to Claim 14, and the limitation “wherein when both the first wafer and the second wafer have symmetrical structures, the wafer bonding process is initiated by bringing the first wafer and the second wafer into contact at the first bonding position using a center bonding pin of the plurality of bonding pin , and the first bonding position is at the center region of the first wafer and the second wafer”, it would have been obvious to one of ordinary skill in the art, before the effective date of the invention, to arrive at the limitation of symmetrical or asymmetrical shapes, as changes in shape are prima facie obvious in the absence of unobvious results. See In re Dailey, 149 USPQ 47 (CCPA 1966). As Matsunaga et al pertains to wafers in general, the use of symmetrical or asymmetrical wafers would have been within the skill of one of ordinary skill in the art. Moreover, see Figures 16E-16H of Matsunaga et al disclose starting at the center and then bonding the peripheral region.
With respect to Claim 15 and the limitation “wherein when at least one of the first wafer and the second wafer has an asymmetrical structure, the wafer bonding process is initiated by bringing the first wafer and the second wafer into contact at the first bonding position using a bonding pin located near a center bonding pin of the plurality of bonding pins, and the first bonding position deviates from the center position of the first wafer and the second wafer”, it would have been obvious to one of ordinary skill in the art, before the effective date of the invention, to arrive at the limitation of symmetrical or asymmetrical shapes, as changes in shape are prima facie obvious in the absence of unobvious results. See In re Dailey, 149 USPQ 47 (CCPA 1966). As Matsunaga et al pertains to wafers in general, the use of symmetrical or asymmetrical wafers would have been within the skill of one of ordinary skill in the art. Moreover, see Figures 16E-16H of Matsunaga et al disclose starting at the center and then bonding the peripheral region.
With respect to Claim 16, and the limitation “wherein both the first wafer chuck and the second wafer chuck are provided with a plurality of bonding pins, and a pair of corresponding bonding pins of the plurality of bonding pins of the first wafer chuck and the second wafer chuck are simultaneously moved under the control of a controller during the wafer bonding process”, it would have been obvious to one of ordinary skill in the art, before the effective date of the invention, to arrive at the limitation as Matsunaga et al discloses moveable pins and a controller (see Claim 1 of Matsunaga et al) and the use of simultaneous or separate process steps is prima facie to one of ordinary skill in the art, as selection of order of performing process steps is prima facie obvious in the absence of new or unexpected results. See In re Burhans, 69 USPQ 330 (CCPA 1946).
With respect to Claim 17, and the limitation “ wherein both the first wafer chuck and the second wafer chuck are provided with a plurality of bonding pins, and a pair of corresponding bonding pins of the plurality of bonding pins of the first wafer chuck and the second wafer chuck are separately moved under the control of the controller during the wafer bonding process”, it would have been obvious to one of ordinary skill in the art, before the effective date of the invention, to arrive at the limitation as Matsunaga et al discloses moveable pins and a controller (see Claim 1 of Matsunaga et al) and the use of simultaneous or separate process steps is prima facie to one of ordinary skill in the art, as selection of order of performing process steps is prima facie obvious in the absence of new or unexpected results. See In re Burhans, 69 USPQ 330 (CCPA 1946).
With respect to Claim 21, and the limitation ” wherein when both the first wafer and the second wafer have symmetrical structures, the wafer bonding process is initiated by bringing the first wafer and the second wafer into contact at the first bonding position using a first center aperture of the plurality of first apertures and a center second aperture of the plurality of second apertures, and the first bonding position is at the center region of the first wafer and the second wafer”, it would have been obvious to one of ordinary skill in the art, before the effective date of the invention, to arrive at the limitation of symmetrical or asymmetrical shapes, as changes in shape are prima facie obvious in the absence of unobvious results. See In re Dailey, 149 USPQ 47 (CCPA 1966). As Matsunaga et al pertains to wafers in general, the use of symmetrical or asymmetrical wafers would have been within the skill of one of ordinary skill in the art. Moreover, see Figures 16E-16H of Matsunaga et al disclose starting at the center and then bonding the peripheral region.
With respect to Claim 22, and the limitation “wherein at least one of the first wafer and the second wafer has an asymmetrical structure, and the wafer bonding process is initiated by bringing the first wafer and the second wafer into contact at the first bonding position using a first aperture located near a center first aperture of the first apertures and a second aperture located near a center second aperture of the second apertures, and the first bonding position deviates from the center region of the first wafer and the second wafer”, it would have been obvious to one of ordinary skill in the art, before the effective date of the invention, to arrive at the limitation of symmetrical or asymmetrical shapes, as changes in shape are prima facie obvious in the absence of unobvious results. See In re Dailey, 149 USPQ 47 (CCPA 1966). As Matsunaga et al pertains to wafers in general, the use of symmetrical or asymmetrical wafers would have been within the skill of one of ordinary skill in the art. Moreover, see Figures 16E-16H of Matsunaga et al disclose starting at the center and then bonding the peripheral region.
With respect to Claim 28, Claim 28 is rejected for the reasons as discussed above with respect to Claim 25 and Claim 14.
With respect to Claim 29, Claim 29 is rejected for the reasons as discussed above with respect to Claim 25 and Claim 15
With respect to Claim 30, Claim 30 is rejected for the reasons as discussed above with respect to Claim 25 and 17.
Claims 13, 20 and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Matsunaga et al (10,840,213) as applied to claims 11-12, 18-19 and 23-26 above, and further in view of Schepis et al (US 2023/0326814).
Matsunaga et al is relied upon as discussed above.
However, Matsunaga et al does not disclose measuring warpage of the first wafer and the second wafer using a wafer metrology tool; and determining the first bonding position based on measurement information from the wafer metrology tool.
Schepis et al is relied upon to disclose measuring warpage of the first wafer and the second wafer using a wafer metrology tool; and determining the first bonding position based on measurement information from the wafer metrology tool. See Figure 2B and corresponding text, especially paragraphs 6, 19-24, 50-59 and 84.
With respect to Claims 13, 20 and 27, it would have been obvious to one of ordinary skill in the art, before the effective date of the invention, to use a measurement tool to measure warpage and determine the first bonding position in the process of Matsunaga et al, for its known benefit in the art of obtaining a better bond as disclosed by Schepis et al. The use of a known component, a metrology tool, for its known benefit would have been prima facie obvious to one of ordinary skill in the art.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDER G GHYKA whose telephone number is (571)272-1669. The examiner can normally be reached Monday-Friday 9-6.
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AGG
February 9, 2026
/ALEXANDER G GHYKA/Primary Examiner, Art Unit 2812