DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicants’ response of 5/11/2026 has been considered and entered in the record. Claims 11-30 are under consideration. The rejections of record are withdrawn in view of Applicants’ amendments and arguments. The following new rejections are made for Claims 11-18. Claims 19-30 are allowed. Applicants’ arguments have been considered, but are not persuasive in view of the new grounds of rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 11-12 and 14-18 are rejected under 35 U.S.C. 103 as being unpatentable over Matsunaga et al (10,840,213) in view of Nguyen et al (US 2014/0113433).
With respect to Claim 11, Matsunaga et al discloses a wafer bonding method (Figures 16D – 16H) comprising: coupling a first wafer (Figure 16D, W1b) to a first wafer chuck (Figure 16D, 230); coupling a second wafer (Figure 16D, W2b) to a second wafer chuck (Figure 16D, 231), wherein at least one of the first wafer chuck and the second wafer chuck is provided with a plurality of bonding pins (Figure 13, 245, 251 and 265) configured to be moveable to apply pressure to bend at least one of the first wafer and the second wafer during a wafer bonding process; initiating the wafer bonding process by using at least one of the plurality of bonding pins to extend through the at least one of the first wafer chuck and the second wafer chuck to bring the first wafer and the second wafer into contact at a first bonding position (Figure 16E, center); and continuing the wafer bonding process by bringing the first wafer and the second wafer into contact in a second bonding position (Figures 16F – 16H) further from a center position of the first wafer and the second wafer than the first bonding position. See Figures 13-16H, and corresponding text, especially column 20, line 60 to column 24, line 40.
However, Matsunaga et al does not disclose “using at least another one of the plurality of bonding pins to extend through the at least one of the first wafer chuck and the second wafer chuck to bring the first wafer and the second wafer into contact in a second bonding position further from a center region of the first wafer and the second wafer than the first bonding position”.
Nguyen et al also pertains to a wafer bonding process and disclose a multitude of pins (Figures 7-12, 220) which are peripheral to a central bonding pin (Figures 7-12, 210) and which extend through a wafer chuck (Figures 7-12, 23), and which are used to bring the first wafer and the second wafer into contact in a second bonding position further from a center region of the first wafer and the second wafer than the first bonding position. See Figures 7-12 and corresponding text, especially paragraph 54.
It would have been obvious for one of ordinary skill in the art, before the effective date of the invention, to use multiple pins which go through the chuck in the process of Matsunaga et al, for their known benefit of bonding two wafers, as disclosed by Nguyen et al. The use of known elements, bonding pins which penetrate through the chuck, for their known benefit, would have been prima facie obvious to one of ordinary skill in the art. Moreover, the use of multiple bonding pins would be considered duplication of parts, for their known benefit, and would be prima facie obvious to one of ordinary skill in the art. See In re Harza, 124 USPQ 378 (CCPA 1960).
With respect to Claim 12, the combined references make obvious the limitation “wherein the bonding between the first wafer and the second wafer starts from the first bonding position (center) , passes through the second bonding position, and spreads to edge regions of the first wafer and the second wafer in a radial and wave-like fashion” (the spreading in a wave-like fashion is inherent as all of the claim components and steps are disclosed). See Figures 16E – 16F of Matsunaga et al and corresponding text; and Figures 7-12 of Nguyen et al and corresponding text.
With respect to Claims 14-15, Matsunaga et al or Nguyen et al do not explicitly disclose symmetrical and asymmetrical wafer structures (Claims 14-15), and a plurality of bonding pins which are moved simultaneously or separately by a controller (Claims 16-17).
With respect to Claims 14-15 and the symmetrical or asymmetrical shapes of the wafers , it would have been obvious to one of ordinary skill in the art, before the effective date of the invention, to arrive at the limitation of symmetrical or asymmetrical shapes, as changes in shape are prima facie obvious in the absence of unobvious results. See In re Dailey, 149 USPQ 47 (CCPA 1966). As Matsunaga et al and Nguyen et al pertain to wafers in general, the use of symmetrical or asymmetrical wafers would have been within the skill of one of ordinary skill in the art.
With respect to Claim 14, and the limitation “wherein when both the first wafer and the second wafer have symmetrical structures, the wafer bonding process is initiated by bringing the first wafer and the second wafer into contact at the first bonding position using a center bonding pin of the plurality of bonding pin , and the first bonding position is at the center region of the first wafer and the second wafer”, it would have been obvious to one of ordinary skill in the art, before the effective date of the invention, to arrive at the limitation of symmetrical or asymmetrical shapes, as changes in shape are prima facie obvious in the absence of unobvious results. See In re Dailey, 149 USPQ 47 (CCPA 1966). As Matsunaga et al pertains to wafers in general, the use of symmetrical or asymmetrical wafers would have been within the skill of one of ordinary skill in the art. Moreover, see Figures 16E-16H of Matsunaga et al disclose starting at the center and then bonding the peripheral region; and Figures 7-12 of Nguyen et al.
With respect to Claim 15 and the limitation “wherein when at least one of the first wafer and the second wafer has an asymmetrical structure, the wafer bonding process is initiated by bringing the first wafer and the second wafer into contact at the first bonding position using a bonding pin located near a center bonding pin of the plurality of bonding pins, and the first bonding position deviates from the center position of the first wafer and the second wafer”, it would have been obvious to one of ordinary skill in the art, before the effective date of the invention, to arrive at the limitation of symmetrical or asymmetrical shapes, as changes in shape are prima facie obvious in the absence of unobvious results. See In re Dailey, 149 USPQ 47 (CCPA 1966). As Matsunaga et al pertains to wafers in general, the use of symmetrical or asymmetrical wafers would have been within the skill of one of ordinary skill in the art. Moreover, see Figures 16E-16H of Matsunaga et al and Nguyen et al disclose starting at the center and then bonding the peripheral region.
With respect to Claims 16-17 and a plurality of bonding pins which are moved simultaneously or separately by a controller, it would have been obvious to one of ordinary skill in the art, before the effective date of the invention, to arrive at the limitation as Matsunaga et al and Nguyen et al disclose moveable pins and a controller (see Claim 1 of Matsunaga et al; and Claim 1 of Nguyen et al) and the use of simultaneous or separate process steps is prima facie to one of ordinary skill in the art, as selection of order of performing process steps is prima facie obvious in the absence of new or unexpected results. See In re Burhans, 69 USPQ 330 (CCPA 1946).
With respect to Claim 16, and the limitation “wherein both the first wafer chuck and the second wafer chuck are provided with a plurality of bonding pins, and a pair of corresponding bonding pins of the plurality of bonding pins of the first wafer chuck and the second wafer chuck are simultaneously moved under the control of a controller during the wafer bonding process”, it would have been obvious to one of ordinary skill in the art, before the effective date of the invention, to arrive at the limitation as Matsunaga et al and Nguyen et al disclose moveable pins and a controller (see Claim 1 of Matsunaga et al; and Claim 1 of Nguyen et al) and the use of simultaneous or separate process steps is prima facie to one of ordinary skill in the art, as selection of order of performing process steps is prima facie obvious in the absence of new or unexpected results. See In re Burhans, 69 USPQ 330 (CCPA 1946).
With respect to Claim 17, and the limitation “ wherein both the first wafer chuck and the second wafer chuck are provided with a plurality of bonding pins, and a pair of corresponding bonding pins of the plurality of bonding pins of the first wafer chuck and the second wafer chuck are separately moved under the control of the controller during the wafer bonding process”, it would have been obvious to one of ordinary skill in the art, before the effective date of the invention, to arrive at the limitation as Matsunaga et al and Nguyen et al disclose moveable pins and a controller (see Claim 1 of Matsunaga et al; and Claim 1 of Nguyen et al ) and the use of simultaneous or separate process steps is prima facie to one of ordinary skill in the art, as selection of order of performing process steps is prima facie obvious in the absence of new or unexpected results. See In re Burhans, 69 USPQ 330 (CCPA 1946).
With respect to Claim 18, Matsunaga et al discloses wherein the first wafer is vacuum coupled to the first wafer chuck, and the second wafer is vacuum coupled to the second wafer chuck. See column 21, lines 1-30.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Matsunaga et al (10,840,213) in view of Nguyen et al (US 2014/0113433) as applied to claims 11-12 and 14-18 above, and further in view of Schepis et al (US 2023/0326814).
Matsunaga et al and Nguyen et al are relied upon as discussed above.
However, neither Matsunaga et al nor Nguyen et al disclose measuring warpage of the first wafer and the second wafer using a wafer metrology tool; and determining the first bonding position based on measurement information from the wafer metrology tool.
Schepis et al is relied upon to disclose measuring warpage of the first wafer and the second wafer using a wafer metrology tool; and determining the first bonding position based on measurement information from the wafer metrology tool. See Figure 2B and corresponding text, especially paragraphs 6, 19-24, 50-59 and 84.
With respect to Claim 13, it would have been obvious to one of ordinary skill in the art, before the effective date of the invention, to use a measurement tool to measure warpage and determine the first bonding position in the process of Matsunaga et al in view of Nguyen et al , for its known benefit in the art of obtaining a better bond as disclosed by Schepis et al. The use of a known component, a metrology tool, for its known benefit would have been prima facie obvious to one of ordinary skill in the art.
Allowable Subject Matter
Claims 19-30 are allowed.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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AGG
July 15, 2026
/ALEXANDER G GHYKA/Primary Examiner, Art Unit 2812
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