Prosecution Insights
Last updated: April 19, 2026
Application No. 18/312,019

METHOD OF FORMING A SILICON COMPRISING LAYER

Non-Final OA §103
Filed
May 04, 2023
Examiner
MILLER, MICHAEL G
Art Unit
1712
Tech Center
1700 — Chemical & Materials Engineering
Assignee
Asm Ip Holding B V
OA Round
1 (Non-Final)
50%
Grant Probability
Moderate
1-2
OA Rounds
4y 0m
To Grant
68%
With Interview

Examiner Intelligence

Grants 50% of resolved cases
50%
Career Allow Rate
312 granted / 622 resolved
-14.8% vs TC avg
Strong +18% interview lift
Without
With
+18.1%
Interview Lift
resolved cases with interview
Typical timeline
4y 0m
Avg Prosecution
18 currently pending
Career history
640
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
65.2%
+25.2% vs TC avg
§102
13.8%
-26.2% vs TC avg
§112
16.8%
-23.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 622 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Claims 1-16 in the reply filed on 29 SEP 2025 is acknowledged. Claim 17 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 29 SEP 2025. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 1-10, 12-13, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Singh ‘581 (U.S. PGPub 2007/0087581). Claim 1 – Singh ‘581 teaches a method of forming a silicon-comprising layer on a substrate (PG 0036-0048), the method comprising: providing the substrate to a process chamber (PG 0038), the process chamber being comprised in a low pressure chemical deposition (LPCVD) furnace (PG 0054, LPCVD processes known for nitridation of silicon; PG 0033, process chamber capable of sustaining microTorr pressures) and performing, repetitively, a deposition cycle, thereby forming on the substrate the silicon-comprising layer, wherein the deposition cycle comprises (Figure 4): a first deposition pulse comprising a provision of a first precursor, comprising a silicon-containing compound, into the process chamber (PG 0039), a first purge pulse for removing a portion of the first precursor from the process chamber (PG 0040), a second deposition pulse comprising a provision of a second precursor, comprising a nitrogen-containing compound, into the process chamber (PG 0044 in view of PG 0054, PG 0010 expressly contemplates silicon nitride films), and a second purge pulse for removing a portion of the second precursor from the process chamber (PG 0045), wherein the process chamber is maintained at a process temperature in a range from about 400 °C to about 650 °C during the deposition cycle (PG 0027, e.g. 500 °C; PG 0054, e.g. 600 °C). and wherein the process chamber is maintained, during the first deposition pulse, at a first pressure (PG 0039, first pressure) and is maintained , during the second deposition pulse, at a second pressure (PG 0044, second pressure). Singh ‘581 does not expressly teach or suggest wherein said first and second pressures are different from each other. The previously cited paragraphs discussing deposition pressure disclose flow rates and pressures as variables to be controlled for saturation of the substrate surface; selection of appropriate values commensurate with the claim is therefore held as prima facie obvious. Claim 2 – Singh ‘581 renders obvious the method according to claim 1, but does not expressly teach or suggest wherein the process chamber is maintained at a process temperature in a range from about 510 °C to about 550 °C during the deposition cycle. Singh ‘581 PG 0038 discloses thermal control of the substrate temperature and by extension thermal control of the chamber temperature, noting that this temperature selection may be chosen in accordance with the deposition to be performed. Selection of appropriate temperature values commensurate with the claim is therefore held as prima facie obvious. Claim 3 – Singh ‘581 renders obvious the method according to claim 1, but does not expressly teach or suggest wherein the first pressure is lower than the second pressure. Singh ‘581 PG 0039 and PG 0044 disclose first and second pressures respectively. The cited paragraphs discussing deposition pressure disclose flow rates and pressures as variables to be controlled for saturation of the substrate surface; selection of appropriate values commensurate with the claim is therefore held as prima facie obvious. Claim 4 – Singh ‘581 renders obvious the method according to claim 1, but does not expressly teach or suggest wherein the first pressure is in a range from about 6 Torr to about 10 Torr and wherein the second pressure is in a range from about 15 Torr to about 25 Torr. Singh ‘581 PG 0039 and PG 0044 disclose first and second pressures respectively. The cited paragraphs discussing deposition pressure disclose flow rates and pressures as variables to be controlled for saturation of the substrate surface; selection of appropriate values commensurate with the claim is therefore held as prima facie obvious. Claim 5 – Singh ‘581 renders obvious the method according to claim 1, but does not expressly teach or suggest wherein the first precursor is provided into the process chamber at a first flow rate being lower than a second flow rate of the second precursor. Singh ‘581 PG 0039 and PG 0044 disclose first and second flow rates respectively. The cited paragraphs discussing deposition flow rates disclose flow rates and pressures as variables to be controlled for saturation of the substrate surface; selection of appropriate values commensurate with the claim is therefore held as prima facie obvious. Claim 6 – Singh ‘581 renders obvious the method according to claim 5, but does not expressly teach or suggest wherein the first flow rate is up to 500 sccm and wherein the second flow rate is up to 770 sccm. Singh ‘581 PG 0039 and PG 0044 disclose first and second flow rates respectively. The cited paragraphs discussing deposition flow rates disclose flow rates and pressures as variables to be controlled for saturation of the substrate surface; selection of appropriate values commensurate with the claim is therefore held as prima facie obvious. Claim 7 – Singh ‘581 renders obvious the method according to claim 1, but does not expressly teach or suggest wherein the provision of the first precursor, into the process chamber, is shorter than the provision of the second precursor. Singh ‘581 PG 0039 and 0044 disclose separate exposure protocols such that the substrate is suitably exposed to the reactants. The cited paragraphs discussing deposition flow rates disclose flow rates and pressures as variables to be controlled for saturation of the substrate surface; selection of appropriate values commensurate with the claim is therefore held as prima facie obvious. Claim 8 – Singh ‘581 renders obvious the method according to claim 1, wherein the silicon-containing compound is a silicon halide (Singh ‘581 PG 0054, e.g. dichlorosilane). Claim 9 – Singh ‘581 renders obvious the method according to claim 1, wherein the nitrogen-containing compound is a nitrogen hydride (Singh ‘581 PG 0054, e.g. ammonia). Claim 10 – Singh ‘581 renders obvious the method according to claim 9, wherein the nitrogen hydride is NH3 (Singh ‘581 PG 0054, e.g. ammonia). Claim 12 – Singh ‘581 renders obvious the method according to claim 1, wherein the process chamber comprises a gas injector and wherein the first precursor and the second precursor are alternatingly provided into the process chamber through the gas injector (Singh ‘581 e.g. PG 0039 and 0044 as separate injection steps of the ALD process’ gas necessarily must have a way to enter the deposition chamber and as such a gas injector is held as inherent to the deposition chamber). Claim 13 – Singh ‘581 renders obvious the method according to claim 1, but does not expressly teach or suggest wherein the process chamber comprises two gas injectors, a first gas injector and a second gas injector, and wherein the first precursor and the second precursor are alternatingly provided into the process chamber from the first gas injector and from the second gas injector, respectively. The presence of a gas injector is inherent in Singh ‘581 as there must be a means for process gas to enter a deposition chamber if deposition is to occur; provision of a second gas injector to separately provide process gases is held as prima facie obvious for requiring a mere duplication of parts absent unexpected results derived from the choice of multiple injectors. Claim 16 – Singh ‘581 renders obvious the method according to claim 1, wherein the silicon-comprising layer is a silicon nitride layer (Singh ‘581 PG 0010). Claims 11 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Singh ‘581 (U.S. PGPub 2007/0087581) in view of Wiegers ‘768 (U.S. PGPub 2020/0048768). Claim 11 – Singh ‘581 renders obvious the method according to claim 1, but does not expressly teach or suggest wherein the silicon-comprising layer is formed on a plurality of substrates arranged in a wafer boat, the wafer boat being receivable in the process chamber. Wiegers ‘768 is drawn to vertical furnaces disclosed as suitable for use in LPCVD silicon nitride processes (PG 0027), wherein the furnace holds a wafer boat receivable in the reaction chamber with a plurality of substrates held within (PG 0023-0024). Therefore, it would have been obvious to a person having ordinary skill in the art at the time the invention was made or filed to have modified the invention of Singh ‘581 to use the LPCVD furnace and wafer boat suggested by Wiegers ‘768, as both references contemplate LPCVD furnaces for deposition of silicon nitride and Wiegers ‘768 expressly discloses an LPCVD furnace structure suitable for the purpose. Claim 14 – Singh ‘581 renders obvious the method according to claim 1, but does not expressly teach or suggest wherein the LPCVD furnace is a vertical furnace. Wiegers ‘768 is drawn to vertical furnaces disclosed as suitable for use in LPCVD silicon nitride processes (PG 0027), wherein the furnace holds a wafer boat receivable in the reaction chamber with a plurality of substrates held within (PG 0023-0024). Therefore, it would have been obvious to a person having ordinary skill in the art at the time the invention was made or filed to have modified the invention of Singh ‘581 to use the LPCVD furnace and wafer boat suggested by Wiegers ‘768, as both references contemplate LPCVD furnaces for deposition of silicon nitride and Wiegers ‘768 expressly discloses an LPCVD furnace structure suitable for the purpose. Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Singh ‘581 as applied to claim 1 above, and further in view of Huang ‘324 (U.S. PGPub 2013/0099324). Claim 15 – Singh ‘581 renders obvious the method according to claim 1, but does not expressly teach or suggest wherein the substrate comprises a Group III-nitride containing layer, and wherein the silicon-comprising layer is formed at least partially on said layer. Singh ‘581 PG 0050 discloses semiconductor processing applications. Huang ‘324 PG 0026-0029 disclose a semiconductor wafer structure (PG 0026) comprising a layer of e.g. gallium nitride, aluminum nitride, aluminum gallium nitride, indium gallium nitride, or aluminum gallium indium nitride (PG 0028), which then desirably has a passivation layer of e.g. silicon nitride deposited thereon by e.g. ALD (PG 0029). Therefore, it would have been obvious to a person having ordinary skill in the art at the time the invention was made or filed to have modified the invention of Singh ‘581 to use the specific substrates contemplated by Huang ‘324 in the deposition process, as Singh ‘581 contemplates silicon nitride deposition on semiconductor products and Huang ‘324 teaches the desirability of silicon nitride deposition on a specific class of semiconductor wafers. Aluminum, gallium, and indium are all Group III elements and their corresponding nitrides are Group III-nitrides. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL G MILLER whose telephone number is (571)270-1861. The examiner can normally be reached M-F 9:00-5:30 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Michael Cleveland can be reached at 571-272-1418. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MICHAEL G MILLER/ Primary Examiner, Art Unit 1712
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Prosecution Timeline

May 04, 2023
Application Filed
Dec 13, 2025
Non-Final Rejection — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
50%
Grant Probability
68%
With Interview (+18.1%)
4y 0m
Median Time to Grant
Low
PTA Risk
Based on 622 resolved cases by this examiner. Grant probability derived from career allow rate.

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