Prosecution Insights
Last updated: April 19, 2026
Application No. 18/312,552

CHIP PACKAGE AND MANUFACTURING METHOD THEREOF

Final Rejection §102§103
Filed
May 04, 2023
Examiner
SUN, YU-HSI DAVID
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Xintec Inc.
OA Round
2 (Final)
77%
Grant Probability
Favorable
3-4
OA Rounds
2y 9m
To Grant
85%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allow Rate
648 granted / 845 resolved
+8.7% vs TC avg
Moderate +8% lift
Without
With
+8.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
27 currently pending
Career history
872
Total Applications
across all art units

Statute-Specific Performance

§101
3.0%
-37.0% vs TC avg
§103
45.9%
+5.9% vs TC avg
§102
25.5%
-14.5% vs TC avg
§112
16.6%
-23.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 845 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1, 2, and 10 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Tu et al. (US PG Pub 2011/0156188, hereinafter Tu). Regarding claim 1, figure 6C of Tu discloses a chip package, comprising: a carrier board (20); a chip (30) located on the carrier board and having a sensing area (321); a light transmissive sheet (95) covering the sensing area of the chip, wherein a sidewall of a top portion of the light transmissive sheet has a protruding portion extending in a horizontal direction; a supporting element (90) located between the light transmissive sheet and the chip and surrounding the sensing area of the chip, wherein the light transmissive sheet is located above the supporting element; and a molding material (50) located on the carrier board and surrounding the chip and the light transmissive sheet, wherein a top surface of the molding material is lower than a top surface of the light transmissive sheet and the entire molding material is located below the protruding portion of the light transmissive sheet.. Regarding claim 2, figure 6C of Tu discloses a top of an edge of the molding material (50) is lower than a position of half a thickness of the light transmissive sheet (95). Regarding claim 10, figure 6C of Tu discloses the carrier board (20) has a conductive pad (211), the chip (30) has a contact electrically connected to the conductive pad of the carrier board by a conductive wire (33), and the conductive wire is located in the molding material (50). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Tu. Regarding claim 3, Tu does not explicitly disclose a thickness of the light transmissive sheet (95) is in a range from 50 µm to 1000 µm, and a thickness of the supporting element (90) is in a range from 40 µm to 250 µkm. However, it would have been obvious to form the claimed elements with thicknesses within the claimed ranges, since it has been held by the Federal circuit that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)). Response to Arguments Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Allowable Subject Matter Claims 4 and 7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU-HSI DAVID SUN whose telephone number is (571)270-5773. The examiner can normally be reached Mon-Fri 8am-4pm ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /YU-HSI D SUN/ Primary Examiner, Art Unit 2817
Read full office action

Prosecution Timeline

May 04, 2023
Application Filed
Nov 04, 2025
Non-Final Rejection — §102, §103
Feb 08, 2026
Response Filed
Mar 24, 2026
Final Rejection — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12604693
METHOD OF MANUFACTURING CHIPS
2y 5m to grant Granted Apr 14, 2026
Patent 12598821
CHIP PACKAGE STRUCTURE AND METHOD FOR PRODUCING THE SAME
2y 5m to grant Granted Apr 07, 2026
Patent 12593717
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
2y 5m to grant Granted Mar 31, 2026
Patent 12581982
BONDING WIRE FOR SEMICONDUCTOR DEVICES
2y 5m to grant Granted Mar 17, 2026
Patent 12582016
SEMICONDUCTOR DEVICE
2y 5m to grant Granted Mar 17, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
77%
Grant Probability
85%
With Interview (+8.4%)
2y 9m
Median Time to Grant
Moderate
PTA Risk
Based on 845 resolved cases by this examiner. Grant probability derived from career allow rate.

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