DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group II in the reply filed on 12/23/2025 is acknowledged. Claims 16-35 are under consideration.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Kamitai et al (US 2007/0241766) in view of Lee et al (US 2017/0125309).
With respect to Claim 16, Kamitai et al discloses a method for forming an integrated chip (Figure 27, formation is inherent as claimed elements are shown) comprising: forming a plurality of input /output structures (Figure 27, 1515) within a test line region (Figure 7, 411 and Figure 27) of a semiconductor workpiece; forming an interconnect structure (Figure 27, 1519) over the semiconductor workpiece; and forming a plurality of electrical I/O structures (Figure 27, 1520) on the interconnect structure and within the test line region, wherein the plurality of electrical I/O structures are laterally adjacent to the plurality of I/O structures. See Figures 4 and 17, and corresponding text, especially paragraph 100.
Kamitai et al differs from the Claims at hand, in that Kamitai et al does not specifically disclose the input/output structures are optical input/output structures.
Lee et al discloses that optical input/output structures are a known input/output structure used in testing semiconductor devices. See paragraphs 13-15.
It would have been obvious to one of ordinary skill in the art, before the effective date of the invention, to use optical input/output structures as the input/output structures of Kamitai et al, for their known benefit as input/output structures in testing semiconductor devices. The use of a known device, for its known benefit, would have been prima facie obvious to one of ordinary skill in the art.
Allowable Subject Matter
Claims 17-24 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The cited references do not anticipate or make obvious inter alia “wherein the semiconductor workpiece comprises a base substrate separated from an active layer by an insulator structure, and wherein forming the plurality of optical I/O structures comprises etching the active layer to form a plurality of grating coupler elements and a grating taper structure within the active layer”.
Claims 25-35 are allowed.
With respect to Claims 25-31, the cited references do not anticipate or make obvious “wherein the one or more optical test devices are optically coupled between the first optical test I/O structure and the second optical test I/O structure; forming a plurality of first optical devices on the semiconductor layer and within a first device region adjacent to the test line region; forming an interconnect structure over the semiconductor substrate, wherein the interconnect structure comprises a plurality of conductive interconnects arranged in a dielectric structure; depositing a passivation structure over the interconnect structure; and forming a plurality of electrical I/O structures in the passivation structure and within the test line region, wherein a first lateral distance between theone or more optical test devices and a first electrical I/O structure in the plurality of electrical I/O structures is less than a second lateral distance between the first and second optical test I/O structures” in combination with the other claimed process steps.
With respect to Claims 32-35, the cited references do not anticipate or make obvious “ wherein the plurality of optical test devices are formed concurrently with the plurality of first optical devices and the plurality of second optical devices, wherein the plurality of optical test devices comprises a modulator having a first doped region; depositing a dielectric structure over the semiconductor substrate; forming a plurality of conductive wires and a plurality of conductive vias in the dielectric structure; and forming a plurality of electrical I/O structures on the dielectric structure and within the test line region, wherein a first electrical I/O structure in the plurality of electrical I/O structures is electrically coupled to the first doped region “ in combination with the other claimed process steps.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDER G GHYKA whose telephone number is (571)272-1669. The examiner can normally be reached Monday-Friday 9-6.
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AGG
February 3, 2026
/ALEXANDER G GHYKA/ Primary Examiner, Art Unit 2812