Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
The following is in response to the communication filed 1/21/2026.
Claims 16-35 are currently pending.
Claims 1-15 have been canceled.
Claims 21-35 have been added.
Claims 16-35 have been examined.
Election/Restriction
Applicant's election without traverse of claims of Invention II which includes original claims 16-20 and new claims 21-35, in the reply filed on 1/21/2026, is acknowledged. Claims 1-15 directed to Invention I have been canceled.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 5/5/2023 and 2/27/2025, are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has been considered by the examiner.
Claim Objections
Claim 17 objected to because of the following informalities, such as missing a comma. Claim 17 should read, “while etching the first capping structure, the hard mask layer has a first etching rate lower than a second etching rate of the first capping structure.”
Appropriate correction is required.
Examiner Initiated Interview
Examiner initiated an interview on 4/3/2026 with Applicant’s Attorney of Record to discuss the amendments to the claims presented below. Examiner explained that after search and consideration the proposed amendments to the claims 16, 25, and 32 below would overcome Hsu et al. US 20230063793 A1 and other art presented in the rejection below, because while the closest prior art, Hsu, has air-gaps/cavities 320a and 320b (See Fig. 3) being adjacent to the first capping structure, it does not appear to show that the air-gap/cavity is surrounding the respective capping structure in the plan view. Applicant was given time to consider the suggested amendments but did not reply either to approve or deny the suggested amendments resulting in rejection of the claims within this action.
Suggested Amendments:
16. A method of forming an integrated chip, comprising:
depositing a thin film resistor (TFR) layer over a semiconductor substrate;
depositing a capping layer on the TFR layer;
performing a first patterning process on the TFR layer and the capping layer to remove peripheral regions of the TFR layer and the capping layer;
performing a second patterning process on the capping layer to form a first capping structure on the TFR layer;
etching the first capping structure to remove an outer portion of the first capping structure; and
forming a dielectric structure over and around the first capping structure such that at least one or more surfaces of the dielectric structure define a first cavity, wherein the first cavity completely surrounds the capping structure in a plan view and the first cavity is adjacent to the first capping structure.
25. A method of forming an integrated chip, comprising:
depositing a first dielectric layer over a semiconductor substrate;
forming a resistor layer on the first dielectric layer;
forming a first conductive structure and a second conductive structure on the resistor layer, wherein a coefficient of temperature expansion (CTE) of the first conductive structure is greater than a CTE of the resistor layer; and
depositing a second dielectric layer over and around the first and second conductive structures, wherein the second dielectric layer comprises a first cavity, wherein the first cavity completely surrounds the capping structure in a plan view and the first cavity is surrounding and adjacent to the first conductive structure, and a second cavity, wherein the second cavity completely surrounds the capping structure in a plan view and the second cavity is surrounding and adjacent to the second conductive structure, wherein a CTE of the first cavity is greater than the CTE of the first conductive structure.
32. A method for forming an integrated chip, comprising:
forming a resistor layer over a semiconductor substrate;
forming a conductive layer over the resistor layer; (this is the capping layer)
forming a hard mask over the conductive layer, wherein the hard mask comprises a first hard mask segment and a second hard mask segment laterally offset from the first hard mask segment;
performing an etching process on the conductive layer to remove an inner region of the conductive layer and form a first conductive structure and a second conductive structure under the first hard mask segment and the second hard mask segment, respectively; and
forming a dielectric layer over the resistor layer, wherein the dielectric layer comprises a first air-gap, wherein the first air-gap completely surrounds the capping structure in a plan view and the first air-gap is and adjacent to the first conductive structure, and a second air-gap, wherein the second air-gap completely surrounds the capping structure in a plan view and the second air-gap is surrounding and adjacent to the second conductive structure, wherein a top of the first air-gap is below a top surface of the first hard mask segment.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 16-17, 21-23, 25-26, 31-32 and 34 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Hsu et al. US 20230063793 A1 (hereinafter Hsu).
The applied reference has a common applicant with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Regarding claim 16, Hsu discloses:
A method of forming an integrated chip, (Hsu, Fig. 5A-10B, method of forming an IC) comprising:
depositing a thin film resistor (TFR) layer (Fig. 5A, resistive layer 502 ) over a semiconductor substrate; (substrate 102)
depositing a capping layer (conductive layer 504) on the TFR layer;
performing a first patterning process on the TFR layer and the capping layer to remove peripheral regions of the TFR layer and the capping layer; (Fig. 6A, [0063], a first patterning process to remove the left and right regions of the resistive layer 502 and the conductive layer 504. Forming resistive structure 112 and first conductive structure 604.)
performing a second patterning process on the capping layer (Fig. 6A, conductive structure 604) to form a first capping structure (Fig 8A, first peripheral portion 804a on the TFR layer (resistive structure 112); (Fig. 8A, [0067], performing a patterning process to form first peripheral portion 804a.)
etching the first capping structure to remove an outer portion of the first capping structure; and (Fig. 9A, etching the conductive structure 802a and forming the conductive contact 114 which has the portion not covered by the hard mask etched away.)
forming a dielectric structure (Fig. 10A, IMD structure 118) over and around the first capping structure (first conductive structure 114a) such that at least one or more surfaces of the dielectric structure define a first cavity (Fig. 10A, first cavity 320a) adjacent to the first capping structure (first conductive structure 114a). (Fig. 10A, [0046], the IMD structure 118 is deposed between the cavities 320.)
Regarding claim 17, Hsu further discloses:
forming a hard mask layer(Fig. 7A, capping layer 702.) over the capping layer(conductive layer 504); and
wherein while etching the first capping structure, ([0061], conductive layer 504 can be titanium nitride) the hard mask layer ([0066], the capping layer can be made of SiN.) has a first etching rate lower than a second etching rate of the first capping structure. (The different materials would by necessity have different etch rates. Furthermore, the capping structure 116, which is made from the capping layer 702, overhangs the conductive structure 802, which is made from the conducive layer 504, after a second etching process which by necessity means that the etch rate of the capping layer 702 is lower than the conductive layer 504.)
Regarding claim 21, Hsu further discloses:
wherein the first cavity is laterally offset from the first capping structure. (See Fig. 10A, first cavity 320a is offset from the first conductive structure in the horizontal direction. )
Regarding claim 22, Hsu further discloses:
wherein the first cavity extends around a perimeter of the first capping structure. (Fig. 10A, first cavity 320a extends around a first side, which can be considered a perimeter, of the first conductive contact 114a.)
Regarding claim 23, Hsu further discloses:
wherein the second patterning process (Fig. 8A, [0067] second patterning process) forms a second capping structure (second conductive contact 114b) on the TFR layer (resistive structure 112) and laterally offset from the first capping structure (Fig. 8A, second conductive contact 114b is laterally offset from first conductive contact 114a), wherein a second cavity (second cavity 320b) is arranged in the dielectric structure and adjacent to the second capping structure, (Fig. 8A, second cavity 320b is adject to second conductive structure 114b) wherein the first cavity and the second cavity are arranged between the first and second capping structures. (See Fig. 8A, first cavity 320a and second cavity 320b are arranged between the first conductive structure 114a and second conductive structure 114b.)
Regarding claim 25, Hsu discloses:
A method of forming an integrated chip, (Hsu, Fig. 5A-10B, method of forming an IC) comprising
depositing a first dielectric layer (Fig. 5A, [0018], IMD 110 being an dielectric) over a semiconductor substrate; (substrate 102)
forming a resistor layer (resistive layer 502 ) on the first dielectric layer; (See Fig. 5A.)
forming a first conductive structure (Fig. 9A, first conductive structure 141a) and a second conductive structure (second conductive structure 114b)on the resistor layer, wherein a coefficient of temperature expansion (CTE) of the first conductive structure ([0021], the conductive structures 114a and 114b are made of titanium nitride (TiN))is greater than a CTE of the resistor layer ([0019], the resistive layer 112is made of silicon chromium (SiCr)); and (The CTE of TiN is greater than the CTE of SiCr.)
depositing a second dielectric layer (Fig. 10A, IMD structure 118) over and around the first and second conductive structures(conductive structures 114a and 114b), (See Fig. 10A) wherein the second dielectric layer comprises a first cavity (Fig. 10A , first cavity 320a) adjacent to the first conductive structure, (first conductive structure 114a) and a second cavity (second cavity 320b) adjacent to the second conductive structure, (second conductive structure 114b) wherein a CTE of the first cavity is greater than the CTE of the first conductive structure. (The CTE of the first cavity would be that of air which would be greater than the CTE TiN of the first conductive structure.)
Regarding claim 26, Hsu further discloses:
performing an etch process to reduce a width of at least a portion of the first conductive structure (Fig. 8A, [0075], first peripheral portion 804a has a width that is reduced by an etching process to make first conductive structure 114a.) and a width of at least a portion of the second conductive structure. (Fig. 8A, [0075], second peripheral portion 804b has a width that is reduced by an etching process to make second conductive structure 114b.)
Regarding claim 31, Hsu further discloses:
forming a first conductive via (Fig. 10A, first conductive via 120a) and a second conductive via (second conductive via 120b) in the second dielectric layer (IMD structure 118), wherein the first conductive via contacts the first conductive structure and the second conductive via contacts the second conductive structure. (See Fig. 10A.)
Regarding claim 32, Hsu discloses:
A method for forming an integrated chip, (Hsu, Fig. 5A-10B, method of forming an IC) comprising:
forming a resistor layer (Fig. 5A, resistive layer 502 ) over a semiconductor substrate; (substrate 102)
forming a conductive layer (conductive layer 504) over the resistor layer;
forming a hard mask (Fig. 8A, first capping structure 116a and second capping structure 116b) over the conductive layer (conductive layer 504), wherein the hard mask comprises a first hard mask segment (first capping structure 116a) and a second hard mask segment laterally offset from the first hard mask segment; (second capping structure 116b)
performing an etching process ([0074], second etching process removes the upper second ion the unmasked portions.) on the conductive layer to remove an inner region of the conductive layer (central portion 806) and form a first conductive structure and a second conductive structure under the first hard mask segment and the second hard mask segment, respectively; and (See Fig. 9A, the first conductive portions 114a and second conductive portions 114b.)
forming a dielectric layer (Fig. 10A, IMD structure 118) over the resistor layer, wherein the dielectric layer comprises a first air-gap (first conductive structure 114a) adjacent to the first conductive structure, (Fig. 10A, first cavity 320a) and a second air-gap (second conductive structure 114b) adjacent to the second conductive structure, (second cavity 320b) wherein a top of the first air-gap is below a top surface of the first hard mask segment. (See Fig. 10A, the air-gap is below the first capping structure.)
Regarding claim 34, Hsu further disclose:
wherein the etching process comprises performing a first etch to reduce a thickness of the inner region (Fig. 8A, [0072], a first etching process which removes the upper portion of the first conductive structure.) and a second etch to remove the inner region, (Fig. 9A, [0074] a second wherein the method further comprises:
forming a spacer structure along sidewalls of the conductive layer before performing the second etch. (Fig. 8A, covered sidewalls that are placed before the second etch.)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 18, 32, and 35 is rejected under 35 U.S.C. 103 as being unpatentable over Hsu in view of Rasmussen et al. US 20050215054 A1 (hereinafter Rasmussen).
Regarding claim 18, Hsu discloses all the elements of claim 16 above.
Hsu further discloses:
wherein etching the first capping structure includes performing a wet etch process, ([0074], the second etching process can be a wet etching process.)
… wherein the first cavity abuts the curved sidewall. (Fig. 10A, first cavity 320a is next to the sidewall that is etched of the first conductive contact 114a.)
Hsu does not specifically disclose:
wherein the first capping structure comprises a curved sidewall,
However, Rasmussen, which teaches wet etching processing for semiconductor device processing (Rasmussen, Abstract), discloses that wet etching when done as an isotropic process would result in a curved sidewall. (Rasmussen, [0061].) Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the device of Hsu would have the first capping structure comprises a curved sidewall as a result of a wet etch process as taught by Rasmussen.
Regarding claim 33, Hsu discloses all the elements of claim 32 above.
Hsu further discloses:
wherein the first conductive structure (Fig. 10A, the first conductive portions 114a) comprises a …. sidewall facing a … sidewall of the second conductive structure. (See Fig. 10A, the etched side wall is facing the second conductive portion 114b.)
Hsu does not specifically disclose:
a slanted or curved sidewall
However, Rasmussen, which teaches wet etching processing for semiconductor device processing (Rasmussen, Abstract), discloses that wet etching when done as an isotropic process would result in a curved sidewall. (Rasmussen, [0061].) Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the device of Hsu would have a curved sidewall as a result of a wet etch process as taught by Rasmussen.
Regarding claim 35, Hsu discloses all the elements of claim 42 above.
Hsu further discloses:
wherein a first segment of the spacer structure overlies a … sidewall of the first conductive structure. (Fig. 10A, a segment of 116a is has an overhang that overlies the sidewall of the first conductive portions 114a.)
Hsu does not specifically disclose:
However, Rasmussen, which teaches wet etching processing for semiconductor device processing (Rasmussen, Abstract), discloses that wet etching when done as an isotropic process would result in a curved sidewall. (Rasmussen, [0061].) Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the device of Hsu would have the first capping structure comprises a curved sidewall as a result of a wet etch process as taught by Rasmussen.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Hsu in view of Singh et al. US 20190385892 A1 (hereinafter Singh).
Regarding claim 19, Hsu discloses all the elements of claim 16 above.
Hsu further discloses:
wherein etching the first capping structure includes performing a dry etch process, ([0074], the second etching process can be a dry etching process.)
… wherein the first cavity abuts the slanted straight sidewall. (Fig. 10A, first cavity 320a is next to the sidewall that is etched of the first conductive contact 114a.)
Hsu does not specifically disclose:
the first capping structure comprises a slanted straight sidewall,
Singh, which teaches a negatively sloped sidewall surface (Singh, Abstract), discloses that dry etching when done as an isotropic process would result in a curved sidewall. (Singh, [0022].) Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the device of Hsu would have the first capping structure comprises a sloped straight sidewall as a result of a dry etch process as taught by Singh as a result of the process being used.
Allowable Subject Matter
Claims 20, 24, 27-29, and 30 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 20, the cited prior art of record does not teach or fairly suggest, along with the other claimed features, a semiconductor device comprising “wherein a height of the first cavity is less than the thickness of the first capping structure.” Closest prior art is Hsu which shows a height of the first cavity is the same as the thickness of the first capping structure.
Regarding claim 24, the cited prior art of record does not teach or fairly suggest, along with the other claimed features, a semiconductor device comprising “wherein a height of the first spacer segment is less than a height of the second spacer segment, wherein the first cavity underlies a bottom surface of the first spacer segment.” Closest prior art is Hsu which shows a spacers structures on the sidewalls of the spacer structure not on the same side as the first cavity (See Fig. 9A and 9B, sides of capping structure 116a along conductive contact 114a.), however it does not show that “a height of the first spacer segment is less than a height of the second spacer segment.”
Regarding claim 27, the cited prior art of record does not teach or fairly suggest, along with the other claimed features, a semiconductor device comprising “performing a third etch to form a first curved sidewall and a second curved sidewall in the conductive layer overlying the inner segment” and “performing a fourth etch to remove the inner segment, wherein the first conductive structure comprises the first curved sidewall and the second conductive structure comprises the second curved sidewall” Closest prior art is Hsu which shows a first etch process [0071] and second etching process [0074], but does not show a third etch and/or a fourth etch.
Claims 28 and 29 have allowable subject matter based on the dependence to claim 27.
Regarding claim 30, the cited prior art of record does not teach or fairly suggest, along with the other claimed features, a semiconductor device comprising “wherein the first conductive structure comprises a straight sidewall vertically stacked with a curved sidewall.”
Rasmussen teaches how to etch a curved sidewall (Rasmussen, [0061]) and Singh teaches how to etch a sloped straight sidewall (Singh, [0022]). Singh further teaches a dry etch to produce a sloped side wall and then the wet etch to expand the trench (Singh, [0022]). However, neither Rasmussen or Singh teach that the straight sidewall is vertically is stacked with curved sidewall.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HEIM KIRIN GREWAL whose telephone number is (703)756-1515. The examiner can normally be reached Monday - Thursday 9:30 a.m. - 5:30 p.m. EST.
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/HEIM KIRIN GREWAL/Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812
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