DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This Office Action is in response to Amendments/Remarks filed on December 29, 2025.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-4 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2014/0219304 A1 to Lee et al. (“Lee”) in view of U.S. Patent Application Publication No. 2012/0168803 A1 to Lee et al. (“Lee3”). As to claim 1, although Lee discloses a light-emitting diode (LED) chip, comprising: an active LED structure (120) comprising an n-type layer (121), a p-type layer (123), and an active layer (122) that is between the n-type layer (121) and the p-type layer (123); and an n-contact interconnect (170, 175) arranged to extend through an opening (at 171) of the p-type layer (123) and the active layer (122) to contact a portion of the n-type layer (121), the n-contact interconnect (170, 175) comprising a contact plug (170) and a first n-contact interconnect segment (175) within the opening (at 171), the contact plug (170) being arranged between the first n-contact interconnect segment (175) and the n-type layer (121) (See Fig. 1, Fig. 2, ¶ 0042-¶ 0047, ¶ 0053-¶ 0056, ¶ 0066, ¶ 0076-¶ 0079), Lee does not further disclose and the contact plug forming a plurality of discontinuous regions on the n-type layer within the opening. However, Lee3 does disclose the contact plug (180, 230) forming a plurality of discontinuous regions (separated at or between 181, 231) on the n-type layer (121, 221) (See Fig. 1, Fig. 16, ¶ 0045, ¶ 0050, ¶ 0057, ¶ 0058, ¶ 0062, ¶ 0094, ¶ 0095, ¶ 0096). In view of the teaching of Lee3, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Lee to have and the contact plug forming a plurality of discontinuous regions on the n-type layer within the opening because improvement of adhesion, excellent thermal stability, and maintained ohmic characteristics of low resistance are obtained to further improve light output (See ¶ 0062, ¶ 0095, ¶ 0096). As to claim 2, Lee in view of Lee3 further discloses wherein the first n-contact interconnect segment (175) contacts the n-type layer (121/121, 221) between adjacent regions of the plurality of discontinuous regions (separated at or between 181, 231) (See Lee Fig. 1, Fig. 2, ¶ 0054 and Lee3 Fig. 1, Fig. 16). As to claim 3, Lee in view of Lee3 further discloses wherein the contact plug (170/180, 230) comprises chromium, aluminum-doped zinc oxide, or indium tin oxide (See Lee ¶ 0076 and Lee3 ¶ 0050). As to claim 4, Lee in view of Lee3 further discloses wherein the contact plug (170/180, 230) has a thickness in a range from 10 angstroms to less than 40 angstroms (See Lee3 ¶ 0057, ¶ 0058). As to claim 14, Lee discloses further comprising a p-contact (150) electrically coupled to the p-type layer (123) and an n-contact (180) electrically coupled to the n-contact interconnect (170, 175), wherein the p-contact (150) and the n-contact (170, 175) are arranged on a same side of the active LED structure (120) (See Fig. 2, ¶ 0044, ¶ 0045).
Claim(s) 1-2, 4-10, 12-14, 16-18, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over JP 2019-134119 A to Toya et al. (“Toya”) in view of U.S. Patent Application Publication No. 2012/0168803 A1 to Lee et al. (“Lee”). As to claim 1, although Toya discloses a light-emitting diode (LED) chip, comprising: an active LED structure comprising an n-type layer (130), a p-type layer (150), and an active layer (140) that is between the n-type layer (130) and the p-type layer (150); and an n-contact interconnect (N1) arranged to extend through an opening of the p-type layer (150) and the active layer (140) to contact a portion of the n-type layer (130), the n-contact interconnect (N1) comprising a first n-contact interconnect segment (N1) within the opening (See Fig. 1, Fig. 2, Fig. 3, Page 2-Page 5), Toya does not further disclose the n-contact interconnect comprising a contact plug and the contact plug being arranged between the first n-contact interconnect segment and the n-type layer and the contact plug forming a plurality of discontinuous regions on the n-type layer within the opening. However, Lee does disclose the n-contact interconnect (180, 230) comprising a contact plug (181, 231) and the first n-contact interconnect segment (182, 183, 184, 232, 233, 234), the contact plug (181, 231) being arranged between the first n-contact interconnect segment (182, 183, 184, 232, 233, 234) and the n-type layer (121, 221) and the contact plug (181, 231) forming a plurality of discontinuous regions (181, 231) on the n-type layer (121, 221) (See Fig. 1, Fig. 16, ¶ 0045, ¶ 0050, ¶ 0057, ¶ 0058, ¶ 0062, ¶ 0094, ¶ 0095, ¶ 0096). In view of the teaching of Lee, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Toya to have the n-contact interconnect comprising a contact plug and the contact plug being arranged between the first n-contact interconnect segment and the n-type layer and the contact plug forming a plurality of discontinuous regions on the n-type layer within the opening because improvement of adhesion, excellent thermal stability, and maintained ohmic characteristics of low resistance are obtained to further improve light output (See ¶ 0062, ¶ 0095, ¶ 0096). As to claim 2, Toya in view of Lee further discloses wherein the first n-contact interconnect segment (N1/182, 183, 184, 232, 233, 234) contacts the n-type layer (130/121, 221) between adjacent regions of the plurality of discontinuous regions (181, 231) (See Toya Fig. 1 and Lee Fig. 1, Fig. 16). As to claim 4, Toya in view of Lee further discloses wherein the contact plug (181, 231) has a thickness in a range from 10 angstroms to less than 40 angstroms (See Lee ¶ 0057, ¶ 0058). As to claim 5, Toya discloses further comprising: a dielectric reflector layer (DBR1) on the p-type layer (150); a metal reflector layer (P1) on the dielectric reflector layer (DBR1); and a plurality of reflective layer interconnects (P1 between DBR1) that extend from the metal reflector layer (P1) and through the dielectric reflector layer (DBR1) to form an electrically conductive path to the p-type layer (150) (See Fig. 1, Page 3) (Notes: at least Ag is reflective). As to claim 6, Toya further discloses wherein the metal reflector layer (P1) and the first n-contact interconnect segment (N1) comprise a same material (See Fig. 2, Pages 3-4). As to claim 7, Toya further discloses wherein the same material comprises silver (See Pages 3-4). As to claim 8, Toya further discloses wherein the first n-contact interconnect segment (N1) forms an extension that laterally extends on the dielectric reflector layer (DBR1) (See Fig. 1).
As to claim 9, Toya discloses further comprising a passivation layer (DBR2) on the metal reflector layer (P1), wherein the extension is between the dielectric reflector layer (DBR1) and the passivation layer (DBR2) (See Fig. 1).
As to claim 10, Toya discloses further comprising a second n-contact interconnect segment (N2) that extends through the passivation layer (DBR2) and is electrically coupled to the first n-contact interconnect segment (N1) (See Fig. 1).
As to claim 12, Toya further discloses wherein a width (above DBR2) of the second n-contact interconnect segment (N2) is greater than a width (middle portion between I1) of the extension of the first n-contact interconnect segment (N1) (See Fig. 1). As to claim 13, Toya discloses further comprising a first barrier layer (N1b) on the extension of the first n-contact interconnect segment (N1) and a second barrier layer (N1c) between the second n-contact interconnect segment (N2) and the first barrier layer (N1b), wherein a width of the second barrier layer (N1c) is greater than a width of the first barrier layer (N1b) (See Fig. 3) (Notes: the barrier layer is a physical barrier layer as no material is specified). As to claim 14, Toya discloses further comprising a p-contact (PA) electrically coupled to the p-type layer (150) and an n-contact (NA) electrically coupled to the n-contact interconnect (N1), wherein the p-contact (PA) and the n-contact (NA) are arranged on a same side of the active LED structure (See Fig. 1). As to claim 16, although Toya discloses a light-emitting diode (LED) chip, comprising: an active LED structure comprising an n-type layer (130), a p-type layer (150), and an active layer (140) that is between the n-type layer (130) and the p-type layer (150); a dielectric reflector layer (DBR1) on the active LED structure; a first n-contact interconnect segment (N1) that extends through an opening of the dielectric reflector layer (DBR1), the p-type layer (150), and the active layer (140) to contact a portion of the n-type layer (130), the first n-contact interconnect segment (N1) forming an extension that laterally extends on a surface of the dielectric reflector layer (DBR1) (See Fig. 1, Fig. 2, Fig. 3, Page 2-Page 5), Toya does not further disclose and a contact plug between the first n-contact interconnect segment and the n-type layer, the contact plug forming a plurality of discontinuous regions on the n-type layer within the opening. However, Lee does disclose and a contact plug (181, 231) between the first n-contact interconnect segment (182, 183, 184, 232, 233, 234) and the n-type layer (121, 221), the contact plug (181, 231) forming a plurality of discontinuous regions (181, 231) on the n-type layer (121, 221) (See Fig. 1, Fig. 16, ¶ 0045, ¶ 0050, ¶ 0057, ¶ 0058, ¶ 0062, ¶ 0094, ¶ 0095, ¶ 0096). In view of the teaching of Lee, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Toya to have and a contact plug between the first n-contact interconnect segment and the n-type layer, the contact plug forming a plurality of discontinuous regions on the n-type layer within the opening because improvement of adhesion, excellent thermal stability, and maintained ohmic characteristics of low resistance are obtained to further improve light output (See ¶ 0062, ¶ 0095, ¶ 0096). As to claim 17, Toya discloses further comprising a passivation layer (DBR2) on the dielectric reflector layer (DBR1), wherein the extension of the first n-contact interconnect segment (N1) is between the passivation layer (DBR2) and the dielectric reflector layer (DBR1) (See Fig. 1). As to claim 18, Toya discloses further comprising a second n-contact interconnect segment (N2) that extends through the passivation layer (DBR2) and is electrically coupled to the first n-contact interconnect segment (N1) (See Fig. 1). As to claim 22, Toya in view of Lee further discloses wherein the first n-contact interconnect segment (N1/182, 183, 184, 232, 233, 234) contacts the n-type layer (130/121, 221) between adjacent regions of the plurality of discontinuous regions (181, 231) (See Toya Fig. 1 and Lee Fig. 1, Fig. 16).
Further, the applicant also has not established the critical nature of the “wherein the contact plug has a thickness in a range from 10 angstroms to less than 40 angstroms”. “The law is replete with cases in which the difference between the claimed invention and the prior art is some range or other variable within the claims….In such a situation, the applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range.” In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir.1990). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention was made to have various ranges. It would also have been obvious to one of ordinary skill in the art at the time the invention was made to discover the optimum or workable ranges by routine experimentations to adjust the thickness to obtain optimized device properties and overall device size. See also In re Huang, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996) (claimed ranges of a result effective variable, which do not overlap the prior art ranges, are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious).
Response to Arguments
Applicant's arguments with respect to claims 1 and 16 have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID CHEN whose telephone number is (571)270-7438. The examiner can normally be reached M-F 12-6.
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/DAVID CHEN/Primary Examiner, Art Unit 2815