Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 9-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sio et al. (US 20190164949 A1; hereinafter “Sio”; cited in the 05/05/2023 IDS).
Regarding independent Claim 9:
Sio discloses in fig. 1A, 2A and [0019-0022], a semiconductor device, comprising:
a first cell row 101-5;
a second cell row 101-4 adjacent with the first cell row;
a third cell row 101-3 adjacent with the second cell row 101-4 and separated from the first cell row 101-5;
a fourth cell row 101-2 adjacent with the third cell row 101-3 and separated from the second cell row101-4; and
a fifth cell row 101-1 adjacent with the fourth cell row 101-2 and separated from the third cell row 101-3,
wherein the third cell row 101-3 has a first row height (e.g., height B) along a first direction Y,
each of the second cell row 101-4, the fourth cell row 101-2 and the fifth cell row 101-1 has a second row height (e.g., height A) along the first direction Y, and
the second row height A is different from the first row height B.
Sio does not expressly disclose wherein the first cell row has the same height as the third cell row along the first direction.
However, it has been held to be within the general skill of a worker in the art to select a height of a cell row in an integrated circuit on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. A person of ordinary skill in the art is motivated to select the first cell row having the same height as the third cell row along the first direction in order to accommodate various circuits, each of which can be used in respective different applications (e.g., a performance-orientated application, a power/area-orientated application, a balance-orientated application, etc.) and by arranging the cell groups 100-1 to 100-5 as shown, the integrated circuit 100 may present a specific characteristic, e.g., a speed-orientated circuit, a balance-orientated circuit, or a power/area-orientated circuit (¶17 and 21 of Sio).
In re claim 10, Sio discloses the semiconductor device of claim 9 outlined above.
Sio does not expressly disclose in fig. 1A, the device further comprising:
a sixth cell row adjacent with the fifth cell row and separated from the fourth cell row; and
a seventh cell row adjacent with the sixth cell row and separated from the fifth cell row,
wherein the sixth cell row and the seventh cell row has the first row height and the second row height, respectively.
However, Sio discloses in the embodiment of fig. 1B, the device comprising:
a sixth cell row row6 adjacent with the fifth cell row row5 and separated from the fourth cell row; and
a seventh cell row row7 adjacent with the sixth cell row and separated from the fifth cell row,
wherein the sixth cell row row6 and the seventh cell row row7 has the first row height A and the second row height B, respectively.
A person of ordinary skill in the art is motivated to incorporate sixth and seventh rows with heights A and B in order to accommodate various circuits, each of which can be used in respective different applications (e.g., a performance-orientated application, a power/area-orientated application, a balance-orientated application, etc.) (¶17 of Sio). It has been held to be within the general skill of a worker in the art to select a height of a cell row in an integrated circuit on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
In re claim 11, Sio discloses in fig. 1A and 2A, the semiconductor device of claim 9, wherein the second cell row 101-4 comprises a first fin shaped structure 252-1, a second fin shaped structure 252-2, a third fin shaped structure 252-3 and a fourth fin shaped structure 252-4 separated from each other (¶31).
In re claim 12, Sio discloses in fig. 1A and 2A, the semiconductor device of claim 11, wherein each of the first fin shaped structure 252-1 and the second fin shaped structure 252-2 has a first conductive type (e.g., n-type; ¶38), and each of the third fin shaped structure 252-3 and the fourth fin shaped structure 252-4 has a second conductive type different from the first conductive type (e.g., p-type; ¶38).
In re claim 13, Sio discloses in fig. 1A and 2A, the semiconductor device of claim 12, wherein the first cell row (e.g., row 6 in fig. 2A) comprises a fifth fin shaped structure 262-1 and a sixth fin shaped structure 262-2 separated from each other, and the fifth fin shaped structure 262-1 and the sixth fin shaped structure 262-2 have the first conductive type (i.e., n-type) and the second conductive type (i.e., p-type), respectively (¶39).
Claim(s) 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sio, as applied to claim 9 above and further in view of Gheewala et al. (US 7129562 B1; hereinafter “Gheewala”) (Gheewala has been cited in the 02/06/2025 IDS).
In re claim 14, Sio discloses in fig. 1A and 2A-2B, the semiconductor device of claim 9, further comprising:
a first power rail (e.g., anyone of the power rails 270-1 through 7; ¶42) disposed at a first boundary between the fifth cell row 101-1 and the fourth cell row 101-2;
a second power rail (e.g., anyone of the power rails 270-1 through 7; ¶42) disposed at a second boundary between the third cell row 101-3 and the fourth cell row 101-2; and
a third power rail (e.g., anyone of the power rails 270-1 through 7; ¶42) disposed at a third boundary between the third cell row 101-3 and the second cell row 101-4.
Sio does not expressly disclose wherein first power rail has a first width, and each of the third power rail and the second power rail has a second width smaller than the first width.
In the same field of endeavor, Gheewala discloses a semiconductor device (fig. 4), comprising:
wherein a first power rail has a first width 410, and each of a third power rail 350 and a second power rail 350 has a second width smaller than the first width (“A double-wide VDD conductive trace 410 is also included and is twice the width of conductive traces 340 and 350”; Col. 5th and 6th, lats and 1st paragraphs, respectively).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Gheewala into the device of Sio to efficiently supply power to high power applications such as graphic circuits (Col. 5th and 6th, lats and 1st paragraphs, respectively of Gheewala).
In re claim 15, Sio, as modified by Gheewala, discloses the semiconductor device of claim 14, further comprising:
a fourth power rail (e.g., anyone of the power rails 270-1 through 7 in fig. 2B of Sio; ¶42) disposed at a fourth boundary between the second cell row 101-4 (Sio: fig. 1A) and the first cell row 101-5 (Sio: fig. 1A), and having the second width (as taught by Gheewala, width 350).
Claim(s) 16-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20200050728 A1; hereinafter “Kim1”; cited in the 05/05/2023 IDS) in view of Kim et al. (US 20160300851 A1; hereinafter “Kim2”) and Sio et al. (US 20190164949 A1; hereinafter “Sio”).
Regarding independent Claim 16:
Kim discloses in fig. 3A, a semiconductor device, comprising:
a first cell row R23 having a first row height along a first direction Y (¶29);
a second cell row R21 having the first row height along the first direction Y (¶21, 29);
a third cell row R22 having a second row height along the first direction Y, disposed between the first cell row R23 and the second cell row R21, and adjacent with each of the first cell row and the second cell row;
a second integrated circuit cell C36a disposed in the first cell row R23 and the third cell row R22 (¶32);
a third integrated circuit cell C35a disposed in the first cell row R23 (¶32); and
a fourth integrated circuit cell C34a disposed in the third cell row R22 and adjacent with the third integrated circuit cell C35a (¶32).
Kim teaches integrated circuit cells can be multi-height cells, but does not teach a first integrated circuit cell disposed in the first cell row, the second cell row and the third cell row; and wherein the first row height is different from the second row height.
In the same field of endeavor, Kim2 discloses in fig. 19, a semiconductor device, comprising: multi-height cells, wherein a first integrated circuit cell SC2 disposed in a first cell row AR3, a second cell row AR1 and a third cell row AR2 (¶62, 95).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to incorporate a multi-height first integrated circuit cell in Kim1 to efficiently accommodate relatively large-sized standard cells employing the circuit design technique taught by Kim2 without increasing size of a semiconductor device and meeting (¶2-4 of Kim2).
Kim1, as modified by Kim2, does not expressly disclose wherein the first row height is different from the second row height.
In the same field of endeavor, Sio discloses in figs. 1A, 2, 5, a semiconductor device, comprising:
first cell rows (rows with height A, e.g., row 1, row2, row4, row5; hereinafter “Row-A”) having a first row height (A) (fig. 1A; ¶ 0019-0021); and
second cell rows (rows with height B, e.g., row 3; hereinafter “Row-B”) having a second row height B (figs. 1A, 5; ¶ 0019-0021, 0026, 0072),
wherein the first row height A is different from the second row height B (¶ 0019-0022, 0025-0027, 0072).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Sio into the method of Kim1/Kim2.
One would have been motivated to do so as Sio teaches the cell that has a higher number of active regions having greater height may present higher performance (e.g., a faster speed) over the cell that has a lower number of active regions having smaller height, while the cell that has a lower number of active regions may occupy a smaller area, which typically presents lower power consumption as well, over the cell that has a higher number of active regions (¶ 0025 of Sio).
In re claim 17, Kim1, as modified by Kim2 and Sio, discloses the semiconductor device of claim 16 outlined above.
Kim1 further discloses in fig. 3A, the semiconductor device of claim 16, further comprising: a fifth integrated circuit cell C32a disposed in the second cell row R21 and adjacent with each of the fourth integrated circuit cell C34a and the second integrated circuit cell C36a.
Allowable Subject Matter
Claims 1-8 are allowed.
Claim 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The cited prior art of record, Lim et al. (US 20200051977 A1; hereinafter “Lim”; cited in the 08/08/2025 IDS), Sio et al. (US 20190164949 A1; hereinafter “Sio”), Kim et al. (US 20200050728 A1; hereinafter “Kim”) have been found to be the closest prior art.
Regarding independent Claim 1:
Lim discloses in figs. 9A-9B, a semiconductor device, comprising:
a first cell row R92 having a first row height along a first direction Y (¶54);
a second cell row R91 adjacent with the first cell row R92, and having a second row height along the first direction Y;
a first fin shaped structure F10 extending across the first cell row R92;
a second fin shaped structure F09 extending across the first cell row R92, and separated from the first fin shaped structure F10;
a third fin shaped structure F08 extending across the second cell row R91; and
a fourth fin shaped structure F07 extending across the second cell row R91, and separated from the third fin shaped structure F08,
wherein the first fin shaped structure F10, the second fin shaped structure F09, the third fin shaped structure F08 and the fourth fin shaped structure F07 are arranged in order along the first direction Y.
Lim, alone or in combination with other prior art, does not teach each of the first fin shaped structure, the second fin shaped structure and the fourth fin shaped structure has a first conductive type, the third fin shaped structure has a second conductive type different from the first conductive type; and the first row height is different from the second row height.
Dependent claims 2-8 are indicated allowable for the same reasons as cited for claim 1.
Regarding claim 18, closest prior art of record, alone or in combination, does not expressly disclose a fourth cell row having the first row height along the first direction, and adjacent with the second cell row; a fifth integrated circuit cell disposed in the fourth cell row and adjacent with the first integrated circuit cell; and a sixth integrated circuit cell disposed in the second cell row and adjacent with each of the fifth integrated circuit cell and the second integrated circuit cell, in combination with other limitations cited in claim 16.
Regarding claim 19, closest prior art of record, alone or in combination, does not expressly disclose a fourth cell row having the first row height along the first direction, and adjacent with the first cell row; a fifth integrated circuit cell disposed in the fourth cell row and adjacent with each of the second integrated circuit cell and the third integrated circuit cell; and a sixth integrated circuit cell adjacent with the fifth integrated circuit cell, wherein a height of the sixth integrated circuit cell is approximately equal to a height of the first integrated circuit cell, in combination with other limitations cited in claim 16.
Dependent claim 20 is indicated allowable for the same reason as cited for claim 19.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NILUFA RAHIM whose telephone number is (571)272-8926. The examiner can normally be reached M-F 9am-5:30pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara J. Green can be reached on (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/NILUFA RAHIM/Primary Examiner, Art Unit 2893